JP2014142253A - Testing support method, testing support program, and testing support device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently test a circuit.SOLUTION: A testing support device 100 derives a second period of a clock shorter than a first period allowing a circuit to perform a test operation, on the basis of a timing analysis result 101 of signals within the circuit, which is obtained by causing the circuit to perform the test operation with the clock of the first period. The testing support device 100 derives a third period of the clock shorter than the first period without exceeding an upper limit value 103 of the current consumption of the circuit, on the basis of an analysis result 102 of the current consumption of the circuit, which is obtained by causing the circuit to perform the test operation with the clock of the first period. The testing support device 100 derives a fourth period equal to or longer than longer one of the derived second and third periods and shorter than the first period.

Description

  The present invention relates to a test support method, a test support program, and a test support apparatus.

  Conventionally, a circuit is designed so that a test operation can be performed in addition to the operation after shipment. In addition, for example, there is a technique that guarantees the delay characteristics of a circuit by simulation at the time of circuit design and inspection of a test circuit in the circuit (for example, see Patent Document 1 below). In addition, there is a technique in which a clock cycle for a high-impedance test pattern corresponding to each tester is obtained by logic simulation of a circuit (see, for example, Patent Document 2 below).

JP-A-6-348774 JP 2000-132572 A

  However, if the clock period during the test operation of the circuit is fast, the test operation may not be performed. If the clock period during the test operation is slow, the test time becomes long. For this reason, there exists a problem that a test cannot be performed efficiently.

  In one aspect, an object of the present invention is to provide a test support method, a test support program, and a test support apparatus that can improve the efficiency of circuit testing.

  According to one aspect of the present invention, the circuit executes the test operation based on a timing analysis result of a signal in the circuit when the circuit performs a test operation by the first clock of the first period. Deriving a second period of the second clock that is shorter than the possible first period, and analyzing the amount of current consumption of the circuit when the circuit performs the test operation by the first clock of the first period Based on the result, the third period of the third clock that is shorter than the first period without exceeding the upper limit value of the current consumption of the circuit is derived, and the longer one of the derived second period and the third period is derived. A test support method, a test support program, and a test support apparatus for deriving the fourth period of the fourth clock equal to or greater than the period are proposed.

  According to one embodiment of the present invention, the efficiency of circuit testing can be improved.

FIG. 1 is an explanatory diagram illustrating an example in which the timing margin is improved by the first embodiment. FIG. 2 is an explanatory diagram illustrating a circuit example. FIG. 3 is an explanatory diagram illustrating an example of timing analysis. FIG. 4 is an explanatory diagram showing an example of the capture operation. FIG. 5 is an explanatory diagram showing an example of the shift operation. FIG. 6 is a block diagram of a hardware configuration example of the test support apparatus according to the first embodiment. FIG. 7 is a block diagram of a functional configuration example of the test support apparatus according to the first embodiment. FIG. 8 is an explanatory diagram showing an example of timing constraint information. FIG. 9 is an explanatory diagram illustrating an example of a timing analysis result. FIG. 10 is an explanatory diagram of an example of derivation of the second period according to the first embodiment. FIG. 11 is an explanatory diagram of a second cycle derivation result example according to the first embodiment. FIG. 12 is an explanatory diagram illustrating an example of an analysis result of the current consumption amount. FIG. 13 is an explanatory diagram of an example of deriving the third period according to the first embodiment. FIG. 14 is an explanatory diagram of an example of a third period derivation result according to the first embodiment. FIG. 15 is a flowchart of a processing procedure example performed by the test support apparatus according to the first embodiment. FIG. 16 is a flowchart of an example of a test program generation process procedure according to the first embodiment. FIG. 17 is a block diagram of a functional configuration example of the test support apparatus according to the second embodiment. FIG. 18 is an explanatory diagram of an example of a change in the margin according to the second embodiment. FIG. 19 is an explanatory diagram of a second cycle derivation result example according to the second embodiment. FIG. 20 is a flowchart of an example of a processing procedure performed by the test support apparatus according to the second embodiment. FIG. 21 is a flowchart of a test program generation processing procedure example according to the second embodiment.

  Exemplary embodiments of a test support method, a test support program, and a test support apparatus according to the present invention will be explained below in detail with reference to the accompanying drawings. This embodiment will be described separately in the first embodiment and the second embodiment. In the first embodiment, a period earlier than the first period that satisfies the condition of the amount of current and the timing of the signal is derived from the analysis result of the amount of current and the timing of the signal in the circuit test operation using the clock of the first period. . In the second embodiment, based on the analysis result of the current amount after the layout is changed so that a part of the signal timing satisfies the condition by the analysis result of the signal timing in the circuit test operation by the clock of the first cycle. A period earlier than the first period that satisfies the condition of the current amount is derived.

(Embodiment 1)
FIG. 1 is an explanatory diagram illustrating an example in which the timing margin is improved by the first embodiment. The test support apparatus 100 is a computer that determines an optimal clock cycle for a circuit test operation. For example, the circuit test operation includes a capture operation and a scan operation. Detailed examples of the circuit, the capture operation, and the scan operation will be described later.

  First, the test support apparatus 100 has a first cycle in which the circuit can execute the test operation based on the timing analysis result 101 of the signal in the circuit when the circuit performs the test operation by the first cycle clock. Deriving the second period of the shorter clock. A detailed derivation example of the second period will be described later with reference to FIGS. 10 and 11. The first period is the reciprocal of the clock frequency predetermined by a circuit designer or the like. The first period is stored in advance in a storage device accessible by the test support apparatus 100. In the first embodiment, the first period is included in the timing constraint information described later with reference to FIG.

  Next, the test support apparatus 100 exceeds the upper limit value 103 of the current consumption amount of the circuit based on the analysis result 102 of the current consumption amount of the circuit when the circuit performs the test operation by the clock of the first cycle. First, the third period of the clock shorter than the first period is derived. A detailed derivation example of the third period will be described later with reference to FIGS. 13 and 14. For example, the upper limit value 103 is stored in advance in a storage device accessible by the test support apparatus 100. Further, for example, with respect to the upper limit value 103, when the current consumption amount of the circuit exceeds the upper limit value 103, the consumption is such that the circuit operates abnormally or other circuits connected to the circuit operate abnormally. The amount of current, which is determined in advance by a circuit designer or the like.

  Then, the test support apparatus 100 derives a fourth period that is equal to or longer than the longer one of the derived second period and third period and is shorter than the first period. For example, the test support apparatus 100 may set the longer cycle of the second cycle and the third cycle as the fourth cycle, or a value obtained by adding a margin to the longer cycle of the second cycle and the third cycle. May be the fourth period. Then, the test support apparatus 100 generates a test program for the test operation to be given to the tester with the fourth period as the clock period.

  Thus, an earlier clock cycle is utilized during the test operation in the clock cycle that is in accordance with the test operation. Therefore, the clock cycle during the test operation can be optimized, and the efficiency of the circuit test can be improved. The graph g11 in the example of FIG. 1 shows the timing analysis result in the first period, and the graph g12 shows the timing analysis result in the derived fourth period. By optimizing the clock cycle, the margin indicating how much the timing change of each signal has a margin with respect to the clock cycle can be brought close to zero. Specifically, the margin is a time obtained by subtracting the delay time of the path signal from the first period.

  Here, before detailed description by the test support apparatus 100, the circuit, timing analysis, and circuit test operation will be briefly described with reference to FIGS.

  FIG. 2 is an explanatory diagram illustrating a circuit example. For example, the circuit 200 includes a plurality of flip-flops and a combinational circuit. The flip-flop is hereinafter referred to as FF (Flip Flop). The FF communicates with an external circuit via the external terminal of the circuit 200. In addition, data is exchanged between FFs directly or via a combinational circuit.

  In the timing analysis, a timing shift in the data transfer between the two FFs is estimated based on the type of element, the capacitance of the wiring, and the like. The timing shift is, for example, a delay amount of a signal of each path caused by an element or wiring. Here, the path indicates a path from the external input terminal of the circuit 200 to the FF, a path from the FF to the FF, and a path from the FF to the external output terminal of the circuit 200. In the timing analysis, an analysis is performed as to whether or not the signal of each path complies with the setup time and the hold time by the first cycle clock. As a result, a margin indicating how much margin is available for the first period within a range in which the path signal can comply with the setup time and hold time is derived for each path.

  FIG. 3 is an explanatory diagram illustrating an example of timing analysis. For example, the more combinational circuits are included on the path connecting the FFs, the less margin is given to the timing in the clock with the specified period.

  FIG. 4 is an explanatory diagram showing an example of the capture operation. The capture operation refers to an operation of taking test data into a scan test FF in the circuit 200 during a scan test of the circuit 200.

  FIG. 5 is an explanatory diagram showing an example of the shift operation. The shift operation is an operation for shifting test data from one FF to the next FF during a scan test. The connection relationship between the FFs for scan test connects the FFs for scan test. The connection order of the scan paths may be determined regardless of the logic of the circuit 200. When connecting the scan paths of the large-scale circuit 200, the wiring length of the scan path is shorter when the FFs that are as close as possible are connected than when the FFs that are far from each other in the layout are connected. However, there is a possibility that distant FFs are connected.

  In addition, since the FFs having a connection relationship are different in the product operation, the capture operation, and the scan operation, the timing analysis result 101 is also different for each operation. Therefore, the test may be performed with a clock having a different period for each operation. Here, the product operation indicates an operation when used by a user.

(Hardware configuration example of test support apparatus 100)
FIG. 6 is a block diagram of a hardware configuration example of the test support apparatus according to the first embodiment. In FIG. 6, the test support apparatus 100 includes a CPU 601, a ROM 602, a RAM 603, a disk drive 604, and a disk 605. The test support apparatus 100 includes an I / F 606, an input device 607, and an output device 608. Each unit is connected by a bus 600.

  Here, the CPU 601 governs overall control of the test support apparatus 100. The ROM 602 stores programs such as a boot program. The RAM 603 is used as a work area for the CPU 601. The disk drive 604 controls reading / writing of data with respect to the disk 605 according to the control of the CPU 601. The disk 605 stores data written under the control of the disk drive 604. Examples of the disk 605 include a magnetic disk and an optical disk.

  The I / F 606 is connected to a network NET such as a LAN (Local Area Network), a WAN (Wide Area Network), and the Internet through a communication line, and is connected to other devices via the network NET. The I / F 606 controls an internal interface with the network NET, and controls data input / output from an external device. For example, a modem or a LAN adapter may be employed as the I / F 606.

  The input device 607 is an interface for inputting various data by a user operation such as a keyboard, a mouse, and a touch panel. The input device 607 can also capture images and moving images from the camera. The input device 607 can also capture audio from a microphone. The output device 608 is an interface that outputs data in accordance with an instruction from the CPU 601. Examples of the output device 608 include a display and a printer.

(Functional configuration example of the test support apparatus 100 according to the first embodiment)
FIG. 7 is a block diagram of a functional configuration example of the test support apparatus according to the first embodiment. The test support apparatus 100 includes a timing analysis unit 701, a current consumption amount analysis unit 702, a first derivation unit 703, a second derivation unit 704, a third derivation unit 705, and a fourth derivation unit 706. . The processing of each unit is coded in, for example, a test support program stored in a storage device accessible by the CPU 601. Then, the CPU 601 reads the test support program from the storage device and executes the process coded in the test support program. Thereby, the process of each part is implement | achieved. Further, the processing results of each unit are stored in a storage device such as the RAM 603 and the disk 605, for example.

  The timing analysis unit 701 analyzes a timing change of a signal in the circuit 200 when the circuit 200 is caused to perform a test operation by the first cycle clock. Specifically, the timing analysis unit 701 performs analysis based on a net list indicating a connection relationship between elements of the circuit 200 and a wiring capacity based on the layout data 710. The first period is determined by the designer or verifier of the circuit 200, and may be stored in the storage device such as the disk 605 as the timing constraint information 711, or may be input via the input device 607. .

  FIG. 8 is an explanatory diagram showing an example of timing constraint information. The timing constraint information 711 is a table having a clock cycle determined for each operation of the circuit 200. The timing constraint information 711 has fields of operation and period, and information is set in each field, and is stored as a record. The timing constraint information 711 is stored in a storage device such as the RAM 603 and the disk 605, for example.

  For example, in the shift operation, the clock cycle is 100 [ns], in the capture operation, the clock cycle is 10 [ns], and in the product operation A, the clock cycle is 5 [ns]. In the case of the product operation B, the clock cycle is 2 [ns].

  Further, as described above, in the timing analysis, a timing shift in the data transfer between the two FFs is estimated based on the type of element, the capacitance of the wiring, and the like. Further, as described above, in the timing analysis, it is analyzed whether or not the signal of each path complies with the setup time and the hold time by the clock of the first period. As a result, a margin indicating how much margin is available for the first period within a range in which the path signal can comply with the setup time and hold time is derived for each path. In addition, if the signal of each path does not comply with the setup time and hold time due to the clock of the first cycle, the positional relationship of the wiring indicating the path of the signal determined not to comply and the element to which the path is connected is changed. The layout data 710 thus generated is generated. Then, the timing analysis by the timing analysis unit 701 is performed again based on the changed layout data 710.

  FIG. 9 is an explanatory diagram illustrating an example of a timing analysis result. The timing analysis result 101 includes the signal margin of the path in the circuit 200 for each operation. In FIG. 9, the shortest margin among the signal margins of the path in the circuit 200 is shown for each operation. The timing analysis result 101 is stored in a storage device such as the ROM 602, the RAM 603, and the disk 605, for example.

  For example, the margin is 50 [ns] for the shift operation, the margin is 1 [ns] for the capture operation, and the margin is 0.02 [ns] for the product operation A. In the case of product operation B, the margin is 0.01 [ns].

  The first deriving unit 703 allows the circuit 200 to execute the test operation based on the timing analysis result 101 of the signal of the path in the circuit 200 when the circuit 200 performs the test operation with the first cycle clock. The second period of the clock shorter than the first period is derived. As the test operation, as described above, the scan operation by the flip-flop in the circuit 200 and the capture operation of the flip-flop in the circuit 200 can be cited.

  FIG. 10 is an explanatory diagram of an example of derivation of the second period according to the first embodiment. FIG. 11 is an explanatory diagram of a second cycle derivation result example according to the first embodiment. As shown in FIG. 10, the cycle can be shortened by the shortest margin among the margins of signals in the circuit 200. Therefore, the first deriving unit 703 derives the second period by the following equation (1).

  Second period = period of timing constraint information 711−shortest margin included in the timing analysis result 101 (1)

  In the example of FIG. 11, the second period is “100 [ns] −50 [ns]”, which is 50 [ns].

  Based on the layout data 710, the current consumption amount analysis unit 702 analyzes the current consumption amount of the circuit 200 when the circuit 200 is caused to perform a test operation using the first cycle clock. The analysis of the consumption current amount by the consumption current amount analysis unit 702 is performed by, for example, a current analysis tool.

  Next, the second deriving unit 704 does not exceed the upper limit value 103 based on the analysis result 102 of the current consumption amount of the circuit 200 when the circuit 200 is caused to perform the test operation by the clock of the first period. A third period of the clock shorter than the period is derived. As described above, the upper limit value 103 is determined based on product specifications and the like, and is stored in advance in a storage device such as the ROM 602, the RAM 603, and the disk 605.

  FIG. 12 is an explanatory diagram illustrating an example of an analysis result of the current consumption amount. The current consumption amount analysis result 102 includes, for each operation, a current consumption amount in a portion related to the operation in the circuit 200 and a current consumption amount in a portion other than the operation in the circuit 200. The analysis result 102 of the consumption current amount in FIG. 12 includes the quiescent current of the circuit 200, the consumption current amount of the circuit 200 related to the shift operation in the circuit 200, and the consumption current of the circuit 200 other than the shift operation in the circuit 200. Amount. As described above, the current consumption amount analysis result 102 is stored in a storage device such as the ROM 602, the RAM 603, and the disk 605, for example.

  For example, the quiescent current is 100 [mA], and the current amount of the shift target circuit regarding the shift operation is 70 [mA]. Further, for example, assuming that the circuit 200 has a small amount of operating current other than the shift operation, the operating current amount of the non-shift target circuit is 0 [mA].

  FIG. 13 is an explanatory diagram of an example of deriving the third period according to the first embodiment. FIG. 14 is an explanatory diagram of an example of a third period derivation result according to the first embodiment. As shown in FIG. 13, the upper limit value 103 is not exceeded when the amount of operating current for the shift operation increases. Therefore, the second derivation unit 704 calculates the third period by the following equation (2).

  Third period = period of timing constraint / ((upper limit value 103−static current amount−current amount of circuit 200 other than shift operation) / operating current amount of shift operation) (2)

  In the example of FIG. 14, the third period is “100 [ns] / ((200 [mA] −100 [mA] −0 [mA]) / 70 [mA])”, which is about 70 [ns]. is there.

  The third deriving unit 705 derives a fourth period that is equal to or longer than the longer one of the derived second period and third period and shorter than the first period. For example, the third deriving unit 705 sets the longer one of the derived second period and the derived third period as the fourth period. Since the second period is 50 [ns] and the third period is 70 [ns], the fourth period is 70 [ns].

  Alternatively, for example, the third deriving unit 705 sets a cycle obtained by adding a margin within a range not exceeding the first cycle to the longer cycle of the derived second cycle and the derived third cycle. It is good also as a period. Since the second period is 50 [ns] and the third period is 70 [ns], the margin may be 5 [ns] and the fourth period may be 75 [ns].

  In the above example, the shift operation is taken as an example, but the capture operation may be performed in the same manner. The clock cycle may be different between the shift operation and the capture operation.

  A case where the clock period is the same in the shift operation and the capture operation will be described. Here, for example, the first test operation is a shift operation, and the second test operation is a capture operation. The derivation of the clock cycle for the shift operation is the second cycle and the third cycle described above. The fourth deriving unit 706 derives the fifth period of the clock shorter than the first period in which the circuit 200 can execute the capture operation, based on the timing analysis result 101 of the signal in the circuit 200 when the capture operation is performed. To do. For example, the fifth period is “10 [ns] −1 [ns]”, which is 9 [ns].

  Then, the third deriving unit 705 derives a fourth period that is equal to or longer than the longest period of the derived second period, the third period, and the fifth period and is shorter than the first period. For example, the third deriving unit 705 sets the longest period among the derived second period, the derived third period, and the derived fifth period as the fourth period. As described above, the second period in the shift operation is 50 [ns], the third period in the shift operation is 70 [ns], and the fifth period in the capture operation is 9 [ns]. Therefore, for example, the fourth period is 70 [ns].

  Or, for example, the third deriving unit 705 adds a margin to the longest period among the derived second period, the derived third period, and the derived fifth period in a range not exceeding the first period. The cycle may be the fourth cycle. For example, the margin may be 5 [ns] and the fourth period may be 75 [ns].

(Example of processing procedure performed by the test support apparatus 100 according to the first embodiment)
FIG. 15 is a flowchart of a processing procedure example performed by the test support apparatus according to the first embodiment. The test support apparatus 100 performs capacity extraction based on the net list 1501, the layout data 710, and the wiring configuration specification information 1502 (step S1501). The netlist 1501 is information indicating the connection relationship of elements in the circuit 200, and is described by a hardware description language such as Verilog or VHDL (Very high speed integrated hardware Description Language) or a system description language, for example. The wiring configuration specification information 1502 includes information on wiring layers used in the layout data 710, rules for layout design such as a pitch between wirings, and the like.

  Next, the test support apparatus 100 performs delay calculation based on the wiring capacity information 1503, the IP library 1504, and the netlist 1501 (step S1502). Then, the test support apparatus 100 performs timing analysis based on the wiring delay information 1505 that is the delay calculation result, the timing constraint information 711, and the test program 1506 (step S1503). The test support apparatus 100 determines whether or not the timing analysis result 101 satisfies the timing constraint (step S1504). For example, if the margin for all signals in the circuit 200 is 0 or more, it is determined that the timing constraint is satisfied.

  When the timing analysis result 101 does not satisfy the timing constraint (step S1504: No), the test support apparatus 100 corrects the layout (step S1505) and returns to step S1501. When the timing analysis result 101 satisfies the timing constraint (step S1504: Yes), the process proceeds to step S1506 and step S1507. Next to Yes in step S1504, the test support apparatus 100 performs physical verification (step S1506) and ends a series of processes.

  Further, next to Yes in step S1504, the test support apparatus 100 performs a test program generation process (step S1507) and ends a series of processes. Then, the test program 1507 generated by the test program generation process is given to the tester, and the circuit 200 is tested.

  FIG. 16 is a flowchart of an example of a test program generation process procedure according to the first embodiment. The test support apparatus 100 derives the second period based on the timing analysis result 101 and the timing constraint information 711 (step S1601), and proceeds to step S1606. For example, in step S <b> 1601, the test support apparatus 100 performs “second period = first period during shift operation−room margin during shift operation”.

  Further, the test support apparatus 100 performs logic simulation based on the test program 1506, the IP library 1504, and the netlist 1501 (step S1602). Then, the test support apparatus 100 analyzes the amount of current consumption based on the circuit operation information obtained by the logic simulation and the wiring capacity information 1503 obtained by the above-described capacity extraction (step S1603). The test support apparatus 100 derives the third period based on the current consumption amount analysis result 102 and the timing constraint information 711 (step S1604), and proceeds to step S1606. For example, in step S1604, the test support apparatus 100 determines that “third period = period of timing constraint / ((upper limit 103−static current amount−operating current amount of the circuit 200 other than the shift operation) / operating current amount of the shift operation”. )"I do.

  Also, the test support apparatus 100 derives the fifth period based on the timing analysis result 101 and the timing constraint information 711 (step S1605), and proceeds to step S1606. For example, in step S <b> 1605, the test support apparatus 100 performs “5th cycle = first cycle during capture operation−allowance during capture operation”.

  Then, after step S1601, step 1604, and step S1605, the test support apparatus 100 derives a fourth period that is longer than the longest period among the second period, the third period, and the fifth period (step S1606). ). Then, the test support apparatus 100 outputs the fourth period (step S1607), and gives the fourth period to the ATPG to generate the test program 1507 (step S1608).

  According to the test support apparatus 100 described in the first embodiment, the power consumption amount and the signal timing are calculated based on the analysis result of the power consumption amount and the signal timing in the circuit test operation using the first cycle clock. A period earlier than the first period that satisfies the condition is derived. Thus, an earlier clock cycle is utilized during the test operation in the clock cycle that is in accordance with the test operation. Therefore, the clock cycle during the test operation can be optimized, and the efficiency of the circuit test can be improved.

  The test operation is a shift operation or a capture operation. This optimizes the clock period for each test operation.

  Further, the power consumption and signal timings in the plurality of test operations are determined based on the power consumption and signal timing analysis results in the first test operation and the signal timing analysis results in the second test operation. A period that satisfies is derived. As a result, among the clock cycles in which any of the plurality of test operations can be performed, an earlier clock cycle is used during the test operation. Therefore, the efficiency of the circuit test can be improved.

  In addition, since the first test operation is a shift operation and the second test operation is a capture operation, it is possible to derive a period that satisfies the power consumption for the shift operation that is estimated to have a large amount of power consumption. it can.

(Embodiment 2)
In the second embodiment, based on the timing analysis result 101 based on a predetermined clock cycle, the clock cycle is corrected to a strict condition, and layout data that satisfies the corrected clock cycle is generated. In the second embodiment, the clock cycle of the test operation is calculated by calculating the clock cycle so that the current consumption amount does not exceed the upper limit value 103 based on the analysis result 102 of the current consumption amount based on the generated layout data. Optimize the period. In the second embodiment, the same parts as those described in the first embodiment are denoted by the same reference numerals, and illustration and description thereof are omitted.

(Example of Functional Configuration of Test Support Device According to Second Embodiment)
FIG. 17 is a block diagram of a functional configuration example of the test support apparatus according to the second embodiment. The test support apparatus 1700 includes a timing analysis unit 1701, a current consumption amount analysis unit 1702, a generation unit 1704, a first derivation unit 1703, a second derivation unit 1705, and a third derivation unit 1706. The processing of each unit is coded in, for example, a test support program stored in a storage device accessible by the CPU 601. Then, the CPU 601 reads the test support program from the storage device and executes the process coded in the test support program. Thereby, the process of each part is implement | achieved. Further, the processing results of each unit are stored in a storage device such as the RAM 603 and the disk 605, for example.

  The timing analysis unit 1701 performs timing analysis using the first layout data 710. Based on the timing analysis result 101, the first deriving unit 1703 derives the second period of the clock shorter than the first period in which some signals in the circuit 200 are in the test operation. The timing analysis result 101 in the second embodiment is the timing analysis result 101 based on the first layout data 710, and the timing of the signal in the circuit 200 when the circuit 200 is caused to execute the test operation by the first cycle clock. This is an analysis result 101.

  FIG. 18 is an explanatory diagram of an example of a change in the margin according to the second embodiment. A graph 1800 shows a distribution of signal margin in the circuit 200 when the circuit 200 is caused to perform a test operation by the first cycle clock. The vertical axis is the number of signal paths, and the horizontal axis is the margin.

  Here, for example, in the distribution shown in the graph 1801 regarding the signal margin of each path, a path having a margin that is shorter than the margin including the number of paths of 90 [%] and elements connected to the path are laid out. Make it a target of modification. The first deriving unit 1703 derives the second period in which the margin including the number of signals of 90 [%] in the distribution is 0. For example, the first deriving unit 1703 derives the second period by the following equation (3).

  Second period = period of timing constraint—margin including 90% signal number in distribution (3)

  FIG. 19 is an explanatory diagram of an example of the second cycle derivation result according to the second embodiment. In the example of FIG. 19, the second period is 30 [ns], and the first deriving unit 1703 changes the period corresponding to the shift operation in the timing constraint information 711 to 30 [ns].

  Next, when the generation unit 1704 causes the test operation of the circuit 200 to be executed by the clock of the second period, all the signals in the circuit 200 become the test operation, and the positional relationship of the elements or wirings is the first layout. Second layout data 1710 different from the data 710 is generated. The generation unit 1704 generates second layout data 1710 based on the first layout data 710. A graph 1802 shown in FIG. 18 shows a margin of a signal in the circuit 200 when the test operation of the circuit 200 is executed by the clock of the second period based on the second layout data 1710. After the layout correction, the position where the margin becomes zero approaches the distribution after the layout correction.

  Based on the second layout data 1710, the current consumption amount analysis unit 1702 analyzes the current consumption amount of the circuit 200 when the circuit 200 is caused to perform a test operation using the second cycle clock. The analysis of the consumption current amount by the consumption current amount analysis unit 1702 is performed by a current analysis tool.

  The second deriving unit 1705 derives the third cycle of the clock shorter than the first cycle without exceeding the upper limit value 103 of the current consumption of the circuit 200 based on the analysis result by the current consumption analyzing unit 1702.

  Third period = second period / ((upper limit value 103−static current amount−current amount of circuit 200 other than shift operation) / operating current amount of shift operation) (4)

  The third deriving unit 1706 derives a fourth period that is equal to or greater than the longer one of the derived second period and third period. A specific example of the third derivation unit 1706 is the same as the third derivation unit 705 of the first embodiment, and thus detailed description thereof is omitted.

(Example of processing procedure performed by the test support apparatus 1700 according to the second embodiment)
FIG. 20 is a flowchart of an example of a processing procedure performed by the test support apparatus according to the second embodiment. The test support apparatus 1700 performs capacity extraction based on the net list 1501, the first layout data 710, and the wiring configuration specification information 1502 (step S2001). Next, the test support apparatus 1700 performs delay calculation based on the wiring capacity information 1503, the IP library 1504, and the netlist 1501 (step S2002), and performs timing analysis based on the wiring delay information 1505. (Step S2003).

  The test support apparatus 1700 determines whether or not the timing analysis is the first time (step S2004). If it is the first time (step S2004: Yes), the test support apparatus 1700 derives the second period, updates the timing constraint information (step S2005), and proceeds to step S2007.

  When it is not the first time (step S2004: No), the test support apparatus 1700 determines whether or not the timing analysis result 101 satisfies the timing constraint (step S2006). When the timing analysis result 101 does not satisfy the timing constraint (step S2006: No), the test support apparatus 1700 corrects the layout (step S2007) and returns to step S2001. In step S2007, second layout data 1710 is generated.

  When the timing analysis result 101 satisfies the timing constraint (step S2006: Yes), the process proceeds to step S2008 and step S2009. For example, for all signals in the circuit 200, if the signal delay time is shorter than the first period, it is determined that the timing constraint is satisfied. Next to Yes in step S2006, the test support apparatus 1700 performs physical verification (step S2008), and ends a series of processes.

  Further, next to Yes in step S2006, the test support apparatus 1700 performs a test program generation process (step S2009) and ends a series of processes. Then, the test program generated by the test program generation process is given to the tester, and the circuit 200 is tested.

  FIG. 21 is a flowchart of a test program generation processing procedure example according to the second embodiment. The test support apparatus 1700 performs a logic simulation based on the test program 1506, the IP library 1504, and the netlist 1501 (step S2101). Then, the test support apparatus 1700 analyzes the consumption current amount based on the circuit 200 operation information obtained by the logic simulation and the wiring capacitance information 1503 obtained by the above-described capacitance extraction (step S2102), and the consumption current is calculated. A third period is derived based on the quantity analysis result 102 (step S2103).

  Then, the test support apparatus 1700 derives a fourth period that is longer than the longer period of the second period and the third period (step S2104). Then, the test support apparatus 1700 outputs the fourth period (step S2105), and gives the fourth period to the ATPG to generate a test program (step S2106). As the output format of the fourth period in step S2105, for example, the data may be output to a storage device such as the RAM 603 and the disk 605, or may be output to another device via the network NET using the I / F 606. You may output to the apparatus 608.

  According to the test support apparatus described in the second embodiment, a first cycle of a clock shorter than a predetermined cycle in which a part of the signals in the circuit is in accordance with the test operation is derived, and the derived first cycle clock is used. Layout data is generated in which all signals in the circuit are in accordance with the circuit test operation. Then, according to the test support apparatus, the second period is derived based on the analysis result of the consumption current amount based on the generated layout data, and the third period that is longer than both the first period and the second period is derived. . As a result, the timing of some of the signals is corrected, and the earlier clock cycle is used during the test operation among the clock cycles in accordance with the test operation. Therefore, the clock cycle during the test operation can be optimized, and the efficiency of the circuit test can be improved.

  Note that the test support methods described in the first and second embodiments can be realized by executing a test support program prepared in advance on a computer such as a personal computer or a workstation. The test support program is recorded on a computer-readable recording medium such as a magnetic disk, an optical disk, or a USB (Universal Serial Bus) flash memory, and is executed by being read from the recording medium by the computer. The test support program may be distributed through a network such as the Internet.

  The following additional notes are disclosed with respect to the first and second embodiments described above.

(Supplementary note 1)
Based on the timing analysis result of the signal in the circuit when the circuit is caused to execute the test operation by the first clock of the first period, the first cycle shorter than the first period in which the circuit can execute the test operation. Deriving a second period of 2 clocks,
Based on an analysis result of the current consumption amount of the circuit when the circuit is caused to execute the test operation by the first clock of the first period, the upper limit value of the current consumption amount of the circuit is not exceeded. Deriving the third period of the third clock shorter than one period,
Deriving a fourth period of the fourth clock equal to or longer than the longer one of the derived second period and the third period;
A test support method characterized by executing processing.

(Supplementary note 2) The test support method according to supplementary note 1, wherein the test operation is a shift operation by a test flip-flop in the circuit.

(Supplementary note 3) The test support method according to supplementary note 1, wherein the test operation is a capture operation of a flip-flop in the circuit.

(Appendix 4) The computer
Further, when the second test operation of the circuit different from the test operation (hereinafter referred to as “first test operation”) is executed by the first clock of the first period, Deriving a fifth period of a fifth clock shorter than the first period in which the circuit can execute the second test operation based on a signal timing analysis result;
Execute the process,
In the process of deriving the fourth period,
The test support method according to appendix 1, wherein the fourth period that is longer than the longest period among the derived second period, the third period, and the fifth period is derived.

(Supplementary note 5) The first test operation is a shift operation by a flip-flop in the circuit, and the second test operation is a capture operation of a flip-flop in the circuit. The test support method described in 1.

(Appendix 6)
A timing analysis result based on first circuit information indicating an element in the circuit and a wiring between the elements, and a signal in the circuit when the test operation is performed by the circuit by the first clock of the first period. Based on the timing analysis result, a second period of the second clock shorter than the first period in which a part of the signals in the circuit is in accordance with the test operation is derived,
When the test operation of the circuit is executed in the derived second period, all signals in the circuit are in accordance with the test operation, and the positional relationship of the element or the wiring is different from the first circuit information. Generate second circuit information,
An analysis result of the current consumption amount of the circuit based on the generated second circuit information, and the current consumption amount of the circuit when the circuit performs the test operation by the second clock of the second period A third period of the third clock shorter than the first period without exceeding the upper limit value of the current consumption amount of the circuit based on the analysis result of
Deriving a fourth period of the fourth clock equal to or longer than the longer one of the derived second period and the third period;
A test support method characterized by executing processing.

(Appendix 7)
Based on the timing analysis result of the signal in the circuit when the circuit is caused to execute the test operation by the first clock of the first period, the first cycle shorter than the first period in which the circuit can execute the test operation. Deriving a second period of 2 clocks,
Based on an analysis result of the current consumption amount of the circuit when the circuit is caused to execute the test operation by the first clock of the first period, the upper limit value of the current consumption amount of the circuit is not exceeded. Deriving the third period of the third clock shorter than one period,
Deriving the fourth period of the fourth clock over the longer period of the derived second period and the third period;
A test support program characterized by causing processing to be executed.

(Appendix 8)
A timing analysis result based on first circuit information indicating an element in the circuit and a wiring between the elements, and a signal in the circuit when the test operation is performed by the circuit by the first clock of the first period. Based on the timing analysis result, a second period of the second clock shorter than the first period in which a part of the signals in the circuit is in accordance with the test operation is derived,
When the test operation of the circuit is executed in the derived second period, all signals in the circuit are in accordance with the test operation, and the positional relationship of the element or the wiring is different from the first circuit information. Generate second circuit information,
An analysis result of the current consumption amount of the circuit based on the generated second circuit information, and the current consumption amount of the circuit when the circuit performs the test operation by the second clock of the second period A third period of the third clock shorter than the first period without exceeding the upper limit value of the current consumption amount of the circuit based on the analysis result of
Deriving a fourth period of the fourth clock equal to or longer than the longer one of the derived second period and the third period;
A test support program characterized by causing processing to be executed.

(Supplementary Note 9) The first circuit is capable of executing the test operation based on a timing analysis result of a signal in the circuit when the circuit performs a test operation with the first clock of the first period. A first deriving unit for deriving a second period of the second clock shorter than the period;
Based on an analysis result of the current consumption amount of the circuit when the circuit is caused to execute the test operation by the first clock of the first period, the upper limit value of the current consumption amount of the circuit is not exceeded. A second deriving unit for deriving a third period of the third clock shorter than one period;
A third deriving unit for deriving a fourth period of the fourth clock that is equal to or longer than the longer one of the derived second period and the third period;
A test support apparatus characterized by comprising:

(Additional remark 10) It is a timing analysis result by the 1st circuit information which shows the element in a circuit, and the wiring between the said elements, Comprising: The said circuit in case the test operation is performed by the said circuit with the 1st clock of a 1st period A first deriving unit for deriving a second period of the second clock shorter than the first period in which a part of the signals in the circuit is in accordance with the test operation based on a timing analysis result of the signal in the circuit;
When the test operation of the circuit is executed according to the second period derived by the first deriving unit, all signals in the circuit are in accordance with the test operation. A generating unit that generates second circuit information different from the first circuit information;
The analysis result of the current consumption amount of the circuit based on the second circuit information generated by the generation unit, wherein the circuit performs the test operation by the second clock of the second period. A second deriving unit for deriving a third period of the third clock shorter than the first period without exceeding an upper limit value of the current consumption of the circuit based on an analysis result of the current consumption of the circuit;
A third deriving unit for deriving a fourth cycle of the fourth clock that is equal to or longer than the longer cycle of the second cycle and the third cycle derived by the second deriving unit;
A test support apparatus characterized by comprising:

(Supplementary Note 11) The first circuit is capable of executing the test operation based on a timing analysis result of a signal in the circuit when the circuit performs a test operation with the first clock of the first period. Deriving a second period of the second clock shorter than the period;
Based on an analysis result of the current consumption amount of the circuit when the circuit is caused to execute the test operation by the first clock of the first period, the upper limit value of the current consumption amount of the circuit is not exceeded. Deriving the third period of the third clock shorter than one period,
Deriving a fourth period of the fourth clock equal to or longer than the longer one of the derived second period and the third period;
A recording medium on which a test support program for causing a computer to execute processing is recorded.

(Additional remark 12) It is the timing analysis result by the 1st circuit information which shows the element in the circuit and the wiring between the said elements, Comprising: The said circuit when the said test operation is performed by the said circuit with the 1st clock of a 1st period A second period of a second clock that is shorter than the first period when a part of the signals in the circuit is in accordance with the test operation,
When the test operation of the circuit is executed in the derived second period, all signals in the circuit are in accordance with the test operation, and the positional relationship of the element or the wiring is different from the first circuit information. Generate second circuit information,
An analysis result of the current consumption amount of the circuit based on the generated second circuit information, and the current consumption amount of the circuit when the circuit performs the test operation by the second clock of the second period A third period of the third clock shorter than the first period without exceeding the upper limit value of the current consumption amount of the circuit based on the analysis result of
Deriving a fourth period of the fourth clock equal to or longer than the longer one of the derived second period and the third period;
A recording medium on which a test support program for causing a computer to execute processing is recorded.

100, 1700 Test support device 101 Timing analysis result 102 Current consumption amount analysis result 103 Upper limit value 200 Circuit 601 CPU
703, 1703 First derivation unit 704, 1705 Second derivation unit 705, 1706 Third derivation unit 1704 generation unit

Claims (10)

Computer
Based on the timing analysis result of the signal in the circuit when the circuit is caused to execute the test operation by the first clock of the first period, the first cycle shorter than the first period in which the circuit can execute the test operation. Deriving a second period of 2 clocks,
Based on an analysis result of the current consumption amount of the circuit when the circuit is caused to execute the test operation by the first clock of the first period, the upper limit value of the current consumption amount of the circuit is not exceeded. Deriving the third period of the third clock shorter than one period,
Deriving a fourth period of the fourth clock equal to or longer than the longer one of the derived second period and the third period;
A test support method characterized by executing processing.   The test support method according to claim 1, wherein the test operation is a shift operation by a test flip-flop in the circuit.   The test support method according to claim 1, wherein the test operation is a capture operation of a flip-flop in the circuit. The computer is
Further, when the second test operation of the circuit different from the test operation (hereinafter referred to as “first test operation”) is executed by the first clock of the first period, Deriving a fifth period of a fifth clock shorter than the first period in which the circuit can execute the second test operation based on a signal timing analysis result;
Execute the process,
In the process of deriving the fourth period,
The test support method according to claim 1, wherein the fourth period that is equal to or longer than the longest period among the derived second period, the third period, and the fifth period is derived.   5. The first test operation is a shift operation by a flip-flop in the circuit, and the second test operation is a capture operation of a flip-flop in the circuit. Exam support method. Computer
A timing analysis result based on first circuit information indicating an element in the circuit and a wiring between the elements, and a signal in the circuit when the test operation is performed by the circuit by the first clock of the first period. Based on the timing analysis result, a second period of the second clock shorter than the first period in which a part of the signals in the circuit is in accordance with the test operation is derived,
When the test operation of the circuit is executed in the derived second period, all signals in the circuit are in accordance with the test operation, and the positional relationship of the element or the wiring is different from the first circuit information. Generate second circuit information,
An analysis result of the current consumption amount of the circuit based on the generated second circuit information, and the current consumption amount of the circuit when the circuit performs the test operation by the second clock of the second period A third period of the third clock shorter than the first period without exceeding the upper limit value of the current consumption amount of the circuit based on the analysis result of
Deriving a fourth period of the fourth clock equal to or longer than the longer one of the derived second period and the third period;
A test support method characterized by executing processing. On the computer,
Based on the timing analysis result of the signal in the circuit when the circuit is caused to execute the test operation by the first clock of the first period, the first cycle shorter than the first period in which the circuit can execute the test operation. Deriving a second period of 2 clocks,
Based on an analysis result of the current consumption amount of the circuit when the circuit is caused to execute the test operation by the first clock of the first period, the upper limit value of the current consumption amount of the circuit is not exceeded. Deriving the third period of the third clock shorter than one period,
Deriving a fourth period of the fourth clock equal to or longer than the longer one of the derived second period and the third period;
A test support program characterized by causing processing to be executed. On the computer,
A timing analysis result based on first circuit information indicating an element in the circuit and a wiring between the elements, and a signal in the circuit when the test operation is performed by the circuit by the first clock of the first period. Based on the timing analysis result, a second period of the second clock shorter than the first period in which a part of the signals in the circuit is in accordance with the test operation is derived,
When the test operation of the circuit is executed in the derived second period, all signals in the circuit are in accordance with the test operation, and the positional relationship of the element or the wiring is different from the first circuit information. Generate second circuit information,
An analysis result of the current consumption amount of the circuit based on the generated second circuit information, and the current consumption amount of the circuit when the circuit performs the test operation by the second clock of the second period A third period of the third clock shorter than the first period without exceeding the upper limit value of the current consumption amount of the circuit based on the analysis result of
Deriving a fourth period of the fourth clock equal to or longer than the longer one of the derived second period and the third period;
A test support program characterized by causing processing to be executed. Based on the timing analysis result of the signal in the circuit when the circuit is caused to execute the test operation by the first clock of the first period, the first cycle shorter than the first period in which the circuit can execute the test operation. A first deriving unit for deriving a second period of two clocks;
Based on an analysis result of the current consumption amount of the circuit when the circuit is caused to execute the test operation by the first clock of the first period, the upper limit value of the current consumption amount of the circuit is not exceeded. A second deriving unit for deriving a third period of the third clock shorter than one period;
A third deriving unit for deriving a fourth period of the fourth clock that is equal to or longer than the longer one of the derived second period and the third period;
A test support apparatus characterized by comprising: A timing analysis result based on first circuit information indicating an element in the circuit and a wiring between the elements, and a signal in the circuit when the test operation is performed by the circuit by the first clock of the first period. A first deriving unit for deriving a second period of a second clock shorter than the first period in which some of the signals in the circuit are in accordance with the test operation based on a timing analysis result;
When the test operation of the circuit is executed according to the second period derived by the first deriving unit, all signals in the circuit are in accordance with the test operation. A generating unit that generates second circuit information different from the first circuit information;
The analysis result of the current consumption amount of the circuit based on the second circuit information generated by the generation unit, wherein the circuit performs the test operation by the second clock of the second period. A second deriving unit for deriving a third period of the third clock shorter than the first period without exceeding an upper limit value of the current consumption of the circuit based on an analysis result of the current consumption of the circuit;
A third deriving unit for deriving a fourth cycle of the fourth clock that is equal to or longer than the longer cycle of the second cycle and the third cycle derived by the second deriving unit;
A test support apparatus characterized by comprising:

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