JP2014107324A - Semiconductor integrated circuit and modulation factor measurement method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit and a modulation factor measurement method, which can confirm whether an SSCG (Spread Spectrum Clock Generator) operates at an intended modulation factor.SOLUTION: In a semiconductor integrated circuit, a counter 4 counts an output clock of an SSCG 2; a modulation period of the SSCG 2 is equally divided by an equal division number setting part 6; the number of equal division setting is calculated based on the equal division number and the modulation period set by a modulation period setting part 3 to obtain a length of the equally divided period; the equally divided period is counted by a counter 5 and a counter value of the counter 4 is caused to be stored and held in a register group 8 when the counter value of the counter 5 becomes equal to the number of equal division setting; and a maximum value and a minimum value are extracted and output from the equivalent count values of the modulation period.

Description

  The present invention relates to a semiconductor integrated circuit having a spread spectrum clock oscillation circuit and a modulation rate measurement method for the spread spectrum clock oscillation circuit.

  In recent years, as electronic devices become faster and have higher performance, the operating frequency of electronic circuits used in the electronic devices has become faster.

  EMI (Electro Magnetic Interference) noise due to electromagnetic waves generated by electronic devices due to the influence of electronic circuits operating at such high speeds is a serious problem. This EMI noise affects other electronic devices such as malfunction and performance degradation. This EMI noise is caused by operating at a single clock frequency. In order to reduce this noise, countermeasures on the board of electronic equipment and countermeasures for the transmission path are taken. I came. However, in recent years, measures have been taken by spreading the peak frequency by modulating the operating clock using a spread spectrum clock generator (hereinafter referred to as SSCG) in a semiconductor integrated circuit constituting an electronic circuit. It is like that.

  In a semiconductor integrated circuit such as an ASIC (Application Specific Integrated Circuit) equipped with this type of SSCG, an external measurement such as an oscilloscope or spectrum analyzer can be used to confirm that the clock output from the SSCG is actually modulated. Since the waveform is observed in an analog manner using an apparatus, there is a problem that it takes time for evaluation.

  To deal with such a problem, Patent Document 1 uses a counter that counts up with an SSCG output clock to measure the count value when the SSCG is turned on and off, and compares the measured values. A semiconductor device is described in which whether the SSCG modulation operation is performed is output by outputting whether the comparison results in a match or a mismatch.

  In the observation using a high-speed logic tester, since the modulation rate is very small, it is possible to confirm the ON / OFF operation of SSCG, but it is difficult to confirm that it is operating at the actually set modulation rate. There was a problem.

  Also, the semiconductor device described in Patent Document 1 can confirm whether the SSCG modulation operation is performed, but cannot confirm that it is operating at the actually set modulation rate.

  The present invention aims to solve such problems.

  That is, an object of the present invention is to provide a semiconductor integrated circuit and a modulation rate measurement method capable of confirming whether SSCG is operating at a desired modulation rate.

  In order to solve the problems described above, the invention described in claim 1 is a spectrum for outputting a modulation clock in which a frequency is modulated with a predetermined modulation period and a predetermined modulation rate from an input first clock. In a semiconductor integrated circuit having a spread clock oscillation circuit, a division unit that equally divides the predetermined modulation period into a plurality of periods, and a measurement unit that measures the number of modulation clocks in each of the plurality of periods equally divided by the division unit And an extraction unit that extracts a maximum value and a minimum value from the number of modulation clocks measured by the measurement unit.

  According to the first aspect of the present invention, the SSCG modulation period is equally divided, the number of modulation clocks in the equally divided period is measured, and the maximum and minimum values of the measured values are extracted. Therefore, since the maximum value corresponds to the upper limit frequency of the modulation rate and the minimum value corresponds to the lower limit frequency of the modulation rate, when the SSCG is operated in the semiconductor integrated circuit having the SSCG, the modulation frequency is modulated by the maximum value and the minimum value. The rate can be confirmed stably and efficiently.

1 is a configuration diagram of a semiconductor integrated circuit according to a first embodiment of the present invention. It is explanatory drawing of a down spread. It is explanatory drawing of a center spread. 3 is a flowchart showing an operation for checking the modulation rate of SSCG shown in FIG. 1. This is an example of dividing a center spread and a down spread. 2 is a timing chart showing operation timings of the semiconductor integrated circuit shown in FIG. 1. FIG. 5 is a configuration diagram showing another configuration of the semiconductor integrated circuit shown in FIG. 1. It is a block diagram of the semiconductor integrated circuit concerning the 2nd Embodiment of this invention.

  Hereinafter, an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a configuration diagram of a semiconductor integrated circuit according to the first embodiment of the present invention. FIG. 2 is an explanatory diagram of a down spread. FIG. 3 is an explanatory diagram of the center spread. FIG. 4 is a flowchart showing the confirmation operation of the SSCG modulation rate shown in FIG. FIG. 5 is an example of dividing the center spread and the down spread. FIG. 6 is a timing chart showing the operation timing of the semiconductor integrated circuit shown in FIG. FIG. 7 is a configuration diagram showing another configuration of the semiconductor integrated circuit shown in FIG.

(First embodiment)
FIG. 1 shows a configuration diagram of a main part of a semiconductor integrated circuit 1 according to a first embodiment of the present invention. The semiconductor integrated circuit 1 includes an SSCG 2, a modulation period setting unit 3, counters 4 and 5, an equal division number setting unit 6, comparators 7 and 9, a register group 8, an output register 10, and an output control unit. 11. In addition to the above-described components, the semiconductor integrated circuit 1 includes a functional block that operates in synchronization with the clock signal output from the SSCG 2, but illustration thereof is omitted.

  The SSCG 2 is a spread spectrum clock oscillation circuit as described above. That is, this is a circuit that modulates the frequency of REFCLK1, which is the first clock signal input from the outside, with a modulation period set in the modulation period setting unit 3 and a predetermined modulation rate, and outputs the modulated signal. According to this SSCG2, the peak value of the frequency spectrum of the clock signal (modulation clock) to be output can be lowered, and radiation noise can be reduced. The modulation factor may be a fixed value determined at the time of circuit design, or may be set to SSCG 2 from the outside so as to be changeable.

  Here, the modulation operation of the SSCG 2 will be described with reference to FIGS. The SSCG operation includes a down spread and a center spread. As shown in FIG. 2, the down spread is such that the output clock signal has the maximum target frequency (Target Freq) and the frequency modulation (variation) of the modulation factor α is performed in the modulation period β. That is, the spectrum is spread (clock modulated) below the original frequency that is not modulated. This down spread is optimal when used below the guaranteed frequency of an ASIC, microcomputer, etc., which is the latter stage of SSCG, for example.

  In the center spread, as shown in FIG. 3, the output clock signal is subjected to frequency modulation with a modulation factor α having an upper and lower limit around the target frequency in a modulation period β. That is, the spectrum is spread (clock modulated) around the original unspread frequency. This center spread is optimal when, for example, there is a margin in the operating frequency with respect to the guaranteed frequency of the ASIC, microcomputer or the like subsequent to SSCG.

  The modulation cycle setting unit 3 is configured by a register, for example, and the modulation cycle of the SSCG 2 can be set from the outside. The modulation period setting unit 3 may use a predetermined default value when the modulation period is not set from the outside.

  A counter 4 serving as a measuring unit and a first counter is a counter that counts up by a clock signal output from the SSCG 2. The counter 4 outputs a count value to the register group 8 based on the comparison result of the comparator 7 and resets the count value.

  The counter 5 as the second counter is a counter that counts up by REFCLK2, which is a second clock signal different from the clock signal output by the SSCG2. The counter 5 is reset with the count value based on the comparison result of the comparator 7.

  The equal division number setting unit 6 as a division unit, a calculation unit, and a division number setting unit includes, for example, a register, and the number of divisions for equally dividing the modulation period set in the modulation period setting unit 3 into a plurality of periods is set from the outside. It is possible. The equal division number setting unit 6 sets the length of the division period of the modulation period to REFCLK2 from the set division number, the modulation period set in the modulation period setting unit 3, and the frequency of REFCLK2 input from the outside. The converted value is calculated and held as an equally divided set value. That is, based on the modulation period and the number of divisions, the equally divided period is calculated as a value converted by the second number of clocks. Further, the equal division number setting unit 6 may use a predetermined default value when the equal division number is not set from the outside. Further, the equal division setting value may be directly set instead of the division number.

  The comparator 7 serving as a detection unit and a control unit compares the count value of the counter 5 with the equal division set number held in the equal division number setting unit 6. Stops counting. After that, after the register group 8 captures and holds the value of the counter 4, the counter 4 and the counter 5 are reset. That is, it is detected whether or not the count value of the second counter coincides with the period equally divided by the dividing unit. Further, when the detection unit detects a match, the count values of the first counter and the second counter are reset after outputting the count value of the first counter as the measurement value of the period.

  The register group 8 as a storage unit includes a plurality of registers A to H (RegA to RegH), and stores the count value of the counter 4. That is, the number of modulation clocks for each period measured by the measurement unit is stored. In FIG. 1, since it is composed of eight registers, a maximum of eight divisions can be supported.

  The comparator 9 as an extracting unit sequentially compares the values stored in the register group 8 and stores the maximum value and the minimum value in the output register 10. That is, the maximum value and the minimum value are extracted by comparing a plurality of modulation clock numbers stored in the storage unit.

  The output register 10 includes registers X and Y (RegX, RegY). In the output register 10, for example, the maximum value output from the comparator 9 is stored in the register X, and the minimum value output from the comparator 9 is stored in the register Y.

  The output control unit 11 outputs the contents of the output register 10 to the outside based on control from, for example, an external input terminal.

  Next, the operation of measuring the modulation rate of SSCG 2 in semiconductor integrated circuit 1 having the above-described configuration will be described with reference to the flowchart of FIG.

  First, in step S1, the operation of the counter is started and the process proceeds to step S2. In this step, SSCG2 operates using REFCLK1 as a reference clock. Then, the counter 4 is incremented by the clock signal output from the SSCG 2. On the other hand, the counter 5 is incremented by REFCLK2, which is a clock signal having a frequency different from that of the clock signal output from SSCG2. In the present embodiment, REFCLK2 is a clock signal having a sufficiently smaller frequency than the clock signal input from the outside and output from SSCG2.

  Next, in step S <b> 2, the comparator 7 compares the value counted up by the counter 5 with the value indicating the length of the equally divided period calculated by the equally divided number setting unit 6. If the comparison results match (in the case of YES), the process proceeds to step S3. If they do not match (in the case of NO), this step is repeated until they match.

  Next, in step S3, since the comparison result matches in step S2, the comparator 7 stops the count-up operation of the counter 4 (SSCG counter) and proceeds to step S4.

  Next, in step S4, the count value of the counter 4 stopped in step S3 is stored and held in the register group 8, and the process proceeds to step S5. That is, the register group 8 captures and holds the count value of the counter 4. The register group 8 changes the register for storing the value in the order of the register A and the register B every time the value is transferred from the counter 4 until the counting operation described later is completed. For example, the register group 8 may be provided with an address pointer (not shown), and the address pointer may be incremented each time a value is transferred from the counter 4.

  Next, in step S5, the comparator 7 confirms whether the number of repetitions of the count-up operation of the counter 4 matches the modulation cycle. If they match (if YES), the process proceeds to step S7, and if they do not match ( If NO, the process proceeds to step S6. Whether the number of repetitions of the count-up operation of the counter 4 matches the modulation period can be determined by, for example, determining whether the number of repetitions of steps S1 to S5 matches the number of equal divisions set in the equal division number setting unit 6. Good.

  Next, in step S6, since the repetition of the count-up operation of the counter 4 does not coincide with the modulation period, the comparator 7 resets the counters 4 and 5 and returns to step S1. That is, when the detection unit detects a match, the count values of the first counter and the second counter are reset after outputting the count value of the first counter as the measurement value of the period.

  On the other hand, in step S7, since the repetition of the count-up operation of the counter 4 coincides with the modulation period, the comparator 7 ends the operations of the counters 4 and 5 and proceeds to step S8. In the above steps S1 to S7, the predetermined modulation period is equally divided into a plurality of periods, and functions as a measurement process for measuring the number of modulation clocks in each of the plurality of equally divided periods.

  Next, in step S8, the comparator 9 sequentially compares the count values stored (held) in the register group 8, selects the maximum value and the minimum value, outputs them to the output register 10, and proceeds to step S9. . That is, it functions as an extraction process for extracting the maximum value and the minimum value from the number of modulation clocks measured in the measurement process.

  Next, in step S9, the output register 10 holds the maximum value and the minimum value output from the register group 8 in step S8, and proceeds to step S10.

  Next, in step S10, the output control unit 11 outputs the contents of the output register 10 to the outside based on control from an external input terminal or the like.

  Next, the operation timing of each circuit in the flowchart described above will be described with reference to the timing charts of FIGS.

  FIG. 5 is an example of dividing the modulation period. FIG. 5A shows an example of division of the center spread, and FIG. 5B shows an example of division of the down spread, both of which are examples divided into eight periods A1 to H1.

  Next, the timing chart shown in FIG. 6 will be described. Among the signals shown in the timing chart of FIG. 6, CLKSSC is the output clock signal of SSCG2, COUNT4 is the value of counter 4, Trig is the control signal output from comparator 7, and COUNT5 is the value of counter 5.

  The divided periods A1, B1, and C1 shown in FIG. 6 correspond to periods obtained by equally dividing the modulation period shown in FIG. The length of each period is determined by a value (equal division setting number) calculated based on the modulation period set in the modulation period setting unit 3 and the modulation division number set in the equal division number setting unit 6. In the example of FIG. 6, a value obtained by dividing the modulation period β by the equal division number 8 is a value converted by the frequency of REFCLK2.

  When the count value of the counter 5 matches the equal division set number set in the equal division number setting unit 6 (OK in the figure), the comparator 7 asserts Trig which is a control signal for stopping the count operation of the counter 4. . The value A of the counter 4 stopped by this Trig is stored and held in the corresponding register A of the register group 8. Thereafter, the process proceeds to the second counting operation. The count operation of period B1 is performed for the second time. Further, when shifting to a new counting operation, the counters 4 and 5 are reset, respectively. These operations are repeated until the equally divided section reaches the modulation period (end of the period H1 in FIG. 5), and when the modulation period is reached, the repetition operation ends.

  Thereafter, as shown in the flowchart of FIG. 4, after the count values of all equally divided periods are held in the register group 8, the data held in the registers of the register group 8 are sequentially read and the values are read. Compare At this time, the maximum and minimum values among the stored register values are detected and held in the output register 10.

  The result held in the output register 10 is output as a test output to an external bus or the like, and operates at a variation rate determined by comparing the expected value with a comparison with an expected value or a manual check. You can check whether or not

  A large counter value to be stored means that many clocks are toggled within the period. Therefore, the maximum value indicates the highest frequency of the clock output from the SSCG 2, and the minimum value indicates the lowest frequency. For example, in the case of FIG. 5, since the sections A1 and H1 are the maximum sections of the output frequency and the sections D1 and E1 are the minimum sections of the output frequency, the maximum value held in the output register 10 is the period A1 in FIG. Or H1, and the minimum value is the period D1 or E1. Therefore, the frequency modulation degree output from the SSCG 2 can be confirmed by the maximum value and the minimum value.

  According to the present embodiment, the counter 4 counts the output clock of the SSCG 2. Then, the modulation period of the SSCG 2 is equally divided by the equal division number setting unit 6, and the equal division setting number is calculated based on the equal division number and the modulation period set in the modulation period setting unit 3. Find the length of. Then, the equally divided period is counted by the counter 5 and the count value of the counter 4 when it matches the set number of equal divisions is stored and held in the register group 8, and the maximum value and the minimum value are calculated from the count values for the modulation period. The value is extracted and output. In this manner, when the SSCG 2 is operated in the semiconductor integrated circuit 1 having the SSCG 2 so that the maximum value corresponds to the upper limit frequency of the modulation rate and the minimum value corresponds to the lower limit frequency of the modulation rate, the modulation of the modulation frequency is performed. The rate can be measured and confirmed stably and efficiently.

  Further, the equal division number setting unit 6 calculates the equal division setting number by converting the value obtained by dividing the modulation period by the equal division number into the frequency of REFCLK2, which is a clock signal different from the output clock of SSCG2. The number of division settings can be set without being affected by SSCG2.

  The output register 10 is output to an external bus or the like as a tester observation point so that it can be tested with an LSI (Large Scale Integration) tester. However, the output register 10 may be configured as shown in FIG. FIG. 7 is configured such that an output of the output register 10 can be read through a CPU bus by a CPU (Central Processing Unit) 20 provided externally by a register read command or the like. That is, the output register 10 functions as a controller output unit that outputs the maximum value and the minimum value extracted by the extraction unit to a controller provided outside. By doing so, the modulation rate of SSCG2 can be confirmed not only at the time of LSI testing but also on the actual board, and debugging efficiency can be improved.

  Further, the number of equal divisions is not limited to 8, and may be finer. For example, if it is 16, the count value is half that of each period in FIG. Therefore, the frequency can be confirmed with higher accuracy. The count value is not limited to a register such as the register group 8 but may be a memory such as a RAM (Random Access Memory). The output register 10 may also be configured with a memory.

  In the configuration described above, not only the modulation rate but also the modulation period can be confirmed. That is, the count value of the counter 4 is sequentially stored in the registers constituting the register group 8 in the order of the registers A to H. That is, in the case of eight divisions, the count values for one cycle are stored in the order of the registers A to H along the variation of the modulation rate. Thus, by specifying where the register holding the maximum and minimum counts is, the half period of the modulation period can be known, and the modulation period can be confirmed.

  For example, if the register A: period A1 is the maximum while the register D: period D1 is the minimum, it can be seen that the cycle is as set. At this time, the register A is the maximum, but if the register F: F1 is the minimum, it can be seen that the modulation period is larger than the set modulation period.

  Specifically, if the value of the address pointer corresponding to the register group 8 register having the maximum value and the minimum value can also be stored in the output register 10, where is the register holding the maximum and minimum counts? Can be identified. A register for an address pointer may be added to the output register 10. That is, the comparator 9 functions as a specifying unit that specifies in which period of the periods in which the maximum value and the minimum value are equally divided.

  Thus, if the modulation period can be measured and confirmed simultaneously, the time required for the test can be shortened and the reliability of the test can be improved.

(Second Embodiment)
Next, a semiconductor integrated circuit 1 according to a second embodiment of the present invention will be described with reference to FIG. Note that the same parts as those in the first embodiment described above are denoted by the same reference numerals and description thereof is omitted. FIG. 8 is a configuration diagram of a semiconductor integrated circuit according to the second embodiment of the present invention.

  The semiconductor integrated circuit 1 according to the present embodiment is different from the first embodiment in that a comparison control unit 12 is provided instead of the register group 8 and the comparator 9.

  The comparison control unit 12 repeats the magnitude comparison with the data of the output register 10 holding the previous data at the timing when the operation of the counter 4 stops and holds the counter value, and changes the data of the output register 10 each time. To do. That is, the maximum value and the minimum value are extracted by sequentially comparing the value measured by the measurement unit and the value previously measured by the measurement unit.

  A specific operation example will be described with reference to FIG. Note that the register X is a maximum value and the register Y is a register storing a minimum value. First, when the count value of the period A1 is output from the counter 4, the count value of the period A1 is stored in the registers X and Y without comparison because of the first value. Next, when the count value of the period A2 is output from the counter 4, the count value of the period A2 is compared with the count value of the period A1 stored in the registers X and Y. When the count value in the period A2 is larger than the register X, the value in the register X is updated to the count value in the period A2. When the count value in the period A2 is smaller than the register Y, the value in the register Y is updated to the count value in the period A2. By repeating this, the maximum value and the minimum value in the modulation period are stored in the registers X and Y.

  According to the present embodiment, since the comparison control unit 12 is provided instead of the register group 8 and the comparator 9, it is not necessary to compare all data after the count operation is completed, and the number of operation cycles and the circuit scale can be reduced. Can do.

  In the above-described embodiment, hardware such as the counters 4 and 5 and the register group 8 is incorporated in the semiconductor integrated circuit 1 in order to measure the modulation rate of the SSCG 2. For example, the semiconductor integrated circuit 1 includes a CPU. If there is, the program may be configured to function as the modulation cycle setting unit 3, counters 4 and 5, equal division number setting unit 6, comparators 7 and 9, register group 8, output register 10, and output control unit 11 . In this case, if a signal corresponding to the CPU and SSCG2 and REFCLK2 can be input, the modulation factor measurement method can be realized by software (a program executed by a computer).

  In the above-described embodiment, the external LSI tester, the CPU 20 or the like determines whether or not the operation is performed with the set modulation rate. However, a determination circuit or the like may be provided inside the semiconductor integrated circuit 1. For example, a register or the like that can set the expected value of the modulation rate and a comparator may be provided inside, and the value of the output register 10 and the expected value may be compared by the comparator and the result may be output.

  Further, as is apparent from the description of the above-described embodiment, the present invention can be applied to both a down spread and a center spread.

  The present invention is not limited to the above embodiment. That is, those skilled in the art can implement various modifications in accordance with conventionally known knowledge without departing from the scope of the present invention. Of course, such modifications are included in the scope of the present invention as long as the configuration of the semiconductor integrated circuit of the present invention is provided.

1 Semiconductor integrated circuit 2 SSCG (spread spectrum clock oscillation circuit)
4 Counter (Measurement unit, 1st counter)
5 Counter (second counter)
6 Equal division number setting part (division part, division number setting part)
7 comparator (detection unit, control unit, calculation unit)
8 register group (storage)
9 Comparator (extraction part, specific part)
10 Output register (controller output part, storage part)
12 Comparison control unit (extraction unit)
20 CPU (controller)
S1 to S7 Count operation start to count operation end (measurement process)
S8 Hold count value selection (extraction process)
S10 Maximum value and minimum value register holding

Japanese Patent No. 4726585

Claims (9)

In a semiconductor integrated circuit having a spread spectrum clock oscillation circuit that outputs a modulation clock obtained by modulating a frequency with a predetermined modulation period and a predetermined modulation rate from an input first clock,
A dividing unit that equally divides the predetermined modulation period into a plurality of periods;
A measuring unit that measures the number of modulation clocks in each of a plurality of periods equally divided by the dividing unit;
An extraction unit for extracting a maximum value and a minimum value from the number of modulation clocks measured by the measurement unit;
A semiconductor integrated circuit comprising: The measurement unit is
A first counter for counting the number of modulation clocks;
A second counter for counting the number of clocks of a second clock different from the modulation clock;
A detection unit for detecting whether the count value of the second counter coincides with a period in which the division unit is equally divided;
A control unit that resets the count values of the first counter and the second counter after outputting the count value of the first counter as the measurement value of the period when the detection unit detects a match;
The semiconductor integrated circuit according to claim 1, comprising:   3. The division unit according to claim 2, further comprising a calculation unit that calculates the equally divided period as a value converted by the second number of clocks based on the modulation period and the number of equally divided divisions. A semiconductor integrated circuit according to 1. The extraction unit has a storage unit that stores the number of modulation clocks of each period measured by the measurement unit;
The extraction unit compares the plurality of modulation clock numbers stored in the storage unit to extract the maximum value and the minimum value;
The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is a semiconductor integrated circuit.   The extraction unit extracts the maximum value and the minimum value by sequentially comparing a value measured by the measurement unit and a value previously measured by the measurement unit. The semiconductor integrated circuit as described in any one of these.   6. The semiconductor according to claim 1, further comprising a specifying unit that specifies in which period of the equally divided periods the maximum value and the minimum value are measured. 6. Integrated circuit.   The semiconductor integrated circuit according to claim 1, wherein the division unit includes a division number setting unit in which a division number for equally dividing the modulation period is set.   8. The semiconductor integrated circuit according to claim 1, further comprising a controller output unit that outputs the maximum value and the minimum value extracted by the extraction unit to a controller provided outside. . In a method for measuring a modulation factor of a semiconductor integrated circuit having a spread spectrum clock oscillation circuit that outputs a modulation clock obtained by modulating a frequency with a predetermined modulation period and a predetermined modulation rate from an input first clock,
A measurement step of equally dividing the predetermined modulation period into a plurality of periods and measuring the number of modulation clocks in each of the plurality of equally divided periods;
An extraction step of extracting a maximum value and a minimum value from the number of modulation clocks measured in the measurement step;
A modulation rate measuring method comprising:

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