JP2014089144A - Semiconductor device and voltage monitoring system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem where a noise of a lower frequency than that of a transmission signal is difficult to remove by conventional methods.SOLUTION: According to one embodiment, a semiconductor device and a voltage monitoring system have a receiving circuit 1. The receiving circuit includes: an input stage circuit 10 that generates a first voltage VA and a second voltage VB that change in mutually opposite directions according to switching of the magnitude of a signal current; an adjustment circuit 12 that reduces a voltage difference between the first voltage VA and the second voltage VB by an adjustment current Iadj that is generated according to the voltage difference between the first voltage VA and the second voltage VB; and a comparator 15 that inverts the logic level of a reception signal DOUT on the basis of a magnitude relation between the first voltage VA and the second voltage VB.

Description

  The present invention relates to a semiconductor device and a voltage monitoring system. For example, the present invention relates to a semiconductor device and a voltage monitoring system for receiving data from other semiconductor devices operating at different power supply voltages.

  In an electric vehicle or a hybrid vehicle, an assembled battery in which a plurality of battery cells are connected in series is used to drive an electric motor. Since this assembled battery is charged / discharged according to the use situation of the vehicle, the voltage fluctuates according to the use situation of the vehicle. At this time, in order to appropriately drive the electric motor, it is important to monitor each state of the plurality of battery cells constituting the assembled battery to ensure appropriate performance. Therefore, a vehicle equipped with an assembled battery is equipped with a voltage monitoring system that monitors the state of the assembled battery.

  In the voltage monitoring system, a plurality of battery cells are classified into a plurality of battery modules, and a battery monitoring module for monitoring the state of the battery cell is provided for each battery module to monitor the state of all the battery cells. In the voltage monitoring system, the control unit that controls the battery monitoring module and the battery monitoring module and the battery monitoring modules are connected by a communication network.

  However, the assembled battery and the voltage monitoring system are often arranged in the vicinity of the electric motor due to their properties, and noise accompanying the operation of the electric motor may enter the communication network and cause communication failure. Therefore, Patent Documents 1 and 2 disclose techniques for improving resistance to noise mixed in a communication network.

  Patent Document 1 has a multistage receiving circuit. Then, a capacitor is provided on the wiring connecting the stages, and the noise mixed in the wiring configuring the communication network is filtered, thereby reducing the influence of the noise on the received signal.

  Patent Document 2 discloses that a small transient noise and ringing are removed by providing hysteresis in a comparator.

US Patent Application Publication No. 2010/0277231 Special table 2003-509882 gazette

  However, the techniques described in Patent Documents 1 and 2 have a problem that noise having a frequency lower than that of a signal used for communication can be removed, but noise having a frequency lower than that of a communication signal cannot be removed. Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, the semiconductor device and the voltage monitoring system have a receiving circuit. The receiving circuit includes: an input stage circuit that generates first and second voltages that change in opposite directions according to switching of the magnitude of the signal current; and a voltage difference between the first voltage and the second voltage. An adjustment circuit that reduces a voltage difference between the first voltage and the second voltage by an adjustment current generated in accordance with the first and second voltages, and a logic level of the received signal is inverted based on a magnitude relationship between the first voltage and the second voltage. And a comparator.

  According to one embodiment, the semiconductor device can realize a receiving circuit with high noise resistance.

It is a block diagram which shows the structure of the voltage monitoring system VMS which monitors the output voltage of the assembled battery which supplies electric power to an electric vehicle etc. It is a block diagram of the principal part of the voltage monitoring system VMS which shows the connection relation of voltage monitoring module VMM1-VMMn and the cell monitoring part CMU. It is a block diagram which shows the structure of voltage monitoring module VMM1. It is a timing chart which shows the control procedure of the voltage monitoring module in a voltage monitoring system. 2 is a block diagram of a voltage monitoring module including a receiving circuit and a transmitting circuit according to the first embodiment; FIG. FIG. 2 is a detailed circuit diagram of a receiving circuit and a transmitting circuit according to the first exemplary embodiment. 4 is a timing chart illustrating an operation of the receiving circuit when the adjustment circuit is invalidated in the receiving circuit according to the first exemplary embodiment; 6 is a timing chart illustrating an operation of the receiving circuit according to the first exemplary embodiment when no noise is input or when noise having a voltage near the midpoint of a noise waveform is applied. 3 is a timing chart showing the operation of the receiving circuit according to the first exemplary embodiment when noise having a voltage near the upper vertex of a noise waveform is applied. 6 is a timing chart illustrating an operation of the receiving circuit according to the first exemplary embodiment when noise having a voltage near the lower apex of the noise waveform is applied. 3 is a timing chart illustrating an operation of the receiving circuit according to the first exemplary embodiment; FIG. 6 is a circuit diagram of a comparative example of a receiving circuit for explaining the effect of the receiving circuit according to the first exemplary embodiment; 12 is a timing chart illustrating an operation of the receiving circuit illustrated in FIG. 11. It is a block diagram of the principal part of the voltage monitoring system VMS which shows the connection relation of the voltage monitoring modules VMM1-VMMn concerning Embodiment 2, and the cell monitoring part CMU. 6 is a timing chart showing a control procedure of a voltage monitoring module in the voltage monitoring system VMS according to the second exemplary embodiment; FIG. 6 is a block diagram of a voltage monitoring module including a receiving circuit and a transmitting circuit according to a second embodiment. FIG. 4 is a detailed circuit diagram of a receiving circuit and a transmitting circuit according to the second embodiment.

  Hereinafter, embodiments will be described with reference to the drawings. In the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted as necessary.

  First, as a premise for understanding the embodiment, a voltage monitoring system that monitors the output voltage of an assembled battery that supplies power to an electric vehicle or the like will be described. First, the outline of the configuration of a voltage monitoring system VMS that monitors the output voltage of an assembled battery that supplies power to an electric vehicle or the like will be described with reference to FIG. FIG. 1 is a block diagram showing the configuration of a voltage monitoring system VMS that monitors the output voltage of an assembled battery that supplies power to an electric vehicle or the like. The voltage monitoring system VMS includes voltage monitoring modules VMM1 to VMMn (n is an integer of 2 or more), insulating elements INS1 and INS2, a cell monitoring unit (Cell Monitoring Unit) CMU, and a battery management unit (Battery Management Unit) BMU. The cell monitoring unit CMU and the battery management unit BMU are configured by, for example, a microcomputer (hereinafter, MCU: Micro Computing Unit).

  The voltage monitoring system VMS monitors the voltage of the assembled battery assy by the voltage monitoring modules VMM1 to VMMn. The assembled battery assy has n battery modules EM1 to EMn connected in series. Each of the battery modules EM1 to EMn has m battery cells (m is an integer of 2 or more) connected in series. That is, in the assembled battery assy, (m × n) battery cells are connected in series. Thereby, the assembled battery assy can obtain a high output voltage.

  The cell monitoring unit CMU is connected to the communication input terminal of the voltage monitoring module VMMn via the insulating element INS2, and is connected to the communication output terminal of the voltage monitoring module VMM1 via the insulating element INS1. As the insulating elements INS1 and INS2, for example, photocouplers are used, and the voltage monitoring modules VMM1 to VMMn and the cell monitoring unit CMU are electrically separated. As a result, it is possible to prevent the cell monitor unit CMU from being damaged due to a high voltage applied from the assembled battery assy to the cell monitor unit CMU in the event of a failure.

  The cell monitoring unit CMU is further connected to the battery management unit BMU. The cell monitoring unit CMU calculates the output voltage of each battery cell from the voltage monitoring results by the voltage monitoring modules VMM1 to VMMn and notifies the battery management unit BMU. In addition, the cell monitoring unit CMU controls the operation of the voltage monitoring modules VMM <b> 1 to VMMn in response to a command from the battery management unit BMU. Battery management unit BMU is further connected to an engine control unit ECU. The battery management unit BMU controls the operation of the voltage monitoring system VMS according to the output voltage of each battery cell notified from the cell monitoring unit CMU and the command from the engine control unit ECU. Further, the battery management unit BMU notifies the engine control unit ECU of information on the state of the voltage monitoring system VMS and the assembled battery assy. The operations of the cell monitoring unit CMU and the battery management unit BMU will be described in detail in the description of the operation of the voltage monitoring system VMS described later.

  Next, a connection relationship between the voltage monitoring modules VMM1 to VMMn and the cell monitoring unit CMU will be described with reference to FIG. FIG. 2 is a block diagram of the main part of the voltage monitoring system VMS showing the connection relationship between the voltage monitoring modules VMM1 to VMMn and the cell monitoring unit CMU. The voltage monitoring modules VMM1 to VMMn are connected to the battery modules EM1 to EMn, respectively, and monitor voltages received from the battery modules EM1 to EMn. The voltage monitoring modules VMM1 to VMMn are configured as a daisy chain, and the outputs of the communication circuits of the voltage monitoring modules VMM2 to VMMn are connected to the inputs of the communication circuits of the voltage monitoring modules VMM1 to VMM (n−1), respectively.

  The cell monitoring unit CMU outputs a control signal to the voltage monitoring module VMMn via the insulating element INS2. Note that the control signals for the voltage monitoring modules VMM1 to VMM (n−1) are transmitted to the voltage monitoring modules VMM1 to VMM (n−1) using the daisy chain configuration. Thereby, the cell monitoring unit CMU controls the operation of the voltage monitoring modules VMM1 to VMMn. The voltage monitoring modules VMM1 to VMMn output monitoring results to the cell monitoring unit CMU via the insulating element INS1 in response to a control signal from the cell monitoring unit CMU. The monitoring results from the voltage monitoring modules VMM2 to VMMn are transmitted to the cell monitoring unit CMU using a daisy chain configuration.

  Next, each configuration of the voltage monitoring modules VMM1 to VMMn will be described. The voltage monitoring modules VMM1 to VMMn have the same configuration. Therefore, as a representative example, the configuration of the voltage monitoring module VMM1 will be described with reference to FIG. FIG. 3 is a block diagram showing a configuration of the voltage monitoring module VMM1. The voltage monitoring module VMM1 includes a power supply circuit VMM_S, a communication circuit VMM_C, a voltage measurement circuit VMC, cell balance circuits CB1 to CBm (m is an integer of 2 or more), a power supply terminal VCC, input terminals V_1 to V_ (m + 1), and a cell balance input. Terminals VB1 to VBm, a communication input terminal Tin, and a communication output terminal Tout are provided.

  In the battery module EM1, battery cells EC1 to ECm are connected in series in order from the high voltage side. In the voltage monitoring module VMM1, the power supply terminal VCC is connected to the high voltage side of the battery cell EC1. The low voltage side of the battery cell ECm is connected to the input terminal V_ (m + 1). The voltage of the input terminal is branched in the voltage monitoring module VMM1, and is supplied as a ground voltage to the voltage measurement circuit VMC and the communication circuit VMM_C. Thereby, the output voltage of the battery module EM1 is supplied to the voltage monitoring module VMM1 as the power supply voltage. The power supply circuit VMM_S receives power supply from the battery cell EC1 through the power supply terminal VCC. The power supply circuit VMM_S supplies power to the communication circuit VMM_C and the voltage measurement circuit VMC.

  The voltage measurement circuit VMC includes a selection circuit VMC_SEL, an A / D converter (Analog to Digital Converter: ADC) VMC_ADC, a register VMC_REG, and a control circuit VMC_CON. The selection circuit VMC_SEL includes switches SWa_1 to SWa_m and SWb_1 to SWb_m. The switches SWa_1 to SWa_m and SWb_1 to SWb_m are turned on / off by a control signal from the control circuit VMC_CON. When j is an integer of 1 to m, the switches SWa_j and SWb_j are simultaneously turned on when measuring the voltage of the battery cell ECj. Thereby, the voltage from the high potential side terminal of the battery cell ECj is supplied to the A / D converter VMC_ADC as the high potential side voltage VH via the input terminal V_j. Similarly, the voltage from the low potential side terminal of the battery cell ECj is supplied to the A / D converter VMC_ADC as the low potential side voltage VL via the input terminal V_ (j + 1).

  The A / D converter VMC_ADC converts the values of the high potential side voltage VH and the low potential side voltage VL into voltage values that are digital values. Then, the digital voltage value is output to the register VMC_REG. The register VMC_REG stores the voltage value output from the A / D converter VMC_ADC. The control circuit repeats an operation of sequentially turning on the switches SWa_1 to SWa_m and SWb_1 to SWb_m every predetermined time (for example, 10 msec). As a result, the value of the voltage supplied to the input terminals V_j and V_ (j + 1) is overwritten in the register VMC_REG at every predetermined time.

  The communication circuit VMM_C receives commands from the cell monitoring unit CMU and outputs from the other voltage monitoring modules VMM2 to VMMn via the communication input terminal Tin. Then, the communication circuit VMM_C transfers the command from the cell monitoring unit CMU to the control circuit VMC_CON. The communication circuit VMM_C transfers the outputs from the voltage monitoring modules VMM2 to VMMn to the cell monitoring unit CMU as they are.

  The cell balance circuit CBj and the external resistor R_j are connected between the input terminal V_j and the input terminal V_ (j + 1), respectively, via the cell balance input terminal VBj. When the cell balance circuit CBj is turned on, the input terminal V_j and the input terminal V_ (j + 1) are electrically connected. The control circuit VMC_CON controls the cell balance circuits CB1 to CBm to be turned on / off, thereby selectively discharging each of the battery cells EC1 to ECm.

  Next, the operation of the voltage monitoring system VMS will be described with reference to FIG. First, the output voltage monitoring operation of the battery cell will be described. The voltage monitoring system VMS starts a battery cell output voltage monitoring operation in response to a voltage monitoring operation start command from the cell monitoring unit CMU. For example, the engine control unit ECU detects power-on of the electric vehicle, and issues a start command for the voltage monitoring system VMS to the battery management unit BMU. The battery management unit BMU issues an activation command for the voltage monitoring modules VMM1 to VMMn to the cell monitoring unit CMU in response to the activation command for the voltage monitoring system VMS. The cell monitoring unit CMU issues a voltage monitoring operation start command to the voltage monitoring modules VMM1 to VMMn in response to the activation command of the voltage monitoring modules VMM1 to VMMn.

  The operation of the voltage monitoring modules VMM1 to VMMn will be described with reference to FIG. Since the voltage monitoring modules VMM1 to VMMn that have received the voltage monitoring operation start command perform the same operation, the operation of the voltage monitoring module VMM1 will be described below as a representative example. The voltage monitoring module VMM1 starts a voltage monitoring operation in response to a voltage monitoring operation start command from the cell monitoring unit CMU. Specifically, the communication circuit VMM_C transfers a voltage monitoring operation start command from the cell monitoring unit CMU to the control circuit VMC_CON of the voltage measurement circuit VMC. The control circuit VMC_CON turns on the switches SWa_j and SWb_j in response to the voltage monitoring operation start command. Thereby, the input terminals V_j and V_ (j + 1) are connected to the A / D converter VMC_ADC, respectively. The A / D converter VMC_ADC converts the magnitude of the voltage supplied to the connected input terminals V_j and V_ (j + 1) into a voltage value that is a digital value, and writes the voltage value in the register VMC_REG.

  In this example, the control circuit VMC_CON sequentially turns on the switches SWa_1 to SWa_m and SWb_1 to SWb_m within a predetermined time. That is, the switching operation is repeated m times within a predetermined time. The predetermined time is, for example, 10 msec. In this case, the voltage monitoring module VMM1 measures the value of the voltage supplied to each of the input terminals V_j and V_ (j + 1) every predetermined time (10 msec), and sequentially overwrites the register VMC_REG. The voltage monitoring module VMM1 continuously performs the above-described voltage monitoring operation unless there is a command from the cell monitoring unit CMU.

  When referring to the value of the output voltage of the battery cell in order to control the electric vehicle, the cell monitoring unit CMU issues a voltage value output command to the voltage monitoring module VMM1 in response to the command from the battery management unit BMU. In response to the voltage value output command, the voltage monitoring module VMM1 outputs the voltage value of the designated input terminal to the cell monitoring unit CMU. Specifically, the communication circuit VMM_C transfers the voltage value output command from the cell monitoring unit CMU to the control circuit VMC_CON of the voltage measurement circuit VMC. The control circuit VMC_CON issues an output command to the register VMC_REG in response to the voltage value output command. At this time, the control circuit VMC_CON designates which input terminal voltage value is output to the register VMC_REG. In response to the output command from the control circuit VMC_CON, the register VMC_REG outputs the voltage value of the designated input terminal at the time of receiving the output command to the cell monitor unit CMU via the communication circuit VMM_C.

  The cell monitoring unit CMU calculates the output voltage of the battery cell ECj from the voltage values of the input terminals V_j and V_ (j + 1) received from the voltage monitoring module VMM1. For example, the cell monitoring unit CMU can calculate the output voltage of the battery cell EC1 from the voltage difference between the input terminal V_1 and the input terminal V_2. Thereafter, the cell monitoring unit CMU notifies the battery management unit BMU of the calculated output voltage of the battery cell in response to the request of the battery management unit BMU.

  When the electric vehicle is powered off, the engine control unit ECU detects the power off of the electric vehicle and issues a stop command for the voltage monitoring system VMS to the battery management unit BMU. The battery management unit BMU issues a command to stop the voltage monitoring modules VMM <b> 1 to VMMn to the cell monitoring unit CMU in response to the command to stop the voltage monitoring system VMS. The cell monitoring unit CMU issues a voltage monitoring operation stop command to the voltage monitoring modules VMM1 to VMMn in response to the stop command of the voltage monitoring modules VMM1 to VMMn. The voltage monitoring module VMM1 stops the voltage monitoring operation in response to a voltage monitoring operation stop command from the cell monitoring unit CMU. Specifically, the communication circuit VMM_C transfers a voltage monitoring operation stop command from the cell monitoring unit CMU to the control circuit VMC_CON of the voltage measurement circuit VMC. The control circuit VMC_CON turns off all the switches SWa_1 to SWa_m and SWb_1 to SWb_m in response to the voltage monitoring operation stop command. As a result, the voltage monitoring operation is stopped.

  The battery cell voltage monitoring operation has been described above. However, since the voltage monitoring system VMS is mounted on, for example, an electric vehicle, it is necessary to perform an operation according to the usage state of the electric vehicle. Therefore, below, operation | movement of the voltage monitoring system VMS according to the use condition of an electric vehicle is demonstrated.

  In order to use the electric vehicle continuously, it is necessary to charge the assembled battery assy in a desk lamp or the like. When charging the assembled battery assy, the engine control unit ECU detects a driver's operation such as connection of a charging plug, for example, and issues a charging command for charging the assembled battery assy to the battery management unit BMU. The battery management unit BMU opens the relays REL1 and REL2 in response to a charging command from the engine control unit ECU. Thereby, the assembled battery assy and the inverter INV are electrically disconnected. In this state, for example, the assembled battery assy is charged by supplying the external charging voltage CHARGE to the assembled battery assy through a charging plug.

  Generally, it is known that when a secondary battery such as a battery cell is overcharged or overdischarged, the life of the battery cell is shortened. In addition, in a configuration in which a plurality of battery cells are connected in series as in the assembled battery assy, voltage variations and the like occur even when the same charge / discharge operation is performed due to manufacturing variations of the battery cells. If the charging / discharging operation of the assembled battery assy is repeated with such variations occurring, only a specific battery cell is deteriorated, overcharged or overdischarged. As a result, the entire assembled battery assy is shortened and causes failure. For this reason, when using battery cells connected in series, it is necessary to maintain the voltage balance of each battery cell (so-called cell balance).

  Below, operation | movement of the battery cell of the voltage monitoring system VMS at the time of charge in a desk lamp etc. is demonstrated. The battery cell output voltage monitoring operation and the battery cell output voltage calculation method are the same as described above, and thus the description thereof will be omitted as appropriate.

  First, the battery management unit BMU issues an output voltage measurement command to the cell monitoring unit CMU in response to a charge command from the engine control unit ECU. The cell monitoring unit CMU calculates the output voltages of all the battery cells constituting the assembled battery assy in response to the output voltage measurement command from the battery management unit BMU, and notifies the battery management unit BMU. The battery management unit BMU specifies the battery cell having the lowest output voltage among the assembled batteries assy. Here, in order to simplify the description, it is assumed that the battery cell EC1 of the battery module EM1 is the battery cell having the lowest output voltage in the assembled battery assy.

  Thereafter, the battery management unit BMU issues a cell balance operation command to the cell monitoring unit CMU. The cell monitoring unit CMU issues a discharge command to the voltage monitoring modules VMM1 to VMMn according to the cell balance operation command. Hereinafter, the operation of the voltage monitoring module VMM1 will be described as a representative example. In the voltage monitoring module VMM1, the control circuit VMC_CON of the voltage measurement circuit VMC receives a discharge command via the communication circuit VMM_C. The control circuit VMC_CON turns on the cell balance circuits CB2 to CBm in response to the discharge command. Thereby, the battery cells EC2 to ECm are discharged.

  The cell monitoring unit CMU sequentially calculates the output voltage values of the battery cells EC2 to ECm that are being discharged. When the output voltage of each battery cell drops to the output voltage of the battery cell EC1, a discharge stop command is issued to stop the discharge operation of the corresponding battery cell. Below, the case where the output voltage of battery cell EC2 falls to the output voltage of battery cell EC1 by discharge is demonstrated. First, the cell monitoring unit CMU detects that the output voltage of the battery cell EC2 has dropped to the output voltage of the battery cell EC1. Then, a discharge stop command for the battery cell EC2 is issued to the voltage monitoring module VMM1.

  The control circuit VMC_CON of the voltage monitoring module VMM1 receives a discharge stop command for the battery cell EC2 via the communication circuit VMM_C. The control circuit VMC_CON turns off the cell balance circuit CB2 in response to a discharge stop command for the battery cell EC2. Thereby, the discharge of the battery cell EC2 is stopped, and the output voltage of the battery cell EC2 becomes the same as the output voltage of the battery cell EC1. When the cell monitoring unit CMU performs the same operation, the output voltages of the battery cells EC3 to ECm of the battery module EM1 and the battery cells of the battery modules EM2 to EMn are also the same as the output voltage of the battery cell EC1. Thereby, the output voltage of each battery cell of the battery modules EM2 to EMn is equalized, and the cell monitor unit CMU ends the cell balance operation. The cell monitor unit CMU notifies the battery management unit BMU of the end of the cell balance operation.

  In response to the notification of the end of the cell balance operation, the battery management unit BMU issues a charge start command to a power receiving unit (not shown) connected to the charging plug. Thereby, the external charging voltage CHARGE is supplied to the assembled battery assy, and charging of the assembled battery assy is started.

  The cell monitoring unit CMU monitors the output voltage of each battery cell being charged. Then, if the output voltage of any battery cell reaches the charge upper limit voltage, an overcharge alarm is notified to the battery management unit BMU. The battery management unit BMU issues a charge stop command to the power receiving unit in response to the overcharge alarm notification. As a result, the supply of the external charging voltage CHARGE is interrupted and charging is stopped. The upper limit charging voltage is desirably set to a voltage value having a sufficient margin from the voltage level at the time of overcharging and smaller than the threshold voltage level at the time of overcharging in order to reliably prevent the battery cell from being overcharged. .

  The charging characteristics of the battery cells of the battery modules EM1 to EMn vary. For this reason, variation occurs in the voltage value of each battery cell after charging. Therefore, the cell monitoring unit CMU measures the output voltage of each battery cell in order to grasp the variation in the voltage value of each battery cell. Then, it is determined whether or not the variation in the output voltage of each battery cell is within a specified range. Then, the determination result is notified to the battery management unit BMU.

  When the variation in the output voltage of each battery cell is not within the specified range, the battery management unit BMU instructs the cell monitoring unit CMU to start the cell balance operation. Then, after the cell balance operation is completed, the battery management unit BMU instructs the power reception unit to start charging. On the other hand, when the variation in the output voltage of each battery cell is within the specified range, the battery management unit BMU notifies the engine control unit ECU of the completion of charging. The engine control unit ECU displays that the charging of the assembled battery assy is completed on a display device provided in the driver's seat. As described above, the voltage monitoring system VMS can monitor the output voltage of the battery cell to charge the assembled battery assy to a fully charged state while preventing overcharge and maintaining a good cell balance. it can.

  Next, a case where the electric vehicle is accelerated will be described. In the case of accelerating the electric vehicle, the engine control unit ECU detects an operation of the driver such as depression of an accelerator pedal, for example, and issues an acceleration command for accelerating the electric vehicle to the inverter INV and the battery management unit BMU. To emit. Inverter INV switches the operation mode from DC to AC conversion mode in response to an acceleration command from engine control unit ECU. The battery management unit BMU closes the relays REL1 and REL2 in response to an acceleration command from the engine control unit ECU. As a result, a DC voltage is supplied from the assembled battery assy to the inverter INV. Inverter INV converts a DC voltage into an AC voltage and supplies it to motor generator MG. The motor generator MG generates driving force by receiving supply of AC voltage. The driving force generated by the motor generator MG is transmitted to the driving wheels via a drive shaft or the like, so that the electric vehicle is accelerated.

  When the electric vehicle accelerates, the electric power stored in the battery cell is consumed, and the output voltage of the battery cell drops. Therefore, measures to prevent overdischarge of the battery cell are necessary. Therefore, the voltage monitoring system VMS constantly monitors the output voltage of each battery cell during traveling. For example, when the voltage of any battery cell falls below the warning level voltage, the cell monitoring unit CMU issues a voltage drop alarm to the battery management unit BMU. In response to the voltage drop alarm, the battery management unit BMU issues a remaining charge reduction warning for the assembled battery assy to the engine control unit ECU. The engine control unit ECU displays an alarm for reducing the remaining charge of the assembled battery assy on a display device or the like provided in the driver's seat, and notifies the driver that the battery cell may be over-discharged. As a result, the voltage monitoring system VMS can prompt the driver to take an overdischarge prevention measure such as stoppage of travel.

  In addition, when the remaining charge reduction alarm of the assembled battery assy is left and the vehicle continues to travel after that, the output voltage of the battery cell further decreases. Therefore, in order to prevent overdischarge of the battery cell, it is necessary to stop discharge of each battery cell. For example, when the voltage of any battery cell falls below the emergency stop level voltage, the cell monitoring unit CMU issues an emergency stop alarm to the battery management unit BMU. The emergency stop level voltage is desirably set to a voltage value larger than the overdischarge threshold voltage level having a sufficient margin from the voltage level at the time of overdischarge in order to reliably prevent occurrence of overdischarge of the battery cell. .

  The battery management unit BMU activates an emergency stop operation in response to an emergency stop alarm from the cell monitor unit CMU. Specifically, the battery management unit BMU opens the relays REL1 and REL2, and cuts off the power supply from the assembled battery assy to the inverter INV. Thereby, the output voltage drop of a battery cell stops. Further, the battery management unit BMU notifies the engine control unit ECU of the execution of the emergency stop operation. The engine control unit ECU displays that the emergency stop operation has been activated on a display device or the like provided in the driver's seat. Thereby, generation | occurrence | production of the overdischarge of a battery cell can be prevented reliably.

  Next, a case where the electric vehicle is decelerated will be described. When the electric vehicle is decelerated, the engine control unit ECU detects a driver's operation such as depression of a brake pedal, for example, and issues a deceleration command for decelerating the electric vehicle to the inverter INV and the battery management unit BMU. . In the inverter INV, the operation mode is switched from AC to DC conversion mode in response to a deceleration command from the engine control unit ECU. The battery management unit BMU closes the relays REL1 and REL2 in response to a deceleration command from the engine control unit ECU. Motor generator MG generates power by the rotational force of the tire transmitted via a drive shaft or the like. The rotational resistance generated by the power generation is transmitted to the drive wheels as a braking force via a drive shaft or the like. Thereby, the electric vehicle decelerates. This braking method is generally referred to as regenerative braking operation. The AC voltage generated by the regenerative braking operation is supplied to the inverter INV. The inverter INV converts the AC voltage from the motor generator MG into a DC voltage and supplies it to the assembled battery assy. Thereby, the assembled battery assy is charged with the voltage recovered by the regenerative braking operation.

  Since the assembled battery assy is charged during the regenerative braking operation, the output voltage of each battery cell rises. Therefore, measures to prevent overcharging of the battery cell are necessary. Therefore, the voltage monitoring system VMS constantly monitors the output voltage of each battery cell during traveling. The cell monitoring unit CMU determines whether or not the output voltage of each battery cell at the start of the regenerative braking operation is equal to or lower than the charge upper limit voltage. When there is a battery cell having an output voltage higher than the upper limit charging voltage, the cell monitoring unit CMU issues an overcharge alarm to the battery management unit BMU. The battery management unit BMU opens the relays REL1 and REL2 in response to the overcharge alarm and prevents the assembled battery assy from being charged.

  Further, the cell monitoring unit CMU continues to monitor the output voltage of the battery cell even during charging by the regenerative braking operation. When a battery cell whose output voltage reaches the charge upper limit voltage is found, the cell monitor unit CMU issues an overcharge alarm to the battery management unit BMU. The battery management unit BMU opens the relays REL1 and REL2 in response to the overcharge alarm and prevents the assembled battery assy from being charged. Thereby, the overcharge of the assembled battery assy can be prevented.

  In the above description, the operation of the voltage monitoring system VMS has been described on the assumption that the voltage of the battery cell can be normally detected. However, in some cases, the output voltage of the battery cell may not be normally detected. For example, if the wiring between the voltage monitoring modules VMM1 to VMMn and the assembled battery assy is disconnected, the voltage at the disconnection part abnormally drops or abnormally increases, and the cell monitor unit CMU cannot calculate a normal voltage. When such a disconnection occurs, it becomes impossible to monitor the output voltage of the battery cell, which is the purpose of the voltage monitoring system VMS, so it is required to detect a disconnection failure.

  Therefore, the cell monitor unit CMU stores in advance an appropriate range of output voltage values. When the calculated output voltage value of the battery cell deviates from the appropriate range, the cell monitoring unit CMU determines that a disconnection failure has occurred. Then, the cell monitoring unit CMU notifies the battery management unit BMU that a disconnection failure has occurred. The battery management unit BMU opens the relays REL1 and REL2 and disconnects the connection between the inverter INV and the assembled battery assy in response to the notification of the occurrence of the disconnection failure. This prevents a further failure from occurring in the system. Further, the battery management unit BMU notifies the engine control unit ECU of the occurrence of the disconnection failure. The engine control unit ECU displays the occurrence of the disconnection failure on a display device or the like provided in the driver's seat, and notifies the driver of the occurrence of the failure. As described above, the voltage monitoring system VMS can also detect the occurrence of a disconnection failure. In order to detect the occurrence of the disconnection failure, the voltage monitoring modules VMM1 to VMMn need to have a configuration for detecting the disconnection failure. This configuration is disclosed in, for example, Japanese Patent Application No. 2012-122688. ing.

  Note that the configuration and operation of the voltage monitoring system VMS are merely examples. Therefore, for example, the cell monitor unit CMU and the battery management unit BMU can be integrated into one circuit block. Moreover, it is possible to mutually substitute all or part of the functions shared by the cell monitoring unit CMU and the battery management unit BMU. Furthermore, the cell monitoring unit CMU, the battery management unit BMU, and the engine control unit ECU can be integrated into one circuit block. The engine control unit ECU can replace all or part of the functions of the cell monitoring unit CMU and the battery management unit BMU.

Embodiment 1
In the above description, the configuration and operation of the voltage monitoring system VMS have been described with reference to FIGS. The semiconductor device according to the first embodiment includes a transmission circuit and a reception circuit. The transmission circuit and the reception circuit can be applied to the voltage monitoring modules VMM1 to VMMn described above. Therefore, a control command transmission procedure in the voltage monitoring system VMS including the semiconductor device according to the first embodiment (for example, the voltage monitoring modules VMM1 to VMMn) will be described.

  FIG. 4 shows a timing chart showing the control procedure of the voltage monitoring module in the voltage monitoring system VMS. As shown in FIG. 4, in the voltage monitoring system VMS, the cell monitoring unit CMU issues a first command (for example, a voltage monitoring operation start command VMST based on an instruction from the battery management unit BMU, which is a host system, to 4, the cell monitoring unit CMU designates the voltage monitoring module VMM2 and issues a voltage monitoring operation start command VMST, which is the voltage monitoring operation start command VMST. First, the voltage monitoring module VMMn located at the lowest position of the daisy chain receives the voltage monitoring operation start command VMST since the voltage monitoring operation start command VMST is not addressed to itself. To the voltage monitoring module VMMn-1 located in the stage. In the monitoring system VMS, if the command received is not addressed to itself, the voltage monitoring module which has received the instruction sequence transmitted to the next stage of the voltage monitoring module.

  When the voltage monitoring operation start command VMST specifying the voltage monitoring module VMM2 reaches the voltage monitoring module VMM2, the voltage monitoring module VMM2 outputs a response signal ACK indicating that the reception has been performed correctly. Further, the voltage monitoring module VMM2 starts the voltage monitoring operation based on the voltage measurement operation start command VMST. On the other hand, in the example illustrated in FIG. 4, the response signal ACK is transmitted from the voltage monitoring module VMM2 to the voltage monitoring module VMM1 positioned above the voltage monitoring module VMM2. At this time, since the voltage monitoring module VMM1 is located at the top of the daisy chain, it transmits the received response signal ACK to the cell monitoring unit CMU.

  The cell monitoring unit CMU that has received the response signal ACK recognizes that the voltage monitoring operation start command VMST has normally reached the voltage monitoring module VMM2. Then, the cell monitoring unit CMU acquires measurement results based on an instruction from the battery management unit BMU. In the example illustrated in FIG. 4, the cell monitoring unit CMU issues a second command (for example, a voltage value output command GETRES) that designates the voltage monitoring module VMM2 and instructs transmission of the measurement result. This voltage value output command GETRES is transmitted from the lower order to the higher order of the voltage monitoring modules constituting the daisy chain, similar to the voltage monitoring operation start instruction VMST. When the voltage monitoring module VMM2 receives the voltage value output command GETRES, the voltage monitoring module VMM2 outputs the measurement result RES of the battery cell indicated by the voltage value output command GETRES.

  Then, the measurement result RES is transmitted from the voltage monitoring module VMM2 to the voltage monitoring module VMM1 positioned above the voltage monitoring module VMM2. At this time, since the voltage monitoring module VMM1 is located at the top of the daisy chain, the received measurement result RES is transmitted to the cell monitoring unit CMU.

  As described above, in the voltage monitoring system VMS, the cell monitoring unit CMU transmits the control signal and receives the measurement result via the voltage monitoring modules connected in a daisy chain. At this time, in the voltage monitoring system VMS, since the voltage monitoring modules VMM1 to VMMn operate with different power supply voltages, signals are transmitted and received by increasing / decreasing the current flowing through the wiring connecting the voltage monitoring modules.

  FIG. 5 is a block diagram of the voltage monitoring module including the receiving circuit and the transmitting circuit according to the first embodiment. Since all of the voltage monitoring modules VMM1 to VMMn have the same configuration, FIG. 5 shows the voltage monitoring module VMM1 as a representative example of the voltage monitoring module.

  As shown in FIG. 5, the voltage monitoring module VMM1 includes a communication circuit, a voltage measurement circuit, a control circuit, a register, a cell balance circuit, and a power supply circuit. The communication circuit includes a reception circuit 1 and a transmission circuit 2. The receiving circuit 1 receives a current signal output from a voltage monitoring module located on the lower side of the daisy chain. The reception circuit 1 generates a reception signal from the current signal and transmits the reception signal to the control circuit. Then, the control circuit analyzes the transmitted command transmitted based on the received signal and, if the received command is addressed to itself, gives an operation command to the voltage measurement circuit, the register, and the like. Further, the control circuit instructs the transmission circuit 2 to output the signal received by the reception circuit 1 as it is unless the received command is addressed to itself. The transmission circuit 2 outputs the data instructed by the control circuit to the voltage monitoring module located in the upper part of the daisy chain. Note that the operations of the reception circuit 1, the control circuit, the transmission circuit 2, and the like are examples, and can be arbitrarily set. Hereinafter, the description of the operation in which the reception circuit 1, the control circuit, the transmission circuit 2, and the like cooperate will be omitted.

  The voltage monitoring module according to the first embodiment has one characteristic in the configuration of the receiving circuit 1. Therefore, the receiving circuit 1 will be described in detail below. The receiving circuit 1 according to the first embodiment includes another semiconductor device (for example, a lower voltage monitoring module) that operates based on a power supply in a power supply voltage range lower than that of the own semiconductor device (for example, a higher voltage monitoring module). The signal current output from the transmission circuit 2 provided in the receiver is received. FIG. 6 shows a detailed circuit diagram of the receiving circuit 1 and the transmitting circuit 2 according to the first embodiment. In FIG. 6, in order to explain the connection relationship between the receiving circuit 1 and the transmitting circuit 2, the receiving circuit 1 provided in the voltage monitoring module located on the upper side and the transmitting circuit provided in the voltage monitoring module located on the lower side. 2 was shown. Note that the voltage monitoring module according to the first embodiment includes both the reception circuit 1 and the transmission circuit 2. Further, FIG. 6 shows the transmission line LINE that connects the upper voltage monitoring module and the lower voltage monitoring module. The transmission line LINE is a line through which a signal current transmitted from the lower voltage monitoring module to the upper voltage monitoring module flows, and constitutes a daisy chain communication network. The transmission line LINE serves as a noise mixing path from a motor or the like.

  In the example shown in FIG. 6, the receiving circuit 1 provided in the upper voltage monitoring module includes a low-potential power supply voltage GND having a voltage of 30V in absolute value and a high-potential power supply voltage having a voltage of 35V in absolute value. Based on VDDU. On the other hand, the transmission circuit 2 provided in the lower voltage monitoring module is based on the low potential power supply voltage GND having a voltage of 0V in absolute value and the high potential power supply voltage VDDU having a voltage of 5V in absolute value. Operate. That is, the receiving circuit 1 receives the signal current output from the transmitting circuit 2 that operates in different power supply voltage ranges and generates a received signal. This is because in the voltage monitoring system VMS, a battery module that supplies power to the lower voltage monitoring module and a battery module that supplies power to the upper voltage monitoring module are connected in series.

  As illustrated in FIG. 6, the reception circuit 1 includes an input stage circuit 10, an adjustment circuit 12, and a comparator 15. The receiving circuit 1 includes an NPN transistor Tr1, an NMOS transistor N15, and a diode D. The NPN transistor Tr1 prevents a high voltage (for example, a voltage exceeding the high potential side power supply voltage VDDU) from being applied to the input stage circuit 10 due to noise. The NMOS transistor N15 and the diode D prevent the input stage circuit 10 from being applied with a low voltage due to noise (for example, a voltage lower than the low potential side power supply voltage GND). That is, the receiving circuit 1 has a transmission wiring that transmits the signal current from the transmission circuit 2 to the first wiring W11, and includes the NPN transistor Tr1 on the transmission wiring. The receiving circuit 1 includes an NMOS transistor N15 and a diode D as a backflow prevention circuit connected between the transmission line and the low potential side power supply line.

  The input stage circuit 10 includes a first resistor (for example, a resistor R11), a second resistor (for example, a resistor R12), a first current mirror circuit (for example, a current mirror circuit 11), a first wiring W11, and a first wiring W11. Two wirings W12 are provided.

  The resistor R11 and the resistor R12 include a high potential side power supply wiring (for example, a power supply wiring to which the high potential side power supply voltage VDDU is supplied) and a low potential side power supply wiring (for example, a power supply wiring to which the low potential side power supply voltage GND is supplied). One end is connected to one of the two.

  In the current mirror circuit 11, a first terminal (for example, a source terminal) is connected to the other of the high potential side power supply line and the low potential side power supply line, and a control terminal (for example, a gate) is commonly connected. A second transistor (for example, NMOS transistors N11 and N12) is included. In the current mirror circuit 11, the gate of the first transistor (for example, NMOS transistor N11) and the second terminal (for example, drain) are connected to each other.

  The first wiring W11 connects the resistor R11 and the drain of the NMOS transistor N11. The first wiring W11 has a current input node ND to which the signal current Iin is input. A first voltage (for example, input voltage VA) is generated in the first wiring W11 according to the magnitude of the current I11 flowing through the resistor R11.

  The second wiring W12 connects the resistor R12 and the drain of the NMOS transistor N12. A second voltage (for example, comparison voltage VB) is generated in the second wiring W12 according to the magnitude of the current I12 flowing through the resistor R12.

  The adjustment circuit 12 generates an adjustment current Iadj whose magnitude varies depending on the voltage difference between the input voltage VA generated in the first wiring W11 and the comparison voltage VB generated in the second wiring W12. Then, the adjustment circuit 12 supplies the adjustment current Iadj to the second wiring W12. When the voltage difference between the input voltage VA and the comparison voltage VB becomes larger than the steady state, the adjustment circuit 12 applies the adjustment current Iadj to the second wiring W12 to bring the voltage difference back to the steady state voltage difference.

  The adjustment circuit 12 includes a differential amplifier 13, an output transistor (for example, PMOS transistor P11), and a second current mirror circuit (for example, current mirror circuit 14). The differential amplifier 13 varies the voltage level of the control signal based on the voltage difference between the input voltage VA and the comparison voltage VB. The PMOS transistor P11 varies the magnitude of the adjustment current Iadj based on the voltage level of the control signal. The current mirror circuit 14 generates the adjustment current Iadj based on the current output from the PMOS transistor P11. The current mirror circuit 14 includes third and fourth transistors (for example, NMOS transistors N13 and N14) having a source terminal connected to the other of the high potential side power supply wiring and the low potential side power supply wiring and a gate connected in common. including. In the current mirror circuit 14, the gate and drain of the NMOS transistor N13 are connected to each other. In the current mirror circuit 14, the drain of the NMOS transistor N14 is connected to the second wiring W12, and the adjustment current Iadj is drawn from the second wiring W12.

  The comparator 15 inverts the logic level of the reception signal DOUT based on the magnitude relationship between the input voltage VA and the comparison voltage VB. Further, the comparator 15 inverts the logic level of the reception signal DOUT in response to the voltage difference between the input voltage VA and the comparison voltage VB becoming larger than a predetermined voltage difference set in advance. That is, the comparator 15 has hysteresis. The comparator 15 can improve resistance to noise components of the input voltage VA and the comparison voltage VB by having hysteresis, but can operate even if it does not have hysteresis.

  As shown in FIG. 6, the transmission circuit 2 transfers data by outputting a current Iout1 to the voltage monitoring module located on the upper side. At this time, the transmission circuit 2 outputs the current Iout in a direction in which the current Iout is drawn from the upper voltage monitoring module to the lower voltage monitoring module. The transmission circuit 2 increases the current Iout1 when the logic level of data to be transmitted is the first logic level (for example, high level), and when the data logic level is the second logic level (for example, low level). The current Iout1 is decreased. For example, the transmission circuit 2 sets the current Iout1 to about 1 mA if the data is data 0 (for example, the logic level is low), and sets the current Iout1 to about 0 mA if the data is data 1 (for example, the logic level is high). And

  As illustrated in FIG. 6, the transmission circuit 2 includes a transmission data generation unit 20 and an output stage circuit 21. The transmission data generation unit 20 reads data to be transmitted from the register based on an instruction from a control circuit (not shown), and outputs a current Iout0 according to the logic level of the data. The output stage circuit 21 outputs a signal current (for example, Iout1) according to the current Iout0.

  The output stage circuit 21 includes NMOS transistors N21 to N24. The NMOS transistors N21 and N22 constitute a current mirror circuit. The NMOS transistors N23 and N24 constitute a current mirror circuit. Specifically, the current Iout0 is input to the drain of the NMOS transistor N21. The gate and drain of the NMOS transistor N21 are connected to each other. The source of the NMOS transistor N21 is connected to the drain of the NMOS transistor N23. The gate of the NMOS transistor N22 is connected in common with the gate of the NMOS transistor N21. The drain of the NMOS transistor N22 is connected to the external terminal and outputs a current Iout1. The source of the NMOS transistor N22 is connected to the drain of the NMOS transistor N24. The gate and drain of the NMOS transistor N23 are connected to each other. The source of the NMOS transistor N23 is connected to a low potential side power supply line to which the ground voltage GND is supplied. The gate of the NMOS transistor N24 is connected in common with the gate of the NMOS transistor N23. The source of the NMOS transistor N24 is connected to the low potential side power supply wiring.

  In the voltage monitoring module according to the first exemplary embodiment, the reception circuit 1 is provided, so that a reception signal can be correctly generated even if noise is mixed in the transmission signal via the transmission line LINE. Thus, the operation of the receiving circuit 1 according to the first embodiment will be described.

  First, in describing the operation of the voltage monitoring module according to the first embodiment, first, the operation of the reception circuit 1 having only the input stage circuit 10 when the adjustment circuit 12 is invalidated, that is, the operation will be described. In this case, the adjustment current Iadj does not flow (IAdj = 0 mA). FIG. 7 is a timing chart showing the operation of the receiving circuit 1 according to the first embodiment in which the adjustment circuit 12 is invalidated.

  As shown in FIG. 7, when the adjustment circuit 12 is invalid, the adjustment current Iadj is 0 mA regardless of increase or decrease of the current Iin. In the example shown in FIG. 7, when the input data indicates data 1 (for example, the period between timings T1 to T2 and T3 to T4), the current Iin becomes 0 mA, and the input data indicates data 0 (for example, It becomes a size of about 1 mA in the period of timing T2 to T3.

  When the current Iin indicates data 1, the current I12 having the same magnitude as the current I11 is supplied to the resistor R12 by the current mirror circuit 11. Therefore, when the current Iin indicates data 0, the current I11 and the current I12 have the same magnitude. That is, when the current Iin indicates data 0, the input voltage VA and the comparison voltage VB have the same voltage value.

  On the other hand, when the current Iin indicates data 0, the current I11 increases as the current Iin increases. At this time, since the current flowing through the current mirror circuit 11 decreases, when the current Iin indicates data 0, the current I12 decreases. Therefore, when the current Iin indicates data 0, the input voltage VA is lower and the comparison voltage VB is higher than when the current Iin indicates data 1.

  As described above, when the adjustment circuit 12 is invalidated, the input voltage VA and the comparison voltage VB approach the same voltage, but the magnitude relationship of the voltages does not change. There is no reversal. Therefore, in a state where the adjustment circuit 12 is disabled, the reception signal DOUT is maintained at a low level, and data cannot be received correctly. The adjustment circuit 12 generates the adjustment current Iadj for the operation of the input stage circuit 10 so that the comparator 15 can correctly generate the reception signal DOUT.

  In the following description, the voltage of the input voltage VA and the comparison voltage VB when the current Iin is at a low level is referred to as a common voltage Vcom. The common voltage Vcom is a voltage that serves as a threshold value for whether the adjustment current Iadj is 0 mA or a current value higher than that. That is, the adjustment circuit 12 maintains the adjustment current Iadj at 0 mA when the input voltage VA becomes equal to or higher than the common voltage Vcom. This is because, in order for the adjustment circuit 12 to make the voltage value of the comparison voltage VB equal to or higher than the common voltage Vcom by the adjustment current Iadj, it is necessary to cause a current to flow into the second wiring W12. This is because there is no configuration for allowing current to flow into the wiring W12.

  Next, the operation of the receiving circuit 1 in which the adjustment circuit 12 is validated, that is, the operation of the receiving circuit 1 shown in FIG. 6 will be described. FIG. 8 is a timing chart showing the operation of the receiving circuit 1 according to the first embodiment. The example shown in FIG. 8 shows the operation of the receiving circuit 1 when no noise is input or when noise having a voltage near the midpoint of the noise waveform is applied.

  As shown in FIG. 8, when the adjustment circuit 12 is operating effectively, the adjustment circuit 12 outputs an adjustment current Iadj, and the adjustment current Iadj causes the voltage of the comparison voltage VB to follow the fluctuation of the input voltage VA. More specifically, the operation is as follows.

  At timings T11 and T13, the current Iin changes from data 0 to data 1. Accordingly, at the timings T11 and T13, the current Iin decreases, so the current I11 flowing through the resistor R11 decreases. On the other hand, the current I12 has a magnitude obtained by adding the adjustment current Iadj (for example, the current magnitude is IHadj) and the current flowing through the current mirror circuit 11 in the current I11 in the period immediately before the timings T11 and T13. Then, at the timings T11 and T13, the current flowing through the current mirror circuit 11 increases in accordance with the decrease in the current Iin. Therefore, at the timings T11 and T13, the current I12 increases from the current mirror circuit 11 added to the adjustment current Iadj having the magnitude of the current value IHadj, so that the current I12 increases from the period before the timings T11 and T13. To do. As a result, at the timings T11 and T13, the input voltage VA increases due to the decrease in the current I11, but the comparison voltage VB decreases due to the increase in the current I12. Therefore, the adjustment circuit 12 decreases the adjustment current Iadj based on the voltage difference between the input voltage VA and the comparison voltage VB, and sets the magnitude of the adjustment current Iadj to ILadj (for example, 0 mA). Thereby, in the second half of the period from the timing T11 to T12 and the period from the timing T13 to T14, the input voltage VA and the comparison voltage VB are the same voltage (as in the period from the timing T11 to T12 in FIG. For example, the common voltage Vcom).

  On the other hand, at timing T12, the current Iin changes from data 1 to data 0. Accordingly, at the timing T12, the current Iin increases, so the current I11 flowing through the resistor R11 increases. On the other hand, the current I12 has the magnitude of the current I11 when the current Iin is 0 mA in the period immediately before the timing T12. At time T12, the current flowing through the current mirror circuit 11 decreases in accordance with the increase in the current Iin. At timing T12, the adjustment current Iadj is still 0 mA. Therefore, at the timing T12, the current I12 flowing through the resistor R12 decreases. Thereby, at the timing T12, the input voltage VA decreases due to the increase in the current I11, but the comparison voltage VB increases due to the decrease in the current I12. Therefore, the adjustment circuit 12 increases the adjustment current Iadj based on the voltage difference between the input voltage VA and the comparison voltage VB, and sets the magnitude of the adjustment current Iadj to IHadj. As a result, the current I12 increases by an increase of the adjustment current Iadj, and the voltage value of the comparison voltage VB decreases. In the latter half of the period from the timing T12 to T13, the input voltage VA and the comparison voltage VB are the same voltage, unlike the period from the timing T12 to T13 in FIG.

  Thus, by using the adjustment circuit 12, the magnitude relationship between the input voltage VA and the comparison voltage VB is reversed in the receiving circuit 1 in accordance with the switching of input data. Thereby, in the receiving circuit 1, the comparator 15 can generate the reception signal DOUT whose logic level is switched in accordance with the switching of the logic level of the input data.

  Next, the operation of the receiving circuit 1 according to the first embodiment when noise having a voltage near the upper vertex and near the lower vertex of the noise waveform is applied will be described. First, FIG. 9 shows a timing chart showing the operation of the receiving circuit 1 when noise having a voltage near the upper vertex of the noise waveform is applied.

  As shown in FIG. 9, when the amplitude of noise is near the upper vertex, the input voltage VA transitions at a voltage value higher than the common voltage Vcom. However, when the input voltage VA becomes higher than the common voltage Vcom, the adjustment circuit 12 cannot flow current into the second wiring W12, so that the comparison voltage VB is set to a voltage higher than the common voltage Vcom. It cannot be adjusted. Therefore, in the example shown in FIG. 9, the adjustment current Iadj maintains 0 mA. Even in this case, the receiving circuit 1 changes the current values of the currents I11 and I12 with opposite phases as the current Iin increases or decreases. The input voltage VA and the comparison voltage VB change in voltage with opposite phases, but the magnitude relationship between the voltages repeatedly reverses with the transition of the current Iin. Therefore, the comparator 15 switches the logic level of the reception signal DOUT every time the voltage values of the input voltage VA and the comparison voltage VB are reversed. More specifically, the comparator 15 sets the reception signal DOUT to the high level during the period from the timing T21 to T22 and the period from the timing T23 to T24, and sets the reception signal DOUT to the low level during the period from the timing T22 to T23.

  FIG. 10 is a timing chart showing the operation of the receiving circuit 1 when noise having a voltage near the lower apex of the noise waveform is applied. As shown in FIG. 10, in this example, the current Iin transitions from data 0 to data 1 at timings T31 and T33. Accordingly, at the timings T31 and T33, the current Iin decreases, so the current I11 flowing through the resistor R11 decreases. On the other hand, the current I12 has a magnitude obtained by adding the adjustment current Iadj (for example, the current magnitude is IHadj) and the current flowing through the current mirror circuit 11 out of the current I11 in the period immediately before the timings T31 and T33. Then, at the timings T31 and T33, the current flowing through the current mirror circuit 11 increases in accordance with the decrease in the current Iin. Therefore, at the timings T31 and T33, the current I12 increases from the current mirror circuit 11 added to the adjustment current Iadj having the magnitude of the current value IHadj, so that the current I12 increases from the period before the timings T31 and T33. To do. As a result, at the timings T31 and T33, the input voltage VA increases due to the decrease in the current I11, but the comparison voltage VB decreases due to the increase in the current I12. Therefore, the adjustment circuit 12 reduces the adjustment current Iadj based on the voltage difference between the input voltage VA and the comparison voltage VB, and sets the magnitude of the adjustment current Iadj to ILadj. In the example shown in FIG. 10, even if the input voltage VA becomes high level, the current value ILadj is larger than 0 mA because the voltage is smaller than the common voltage Vcom. As a result, the input voltage VA and the comparison voltage VB are the same voltage (for example, the common voltage Vcom) in the second half of the period from the timing T31 to T32 and the period from the timing T33 to T34.

  On the other hand, at timing T32, the current Iin changes from data 1 to data 0. Accordingly, at the timing T32, the current Iin increases, so the current I11 flowing through the resistor R11 increases. On the other hand, the current I32 has a magnitude obtained by adding the adjustment current Iadj having the magnitude of the current value ILadj to the current I11 when the current Iin is 0 mA in the period immediately before the timing T32. At time T32, the current flowing through the current mirror circuit 11 decreases in accordance with the increase in the current Iin. Further, at the timing T32, the adjustment current Iadj still has the current value ILadj. Therefore, at the timing T32, the current I12 flowing through the resistor R12 decreases. Thereby, at the timing T32, the input voltage VA decreases due to the increase in the current I11, but the comparison voltage VB increases due to the decrease in the current I12. Therefore, the adjustment circuit 12 increases the adjustment current Iadj based on the voltage difference between the input voltage VA and the comparison voltage VB, and sets the magnitude of the adjustment current Iadj to the current value IHadj. As a result, the current I12 increases by an increase of the adjustment current Iadj, and the voltage value of the comparison voltage VB decreases. In the second half of the period from timing T32 to T33, the input voltage VA and the comparison voltage VB are the same voltage.

  As described above, by using the adjustment circuit 12, in the receiving circuit 1, when noise having a voltage near the upper vertex of the noise waveform is applied and when noise having a voltage near the lower vertex is applied. In either case, the magnitude relationship between the input voltage VA and the comparison voltage VB is reversed according to the switching of the input data. Thereby, in the receiving circuit 1, even when noise is applied, the comparator 15 can generate the reception signal DOUT whose logic level is switched according to the switching of the logic level of the input data.

  Next, FIG. 11 shows a timing chart showing the operation of the transmission circuit 1 according to the first embodiment for a longer period than the timing charts shown in FIGS. The left diagram of the timing chart shown in FIG. 11 shows the reception operation when no noise is mixed, and the right diagram shows the reception operation when noise is mixed. The noise has, for example, a frequency of several kHz to several tens of kHz and an amplitude of about 500 Vpp.

  As shown in the left diagram of FIG. 11, when there is no noise, the receiving circuit 1 generates the input voltage VA and the comparison voltage VB according to the signal current output by the transmitting circuit 2 according to the operation shown in FIG. Then, the reception circuit 1 compares the input voltage VA and the comparison voltage VB to generate a reception signal DOUT. The reception signal DOUT is output without interruption during the period in which the signal current is input.

  Further, as shown in the right diagram of FIG. 11, when the signal current is input while being superimposed on the noise, the signal waveform on the transmission line LINE is greatly distorted by the noise. In the example shown in FIG. 11, when the mixed noise is on the lower side of the noise waveform, the upper signal is missing. Since noise is input through the parasitic capacitance of the transmission wiring, a phase shift occurs between the actual noise waveform and the signal waveform on the transmission wiring. However, even in such a case, the receiving circuit 1 according to the first embodiment can be compared with the input voltage VA by causing the voltage level of the comparison signal VB to follow noise in accordance with the operation described in FIGS. The voltage level. As a result, the receiving circuit 1 according to the first embodiment can generate the same received signal DOUT as when no noise is mixed even when noise is mixed.

  Here, as a comparative example, a general reception circuit 100 that generates a reception signal DOUT by comparing a reference voltage Vref having a fixed voltage value with an input voltage VA generated based on a signal current will be described. The effects of the receiving circuit 1 will be described by comparing the general receiving circuit 100 and the receiving circuit 1 according to the first embodiment.

  FIG. 12 shows a block diagram of a voltage monitoring module having a general receiving circuit 100. As shown in FIG. 12, the receiving circuit 100 divides the ground voltage GND and the power supply voltage VDDU given to the receiving circuit 100 by the resistors R102 and R103 to generate the reference voltage Vref. In the receiving circuit 100, the input voltage VA is generated by applying the current Iin to the resistor R101. Then, the receiving circuit 100 generates a reception signal DOUT by comparing the magnitude relationship between the reference voltage Vref and the input voltage VA by the comparator 111.

  A timing chart showing the operation of this general receiving circuit 100 is shown in FIG. The timing chart shown in FIG. 13 is the same as the timing chart described in FIG. Further, the left diagram of the timing chart shown in FIG. 13 shows the reception operation when no noise is mixed, and the right diagram shows the reception operation when noise is mixed.

  As shown in the left diagram of FIG. 13, when there is no noise, the general receiving circuit 100 has the magnitude relationship between the input voltage VA and the reference voltage Vref reversed according to the transition of the input data. The reception signal DOUT can be generated in the same manner as the reception circuit 1 according to the above. The reception signal DOUT is output without interruption during the period in which the signal current is input.

  On the other hand, as shown in the right diagram of FIG. 13, when the signal current is superimposed on the noise, the signal waveform on the transmission line LINE is greatly distorted by the noise. In the example shown in FIG. 13, when the mixed noise is on the lower side of the noise waveform, the upper signal is missing. At this time, in the general reception circuit 100, the input voltage VA cannot fall below the reference voltage Vref and the reception signal DOUT is correctly output during the period in which the input data is superimposed on the noise having the voltage above the noise waveform. Not. That is, even if it is attempted to discriminate input data from a fixed reference voltage Vref as in a general receiving circuit 100, the reception signal DOUT cannot be generated if noise is mixed.

  From the above description, the receiving circuit 1 according to the first embodiment includes the input stage circuit 10, the adjustment circuit 12, and the comparator 15. Then, the input stage circuit 10 generates an input voltage VA and a comparison voltage VB that are in opposite phases according to switching of the current value of the current Iin when the adjustment current Iadj is not input. Further, the adjustment circuit 12 outputs the adjustment current Iadj in response to the increase in the voltage difference between the input voltage VA and the comparison voltage VB when the input voltage VA is lower than the preset common voltage Vcom, and the comparison voltage VB. Is adjusted to the same voltage as the input voltage VA. The receiving circuit 1 generates a reception signal DOUT by determining the magnitude relationship between the input voltage VA and the comparison voltage VB by the comparator 15. With the receiving circuit 1 according to the first exemplary embodiment, the reception signal DOUT can be generated without interruption even when noise is applied via the communication path.

  Further, as described above, the circuit described in Patent Document 1 has a problem that noise having a frequency lower than that of the transmission signal such as motor noise cannot be removed, although noise having a frequency higher than that of the transmission signal can be removed. On the other hand, in the receiving circuit 1 according to the first embodiment, reception is performed even when the voltage of the input voltage VA generated from the signal current is increased or decreased due to the application of noise having a frequency lower than that of the transmission signal. The signal DOUT can be generated without interruption.

  Here, as another method for improving resistance to noise, in addition to using the receiving circuit 1 according to the first embodiment, a method using a differential signal is generally considered. However, when a differential signal is used as a transmission signal, two signal lines are required. When the number of signal lines increases in this way, problems such as an increase in the size of the semiconductor device due to an increase in the number of terminals of the semiconductor device and an increase in the weight of the system accompanying an increase in the number of wirings occur.

  Further, when noise resistance is improved by removing noise with an inverter having a multistage structure as in Patent Document 1, there is a problem that the number of circuit elements increases and the circuit area of the semiconductor device increases.

  Further, as a general method for removing noise having a frequency lower than that of a transmission signal such as motor noise, it is conceivable to install a low-pass filter or the like in the input stage to remove low-frequency noise. However, a low-pass filter that removes low-frequency noise must use a large-capacitance capacitor, and there is still a problem that the circuit area increases or the number of parts increases.

  In particular, the assembled battery is a combination of a large number of battery cells, and the increase in each component and member has a great influence on the cost and weight. In addition, the assembled battery is mounted on an automobile, and the problem of an increase in cost and the problem of an increase in weight accompanying an increase in the number of parts are particularly serious problems.

  For such a problem, in the receiving circuit 1 according to the first embodiment, the reception signal DOUT is generated based on the signal current transmitted through a single line, so that the number of terminals of the semiconductor device and the number of signal lines increase. The problem does not arise. Furthermore, in the receiving circuit 1 according to the first embodiment, noise resistance can be improved without using a multi-stage input stage, a large input capacitance, and the like, so that the circuit area can be reduced. That is, by using the receiving circuit 1 according to the first embodiment, it is possible to solve the problems of an increase in cost and an increase in the number of parts that occur in the signal transmission path in the assembled battery.

Embodiment 2
In the above detailed description, the voltage monitoring module VMMn for monitoring the cell voltage of the battery module EMn arranged on the low potential side is changed to the voltage monitoring module VMM1 for monitoring the cell voltage of the battery module EM1 arranged on the high potential side. The transmission circuit 2 and the reception circuit 1 used in the upstream path for transmitting data or commands have been described.

  However, in a voltage monitoring system, a system may be constructed using a downstream path. In this downstream path, from the voltage monitoring module VMM1 that monitors the cell voltage of the battery module EM1 arranged on the high potential side to the voltage monitoring module VMMn that monitors the cell voltage of the battery module EMn arranged on the low potential side. Transmit data or commands. Therefore, in the second embodiment, the semiconductor device is provided in another semiconductor device (for example, a higher-side voltage monitoring module) that operates based on a power supply in a power supply voltage range higher than that of the own semiconductor device (for example, a lower-side voltage monitoring module). The receiving circuit 3 that receives the signal current output from the transmitting circuit 4 will be described. The voltage monitoring system VMS according to the second embodiment and the receiving circuit according to the second embodiment will be described below. In the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  Therefore, FIG. 14 shows a block diagram of the main part of the voltage monitoring system VMS showing the connection relationship between the voltage monitoring modules VMM1 to VMMn and the cell monitoring unit CMU in the second embodiment. As shown in FIG. 14, the voltage monitoring system VMS according to the second embodiment includes an upstream wiring network UPL and a downstream wiring network DNL. As described above, in the voltage monitoring system VMS according to the second embodiment, the wiring network used in the upstream and the wiring network used in the downstream are separately provided. In the voltage monitoring module according to the second embodiment, the communication circuit includes an upstream receiving circuit and a downstream receiving circuit. Here, the receiving circuit 1 according to the first embodiment is used as the upstream receiving circuit. In the second embodiment, a receiving circuit used as a downstream receiving circuit will be described.

  FIG. 15 is a timing chart illustrating a control procedure of the voltage monitoring module in the voltage monitoring system VMS according to the second embodiment. As shown in FIG. 15, in the voltage monitoring system VMS, the cell monitoring unit CMU issues a first command (for example, a voltage monitoring operation start command VMST based on an instruction from the battery management unit BMU, which is a host system, to 15, the cell monitoring unit CMU designates the voltage monitoring module VMM2 and issues a voltage monitoring operation start command VMST, which is the voltage monitoring operation start command VMST. First, the voltage monitoring module VMMn located at the lowest position of the daisy chain receives the voltage monitoring operation start command VMST since the voltage monitoring operation start command VMST is not addressed to itself. To the voltage monitoring module VMMn-1 located in the stage. In the voltage monitoring system VMS, if the command received is not addressed to itself, the voltage monitoring module which has received the instruction sequence transmitted to the next stage of the voltage monitoring module.

  When the voltage monitoring operation start command VMST specifying the voltage monitoring module VMM2 reaches the voltage monitoring module VMM2, the voltage monitoring module VMM2 outputs a response signal ACK indicating that the reception has been performed correctly. Further, the voltage monitoring module VMM2 starts the voltage monitoring operation based on the voltage measurement operation start command VMST. On the other hand, in the example shown in FIG. 15, the response signal ACK is transmitted from the voltage monitoring module VMM2 to the cell monitoring unit CMU via the voltage monitoring module VMMn located in the field of the voltage monitoring module VMM2.

  The cell monitoring unit CMU that has received the response signal ACK recognizes that the voltage monitoring operation start command VMST has normally reached the voltage monitoring module VMM2. Then, the cell monitoring unit CMU acquires measurement results based on an instruction from the battery management unit BMU. In the example illustrated in FIG. 15, the cell monitoring unit CMU issues a second command (for example, a voltage value output command GETRES) that designates the voltage monitoring module VMM2 and instructs transmission of the measurement result. This voltage value output command GETRES is transmitted from the lower order to the higher order of the voltage monitoring modules constituting the daisy chain, similar to the voltage monitoring operation start instruction VMST. When the voltage monitoring module VMM2 receives the voltage value output command GETRES, the voltage monitoring module VMM2 outputs the measurement result RES of the battery cell indicated by the voltage value output command GETRES.

  Then, the measurement result RES is transmitted from the voltage monitoring module VMM2 to the cell monitoring unit CMU via the voltage monitoring module VMMn positioned below the voltage monitoring module VMM2.

  As described above, in the voltage monitoring system VMS, the cell monitoring unit CMU transmits the control signal and receives the measurement result via the voltage monitoring modules connected in a daisy chain. At this time, in the voltage monitoring system VMS, the voltage monitoring modules VMM1 to VMMn operate with different power supply voltages, respectively. Therefore, as in the first embodiment, by increasing or decreasing the current flowing through the wiring connecting the voltage monitoring modules, Send and receive.

  FIG. 16 is a block diagram of a voltage monitoring module including a receiving circuit and a transmitting circuit according to the second embodiment. Since the voltage monitoring modules VMM1 to VMMn all have the same configuration, the voltage monitoring module VMM1 is shown as a representative example of the voltage monitoring module in FIG.

As illustrated in FIG. 16, the voltage monitoring module VMM1 includes a communication circuit, a voltage measurement circuit, a control circuit, a register, a cell balance circuit, and a power supply circuit. The communication circuit includes reception circuits 1 and 3 and transmission circuits 2 and 4. The reception circuit 1 and the transmission circuit 2 are used in communication using the upstream wiring network UPL. The transmission circuit 3 and the reception circuit 4 are used in communication using the downstream wiring network DNL. The receiving circuit 4 receives a current signal output from a voltage monitoring module located on the upper side of the daisy chain. The reception circuit 4 generates a reception signal from the current signal and transmits the reception signal to the control circuit. Then, the control circuit analyzes the transmitted command transmitted based on the received signal and, if the received command is addressed to itself, gives an operation command to the voltage measurement circuit, the register, and the like. Further, if the received command is not addressed to itself, the control circuit instructs the transmission circuit 4 to output the signal received by the reception circuit 3 as it is. The transmission circuit 4 outputs the data instructed by the control circuit to the voltage monitoring module located in the lower part of the daisy chain. Note that the operations of the receiving circuits 1, 3, the control circuit, the transmitting circuits 2, 4, etc. are examples, and can be arbitrarily set. Hereinafter, the description of the operation in which the reception circuits 1 and 3, the control circuit, the transmission circuits 2 and 4, etc. cooperate will be omitted.
Next, the receiving circuit 3 according to the second embodiment will be described in detail. FIG. 17 shows a detailed circuit diagram of the receiving circuit 3 and the transmitting circuit 4 according to the second embodiment. In FIG. 17, in order to explain the connection relationship between the receiving circuit 3 and the transmitting circuit 4, the transmitting circuit 4 provided in the voltage monitoring module located on the upper side and the receiving circuit provided in the voltage monitoring module located on the lower side. 3 was shown. Note that the voltage monitoring module according to the second embodiment incorporates both the reception circuit 3 and the transmission circuit 4. In FIG. 17, the transmission line LINE for connecting the upper voltage monitoring module and the lower voltage monitoring module is shown. The transmission line LINE is a line through which a signal current transmitted from the upper voltage monitoring module to the lower voltage monitoring module flows, and constitutes a daisy chain communication network. The transmission line LINE serves as a noise mixing path from a motor or the like.

  In the example shown in FIG. 17, the transmission circuit 4 provided in the upper voltage monitoring module includes a low potential side power supply voltage GND having a voltage of 30V in absolute value and a high potential side power supply voltage having a voltage of 35V in absolute value. Based on VDDU. On the other hand, the receiving circuit 3 provided in the lower voltage monitoring module is based on the low potential power supply voltage GND having a voltage of 0V in absolute value and the high potential power supply voltage VDDU having a voltage of 5V in absolute value. Operate. That is, the receiving circuit 3 receives the signal current output from the transmitting circuit 4 that operates in different power supply voltage ranges and generates a received signal. This is because in the voltage monitoring system VMS, a battery module that supplies power to the lower voltage monitoring module and a battery module that supplies power to the upper voltage monitoring module are connected in series.

  As illustrated in FIG. 17, the reception circuit 3 includes an input stage circuit 30, an adjustment circuit 32, and a comparator 34.

  The input stage circuit 30 includes a first resistor (for example, a resistor R31), a second resistor (for example, a resistor R32), a first current mirror circuit (for example, a current mirror circuit 31), a first wiring W31, and a first wiring W31. Two wirings W32 are provided.

  The resistor R31 and the resistor R32 are a high potential side power supply wiring (for example, a power supply wiring to which the high potential side power supply voltage VDDU is supplied) and a low potential side power supply wiring (for example, a power supply wiring to which the low potential side power supply voltage GND is supplied). One end is connected to one of the two.

  In the current mirror circuit 31, a first terminal (for example, a source terminal) is connected to the other of the high potential side power supply wiring and the low potential side power supply wiring, and a control terminal (for example, a gate) is commonly connected. A second transistor (for example, NMOS transistors P31 and P32) is included. In the current mirror circuit 31, the gate of the first transistor (for example, PMOS transistor P31) and the second terminal (for example, drain) are connected to each other.

  The first wiring W31 connects the resistor R31 and the drain of the PMOS transistor P11. The first wiring W31 has a current input node ND to which the signal current Iin is input. A first voltage (for example, input voltage VA) is generated in the first wiring W31 according to the magnitude of the current I31 flowing through the resistor R31.

  The second wiring W32 connects the resistor R32 and the drain of the PMOS transistor P12. A second voltage (for example, comparison voltage VB) is generated in the second wiring W32 according to the magnitude of the current I32 flowing through the resistor R32.

  The adjustment circuit 32 generates an adjustment current Iadj whose magnitude varies depending on the voltage difference between the input voltage VA generated in the first wiring W31 and the comparison voltage VB generated in the second wiring W32. Then, the adjustment circuit 32 supplies the adjustment current Iadj to the second wiring W32. When the voltage difference between the input voltage VA and the comparison voltage VB becomes larger than that in the steady state, the adjustment circuit 32 returns the voltage difference to the steady state voltage difference by applying the adjustment current Iadj to the second wiring W12.

  The adjustment circuit 32 includes a differential amplifier 33 and an output transistor (for example, a PMOS transistor P33). The differential amplifier 33 varies the voltage level of the control signal based on the voltage difference between the input voltage VA and the comparison voltage VB. The PMOS transistor P33 varies the magnitude of the adjustment current Iadj based on the voltage level of the control signal. Further, the PMOS transistor P33 has a drain connected to the second wiring W12, and directly causes the adjustment current Iadj to flow into the second wiring W12.

  The comparator 34 inverts the logic level of the reception signal DOUT based on the magnitude relationship between the input voltage VA and the comparison voltage VB. Further, the comparator 34 inverts the logic level of the reception signal DOUT in response to the voltage difference between the input voltage VA and the comparison voltage VB becoming larger than a predetermined voltage difference set in advance. That is, the comparator 34 has hysteresis. The comparator 34 can improve resistance to noise components of the input voltage VA and the comparison voltage VB by having hysteresis, but can operate even if it does not have hysteresis.

  As shown in FIG. 17, the transmission circuit 4 transfers data by outputting a current Iout1 to the voltage monitoring module located on the lower side. At this time, the transmission circuit 4 outputs the current Iout in a direction in which the current Iout flows from the upper voltage monitoring module to the lower voltage monitoring module. The transmission circuit 4 increases the current Iout1 when the data logic level is the first logic level (for example, high level), and increases the current Iout1 when the data logic level is the second logic level (for example, low level). Decrease. For example, the transmission circuit 4 sets the current Iout1 to about 1 mA if the data is data 0 (for example, the logic level is low), and sets the current Iout1 to about 0 mA if the data is data 1 (for example, the logic level is high). And

  In addition, as illustrated in FIG. 17, the transmission circuit 4 includes a transmission data generation unit 40 and an output stage circuit 41. The transmission data generation unit 40 reads data to be transmitted from the register based on an instruction from a control circuit (not shown), and outputs a current Iout0 according to the logic level of the data. The output stage circuit 41 outputs a signal current (for example, Iout1) according to the current Iout0.

  The output stage circuit 41 includes PMOS transistors P21 to P24. The PMOS transistors P41 and P42 constitute a current mirror circuit. The PMOS transistors P43 and P44 constitute a current mirror circuit. Specifically, the current Iout0 is input to the drain of the PMOS transistor P41. The gate and drain of the PMOS transistor P41 are connected to each other. The source of the PMOS transistor P41 is connected to the drain of the PMOS transistor P43. The gate of the PMOS transistor P42 is connected in common with the gate of the PMOS transistor P41. The drain of the PMOS transistor P42 is connected to the external terminal and outputs a current Iout1. The source of the PMOS transistor P42 is connected to the drain of the PMOS transistor P44. The gate and drain of the PMOS transistor P43 are connected to each other. The source of the PMOS transistor P43 is connected to a low potential side power supply line to which the ground voltage GND is supplied. The gate of the PMOS transistor P44 is connected in common with the gate of the PMOS transistor P43. The source of the PMOS transistor P44 is connected to the low potential side power supply wiring.

  In FIG. 17, the receiving circuit 4 includes an NPN transistor Tr2. The NPN transistor Tr2 prevents the output stage circuit 41 from being applied with a high voltage due to noise (for example, a voltage exceeding the high potential side power supply voltage VDDU).

  Subsequently, an operation of the receiving circuit 2 according to the second exemplary embodiment will be described. Since the receiving circuit 1 according to the first embodiment performs communication through the upstream path, the current signal is input in the direction in which the current signal is extracted from the receiving circuit 1. Therefore, in the receiving circuit 1 according to the first embodiment, it is necessary to generate the input voltage VA by changing the current I11 flowing through the first resistor R11 connected to the high-potential-side power supply wiring by the signal current. However, the receiving circuit 3 according to the second embodiment is input in the direction in which the signal current flows into the receiving circuit 3 in order to cope with communication performed in the downstream path. Therefore, in the receiving circuit 3 according to the second exemplary embodiment, it is necessary to generate the input voltage VA by changing the current I31 flowing through the first resistor R31 connected to the low-potential-side power supply wiring according to the signal current.

  For this reason, the receiving circuit 3 according to the second embodiment has the configuration shown in FIG. Then, the receiving circuit 3 varies the current I31 by the current Iin, and varies the current I32 flowing through the second resistor R32 using the current mirror circuit 31. As a result, the input voltage VA and the comparison voltage VB have opposite phase fluctuations.

  In the receiving circuit 3 according to the second embodiment, in order to draw the comparison voltage VB to the input voltage VA, it is necessary to increase or decrease the current I32 by causing the adjustment current Iadj to flow into the second wiring W12. That is, in the reception circuit 3, when the input voltage VA is lower than the common voltage Vcom, the adjustment current Iadj is not output as in the reception circuit 1 according to the first embodiment.

  For this reason, in the receiving circuit 3 according to the second embodiment, when the input voltage VA is lower than the common voltage Vcom, the output of the adjustment current Iadj is stopped and the comparison between the input voltage VA and the comparison voltage VB is performed. To generate a reception signal DOUT. This operation is based on the same operation principle as that of the reception circuit 1 according to the first embodiment shown in FIG.

  In the receiving circuit 3 according to the second embodiment, in a state where the input voltage VA is equal to or higher than the common voltage Vcom, the adjustment current Iadj is output and the comparison voltage VB is returned to the input voltage VA. The received signal DOUT is generated by comparing the two voltages. This operation is based on the same operation principle as the operation of the receiving circuit 1 according to the first embodiment shown in FIGS.

  From the above description, the receiving circuit 3 according to the second embodiment is transmitted via the downstream path by improving the circuit configuration of the receiving circuit 1 according to the first embodiment in response to the inflowing signal current. The transmission signal can be the reception signal DOUT regardless of noise.

  In the receiving circuit 3 according to the second embodiment, it is not necessary to use a capacitor, a differential signal, or a multistage circuit for noise removal. Therefore, also in the receiving circuit 3 according to the second exemplary embodiment, as in the receiving circuit 1 according to the first exemplary embodiment, it is possible to obtain the effects of suppressing the circuit area and reducing the number of components.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments already described, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

1, 3 Receiving circuit 2, 4 Transmitting circuit 10, 30 Input stage circuit 11, 14, 31 Current mirror circuit 12, 32 Adjustment circuit 13, 33 Differential amplifier 15, 34 Comparator 20, 40 Transmission data generating unit 21, 41 Output Stage circuit 211 Output stage circuit R11, R21, R31, R32 Resistance Tr1, Tr2 NPN transistor N11-N15 NMOS transistor N21-N24 NMOS transistor P11, P31-P33 PMOS transistor P41, P42 PMOS transistor D Diode LINE Transmission wiring W11 Wiring W12 Second wiring ND Current input node I11, I12 Current Iin Current Iadj Adjustment current Iout0, Iout1 Current VA Input voltage VB Comparison voltage VDDU High potential side power supply voltage GND Low potential side power supply Pressure UPL upstream wiring network DNL downstream distribution network

Claims (11)

A semiconductor device having a reception circuit that receives a signal current output from a transmission circuit and generates a reception signal,
The receiving circuit is
A first resistor and a second resistor, one end of which is connected to one of the high potential side power supply wiring and the low potential side power supply wiring;
A first terminal connected to the other of the high-potential-side power supply wiring and the low-potential-side power supply wiring, and a control terminal connected in common; the control of the first transistor A first current mirror circuit in which a terminal and a second terminal are connected to each other;
A first wiring connecting the first resistor and the second terminal of the first transistor and having a current input node to which the signal current is input;
A second wiring connecting the second resistor and the second terminal of the second transistor;
An adjustment current that varies in magnitude according to a voltage difference between a first voltage generated in the first wiring and a second voltage generated in the second wiring is generated, and the adjustment current is supplied to the second wiring. Adjustment circuit for wiring,
A semiconductor device comprising: a comparator that inverts the logic level of the received signal based on a magnitude relationship between the first voltage and the second voltage.   When the voltage difference between the first voltage and the second voltage is larger than a steady state, the adjustment circuit applies the adjustment current to the second wiring to provide the voltage difference to the steady state. The semiconductor device according to claim 1, wherein the semiconductor device is pulled back to the voltage difference. The adjustment circuit includes:
A differential amplifier that varies a voltage level of a control signal based on a voltage difference between the first voltage and the second voltage;
The semiconductor device according to claim 1, further comprising: an output transistor that varies a magnitude of the adjustment current based on a voltage level of the control signal.   4. The semiconductor device according to claim 3, wherein the adjustment circuit includes a second current mirror circuit that generates the adjustment current based on a current output from the output transistor.   2. The comparator according to claim 1, wherein the comparator inverts the logic level of the received signal in response to a voltage difference between the first voltage and the second voltage being larger than a predetermined voltage difference. The semiconductor device described. Transmission wiring for transmitting the signal current from the transmission circuit to the first wiring;
The semiconductor device according to claim 1, further comprising a backflow prevention circuit connected between the transmission wiring and the low potential side power supply wiring.   2. The semiconductor device according to claim 1, wherein the receiving circuit receives the signal current output from the transmitting circuit provided in another semiconductor device that operates based on a power supply having a lower power supply voltage range than the semiconductor device.   The semiconductor device according to claim 1, wherein the reception circuit receives the signal current output from the transmission circuit provided in another semiconductor device that operates based on a power supply having a higher power supply voltage range than the semiconductor device. A measurement circuit for measuring the voltage value of each of a plurality of battery cells connected in series;
A register for storing a measurement result by the measurement circuit;
A control circuit that controls operations of the measurement circuit and the transmission circuit, and
The semiconductor device according to claim 1, wherein the control circuit controls the measurement circuit and the transmission circuit based on a control command obtained via the reception circuit.   The control command includes at least a first command for instructing measurement of a voltage value of the plurality of battery cells by the measurement circuit, and a second command for instructing transmission of the measurement result. The semiconductor device described. A plurality of battery monitoring modules each measuring the state of at least one battery cell and daisy chained;
A communication line connecting the plurality of battery monitoring modules;
A cell monitoring unit for obtaining measurement results of the battery cells from the plurality of battery monitoring modules;
Each of the plurality of battery monitoring modules is
A transmission circuit that switches the current value of the signal current output to the battery monitoring module located on one of the upper side and the lower side according to the logic level of the transmission signal;
A reception circuit that generates a reception signal based on a signal current output from a battery monitoring module located on the other of the upper side and the lower side, and
The receiving circuit is
A first resistor and a second resistor, one end of which is connected to one of the high potential side power supply wiring and the low potential side power supply wiring;
A first terminal connected to the other of the high-potential-side power supply wiring and the low-potential-side power supply wiring, and a control terminal connected in common; the control of the first transistor A first current mirror circuit in which a terminal and a second terminal are connected to each other;
A first wiring connecting the first resistor and the second terminal of the first transistor and having a current input node to which the signal current is input;
A second wiring connecting the second resistor and the second terminal of the second transistor;
An adjustment current that varies in magnitude according to a voltage difference between a first voltage generated in the first wiring and a second voltage generated in the second wiring is generated, and the adjustment current is supplied to the second wiring. Adjustment circuit for wiring,
A voltage monitoring system comprising: a comparator that inverts the logic level of the received signal based on a magnitude relationship between the first voltage and the second voltage.