JP2013223279A - Power conversion apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power conversion apparatus which exhibits high cost performance of manufacturing costs and can reduce harmonics.SOLUTION: A neutral point clamp type inverter 10 comprises n stages of inverter units 1U1 to 1Un and n stages of transformers TR1 to TRn which are respectively connected to the n stages of inverter units 1U1 to 1Un and have phases advanced by 60°/n in each stage from the first stage to the n'th stage. Control is exerted in such a way that the voltages of the n stages of inverter units 1U1 to 1Un are delayed in phase by an amount equal to the 60°/n advanced by the n stages of transformers and two three-level voltages of the inverter units 1U1 to 1Un are shifted in phase by 30°/n.

Description

  Embodiments described herein relate generally to a power conversion device that reduces harmonics.

  In general, an inverter device that outputs a large amount of power needs to use a switching element having a high withstand voltage or to secure a withstand voltage by connecting the switching elements in series in order to convert a high voltage. Alternatively, means for increasing the output voltage by using multiple stages of inverters using a transformer is used. At this time, since the high withstand voltage element has a large switching loss, switching is often performed once per one period of the output frequency (one pulse), and control for eliminating specific harmonics is often performed by shifting the phase.

  Moreover, the power converter device which reduces a harmonic lower than 23rd order and 25th order by four three-phase inverters and four transformers is disclosed.

JP 2000-050634 A JP 2001-161073 A

“Power Electronics Circuit”, first edition, Ohmsha, November 30, 2000, p. 143-153

  However, a power conversion device that reduces higher-order harmonics than the 23rd and 25th orders requires at least four transformers. As the number of transformers increases, the manufacturing cost of the power conversion device increases.

  Therefore, an embodiment of the present invention is to provide a power conversion device that has high cost performance in terms of manufacturing cost and can reduce harmonics.

  The power conversion device according to the aspect of the embodiment of the present invention includes a multi-level inverter circuit of 5 levels or more that outputs two voltages of 3 levels or more for three phases, and n (n is 2 or more). ) Stage three-phase inverter circuit and the n-stage three-phase inverter circuit connected to each other, the n-stage transformer advanced by 60 ° / n phase from the first stage to the n-th stage, and the n-stage three-phase circuit First control means for delaying the phase of the voltage of the inverter circuit by 60 ° / n phase advanced by the n-stage transformer respectively connected to the n-stage three-phase inverter circuit; Second control means for controlling the phase difference between the two voltages by 30 ° / n.

The block diagram which shows the structure of the neutral point clamp type inverter which concerns on the 1st Embodiment of this invention. The lineblock diagram showing the composition of the inverter unit concerning a 1st embodiment. The lineblock diagram showing the composition in case the number of stages of the neutral point clamp type inverter concerning a 1st embodiment is two. FIG. 5 is a relationship diagram showing a switching pattern corresponding to the output voltage of the inverter unit according to the first embodiment. The flowchart which shows the switching method which suppresses the neutral point electric potential fluctuation | variation in the output voltage of the inverter unit which concerns on 1st Embodiment. The timing chart which shows the relationship between the switching pattern and secondary side winding voltage in the inverter unit which concerns on 1st Embodiment. FIG. 5 is a waveform diagram showing waveforms of a U-phase primary winding voltage of the first-stage transformer, a U-phase and V-phase primary winding voltages of the first-stage transformer, and a U-phase voltage according to the first embodiment. The block diagram which shows the structure of the neutral point clamp type inverter which concerns on the 2nd Embodiment of this invention. The block diagram which shows the structure of the neutral point clamp type inverter which concerns on the 3rd Embodiment of this invention. The block diagram which shows the structure of the neutral point clamp type inverter which concerns on the 4th Embodiment of this invention. The block diagram which shows the structure of the U-phase 2nd stage | paragraph inverter unit which concerns on 4th Embodiment. The timing chart which shows the relationship between the switching pattern of a switching element and two voltages in the U-phase 2nd stage inverter unit which concerns on 4th Embodiment.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 is a configuration diagram showing a configuration of a neutral point clamp inverter 10 according to a first embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the same part in drawing, the detailed description is abbreviate | omitted, and a different part is mainly described. In the same manner, other embodiments will not be described repeatedly.

  The neutral point clamp type inverter 10 converts the DC voltage Vdc into a three-phase (U-phase, V-phase, and W-phase) AC voltage having an arbitrary frequency, and supplies power to the three-phase AC loads Lu, Lv, and Lw. To do.

  The neutral point clamp inverter 10 includes n × 3 inverter units 1U1, 1V1, 1W1, 1U2, 1V2, 1W2,..., 1Un, 1Vn, 1Wn, n-stage transformers TR1, TR2,. A power supply 2 is provided. Here, n is 2 or more.

  The neutral point clamp inverter 10 includes n-stage inverter units 1U1 to 1Wn. Each stage is composed of three inverter units 1Um, 1Vm, 1Wm (1 ≦ m ≦ n) constituting three phases.

  The DC voltage Vdc is input from the DC power supply 2 to all the inverter units 1U1 to 1Wn. Inverter units 1U1 to 1Wn convert the DC power supplied from DC power supply 2 into AC power and output it to transformers TR1 to TRn. The inverter units 1U1 to 1Wn are 5-level NPC (neutral-point-clamped) full-bridge inverters.

  The n transformers TR1 to TRn are provided corresponding to each stage. The primary windings of the transformers TR1 to TRn at each stage are connected to the three-phase AC loads Lu, Lv, and Lw. The secondary windings of the transformers TR1 to TRn at each stage are connected to the AC side (output side) of the inverter units 1U1 to 1Wn constituting the corresponding stage.

  The secondary windings (inverter unit side) of all transformers TR1 to TRn are all open Y-connected. The primary winding (load side) is wound differently depending on the transformers TR1 to TRn.

  When the phase of the first-stage transformer TR1 is set to 0 °, the second-stage transformer TR2 has two phases (for example, a U-phase) and the primary winding to advance the output voltage phase by 60 ° / n with respect to the first-stage transformer TR1. Make a staggered wire that wraps across the V phase. The third stage transformer TR3 is staggered to advance the output voltage phase by 60 ° / n with respect to the second stage transformer TR2. Accordingly, the output voltage phase of the third-stage transformer TR3 advances by 120 ° / n with respect to the first-stage transformer TR1. Similarly, the n-th stage transformer TRn after the third stage has a staggered connection that advances the output voltage phase by (60 ° / n) × (n−1) with respect to the first-stage transformer TR1. That is, the transformers TR1 to TRn at each stage advance the output voltage phase by 60 ° / n as the number of stages increases.

  FIG. 2 is a configuration diagram showing the configuration of the inverter units 1U1 to 1Wn according to the present embodiment. Here, the configuration of the U-phase m (1 ≦ m ≦ n) stage inverter unit 1Um will be described. All the inverter units 1U1 to 1Wn are similarly configured.

  The U-phase m-th inverter unit 1Um includes two capacitors Cpum and Cnum, eight switching elements Sum1, Sum2, Sum3, Sum4, Sum5, Sum6, Sum7, Sum8, and eight free-wheeling diodes Dum1, Dum2, Dum3, Dum4. Dum5, Dum6, Dum7, Dum8, and four clamp diodes Dum9, Dum10, Dum11, Dum12.

  The eight free-wheeling diodes Dum1 to Dum8 are connected in antiparallel to the eight switching elements Sum1 to Sum8, respectively.

  Two capacitors Cpum and Cnum are connected in series. The connection point between the positive side capacitor Cpum and the negative side capacitor Cnum is a neutral point.

  The inverter unit 1Um is composed of two legs.

  One leg includes four switching elements Sum1 to Sum4, four free-wheeling diodes Dum1 to Dum4, and two clamp diodes Dum9 and Dum10.

  All four switching elements Sum1 to Sum4 are connected in series. Four switching elements Sum1 to Sum4 connected in series are connected in parallel with two capacitors Cpum and Cnum connected in series. A connection point between the two switching elements Sum2 and Sum3 located inside is connected to one end of the U-phase secondary winding of the m-th transformer TRm as a connection point voltage VumA.

  The two clamp diodes Dum9 and Dum10 are connected in series. The positive side of the two clamp diodes Dum9 and Dum10 connected in series is connected to the connection point of the two switching elements Sum1 and Sum2 on the positive side connected in series. The negative electrode side of the two clamp diodes Dum9 and Dum10 connected in series is connected to the connection point of the two switching elements Sum3 and Sum4 on the negative electrode side connected in series. A connection point between the two switching elements Sum3 and Sum4 is connected to a neutral point formed by two capacitors Cpum and Cnum.

  The other leg is composed of four switching elements Sum5 to Sum8, four free-wheeling diodes Dum5 to Dum8, and two clamp diodes Dum11 and Dum12. The configuration of this leg is the same as the configuration of the aforementioned leg. A connection point between the two switching elements Sum6 and Sum7 located inside is connected to the other end of the U-phase secondary winding of the m-th transformer TRm as a connection point voltage VumB.

  The inverter unit 1Um outputs a potential difference VumA−VumB between the connection point voltage VumA and the connection point voltage VumB to the m-th transformer TRm as a U phase. Similarly, the V-phase and W-phase m-th stage inverter units 1Vm and 1Wm output to the m-th stage transformer TRm as V-phase and W-phase, respectively. As a result, a three-phase voltage is output from the three m-th inverter units 1Um, 1Vm, and 1Wm to the m-th transformer TRm.

  With reference to FIG. 3, the control of the neutral point clamp type inverter 10 will be described by taking a case where the number of stages is 2 (n = 2) as an example. The neutral-clamp inverter 10 having two stages is composed of six inverter units 1U1, 1V1, 1W1, 1U2, 1V2, 1W2 and two transformers TR1, TR2.

  Here, the primary winding and secondary winding of the first stage transformer TR1 are Nr times, the primary winding of the second stage transformer TR2 is Nr times, and the secondary winding of the second stage transformer TR2 is √3Nr times. And

  First, a voltage output method using the inverter units 1U1 to 1W2 alone will be described. Here, the U-phase first-stage inverter unit 1U1 will be described as an example, but the same applies to the other inverter units 1U2 to 1W2.

  Since the inverter unit 1U1 has a full bridge configuration, if the DC voltage is Vdc, the inverter unit 1U1 outputs a five-level voltage Vu21 of −Vdc, −Vdc / 2, 0, + Vdc / 2, and + Vdc.

  Next, a control method for driving (switching) the switching elements Su11 to Su18 constituting the inverter unit 1U1 will be described. Switching elements Su11 to Su18 correspond to switching elements Sum1 to Sum8 shown in FIG. Similarly, in the other elements, the reference numeral shown in FIG. 2 replaces “m” with “1”.

  The inverter unit 1U1 outputs a five-level voltage Vu21 when the switching elements Su11 to Su18 are turned on or off.

  FIG. 4 is a relationship diagram showing switching patterns PT1 to PT9 corresponding to the output voltage Vu21 of the inverter unit 1U1.

  There are nine switching patterns PT1 to PT9 representing the on / off states of the switching elements Su11 to Su18 that determine the output level of the output voltage Vu21. In all the switching patterns PT1 to PT9, the four pairs of the switching element Su11 and the switching element Su13, the switching element Su12 and the switching element Su14, the switching element Su15 and the switching element Su17, and the switching element Su16 and the switching element Su18 are complementary. Works. Complementary operation refers to an operation in which when one of the paired switching elements is on, the other switching element is off.

  There are a plurality of switching patterns for outputting voltages of 0, + Vdc / 2 and -Vdc / 2. Therefore, when outputting voltages of 0, + Vdc / 2 and -Vdc / 2, there is a redundancy of the switching pattern. When outputting a 0 level voltage, there are three switching patterns PT4, PT5 and PT6. When outputting a voltage of + Vdc / 2, there are two switching patterns PT2 and PT3. When outputting a voltage of −Vdc / 2, there are two kinds of switching patterns PT7 and PT8.

  The control of the inverter unit 1U1 uses this redundancy to determine the switching patterns PT2 to PT9 so as to suppress the neutral point potential fluctuation of the inverter unit 1U1. The neutral point potential fluctuates when only one of the two legs is connected to the neutral point. Therefore, this is the case when the output voltage Vu21 is -Vdc / 2, + Vdc / 2. The direction in which the neutral point potential varies is determined by the direction of the connected leg and the output current Iout.

  When the output voltage Vu21 is −Vdc or + Vdc, the switching patterns PT1 and PT9 are uniquely determined. Furthermore, since no current flows into the neutral points in the switching patterns PT1, PT9, the neutral point potential does not fluctuate.

  When the output voltage Vu21 is 0, there are three switching patterns PT4 to PT6. However, in the control of the inverter unit 1U1, the switching pattern PT5 that can shift the output voltage Vu21 by turning on / off one set of switching elements is always selected.

  For example, when it is desired to change the output voltage Vu21 from 0 to + Vdc / 2, the switching pattern PT5 can be switched to the switching pattern PT2 by switching only one set of the switching element Su11 and the switching element Su13.

  On the other hand, switching from the switching pattern PT6 to the switching pattern PT2 requires switching of three sets of the switching element Su11 and the switching element Su13, the switching element Su12 and the switching element Su14, and the switching element Su16 and the switching element Su18.

  As described above, the switching pattern PT5 can be switched to the switching pattern PT2, the switching pattern PT3, the switching pattern PT7, and the switching pattern PT8, which may be switched, by turning on / off the pair of switching elements. Therefore, the number of times of switching can be minimized by always selecting the switching pattern PT5.

  FIG. 5 is a flowchart illustrating a switching method for suppressing the neutral point potential fluctuation when the output voltage Vu21 of the inverter unit 1U1 according to the present embodiment is −Vdc / 2 or + Vdc / 2.

  The potential of the positive side capacitor Cpu1 is Vp, the potential of the negative side capacitor Cnu1 is Vn, and the direction in which the output current Iout is directed from the inverter unit 1U1 to the loads Lu, Lv, and Lw is the positive direction. Note that the potentials Vp and Vn of the two capacitors and the output current Iout are measured by sensors provided in the inverter unit 1U1, respectively.

  It is determined whether or not the output voltage Vu21 is set to −Vdc / 2 or + Vdc / 2 (step S010). Unless the output voltage Vu21 is set to −Vdc / 2 or + Vdc / 2, the switching pattern is uniquely determined corresponding to the output voltage Vu21 (step S050).

  When the output voltage Vu21 is set to -Vdc / 2 or + Vdc / 2, the magnitudes of the potential Vp of the positive side capacitor and the potential Vn of the negative side capacitor are compared (YES in step S010, step S020).

  After comparing the magnitude of the potential Vp of the positive capacitor and the potential Vn of the negative capacitor, it is determined whether or not the output current Iout is in the positive direction (step S030 or step S040).

  When the potential Vp of the positive side capacitor is larger and the output current Iout is in the positive direction (YES in step S030), the switching patterns PT2 and PT7 are selected according to step S060. In step S060, when the output voltage Vu21 is set to + Vdc / 2, the switching pattern PT2 is selected, and when the output voltage Vu21 is set to -Vdc / 2, the switching pattern PT7 is selected.

  When the potential Vp of the positive side capacitor is larger and the output current Iout is negative (NO in step S030), switching patterns PT3 and PT8 are selected according to step S070. In step S070, the switching pattern PT3 is selected when the output voltage Vu21 is set to + Vdc / 2, and the switching pattern PT8 is selected when the output voltage Vu21 is set to -Vdc / 2.

  When the potential Vn of the negative electrode side capacitor is larger and the output current Iout is in the positive direction (YES in step S040), the switching patterns PT3 and PT8 are selected according to step S070 described above.

  When the potential Vn of the negative electrode side capacitor is larger and the output current Iout is in the negative direction (NO in step S040), the switching patterns PT2 and PT7 are selected according to step S060 described above.

  For example, consider the case where the potential Vp of the positive side capacitor Cpum is higher than the potential Vn of the negative side capacitor Cnum and the current direction of the output current Iout is positive. At this time, if a current is passed in a direction in which the negative capacitor Cnu1 is charged or a positive capacitor Cpu1 is discharged, the potential Vn rises and neutral point potential fluctuation is suppressed. Therefore, if the output voltage Vu21 is to be −Vdc / 2, the switching pattern PT7 is selected. If the output voltage Vu21 is to be + Vdc / 2, the switching pattern PT2 is selected. Since it flows, the neutral point potential fluctuation is suppressed. In this way, the switching patterns PT2, PT3, PT7, and PT8 are determined according to the magnitude relationship between the potentials of the two capacitors Cpu1 and Cnu1 and the direction of the output current Iout.

  Next, a method of outputting a voltage with reduced low-order harmonics according to the switching patterns PT1 to PT9 that suppress the above-described neutral point potential fluctuation will be described.

  Square wave voltage includes fundamental wave (first harmonic), 3rd order, 5th order, 7th order, 9th order, 11th order, 13th order, 15th order, 17th order, 19th order, 23rd order, 25th order, and Odd order harmonics higher than the 25th order are superimposed.

  The third, ninth, and fifteenth harmonics that are multiple harmonics of 3 are canceled by outputting the line voltage of each phase that is 120 ° out of phase to the loads Lu, Lv, and Lw.

  To completely cancel the 5th, 7th, 17th and 19th harmonics, the output voltages Vu21 to Vw21 of the first stage inverter units 1U1 to 1W1 and the output voltages Vu22 to Vw22 of the second stage inverters 1U2 to 1W2 The phase may be shifted by 30 °, and the 30 ° phase shifted by the windings of the two transformers TR1 and TR2 may be returned.

  Due to the configuration of the primary windings of the first-stage transformer TR1 and the second-stage transformer TR2, the phases of the primary winding voltages Vu12 to Vw12 of the second-stage transformer TR2 are changed to the primary winding voltages Vu11 to Vu11 of the first-stage transformer TR1. Advance 30 ° from the phase of Vw11. Therefore, if the phases of the output voltages Vu22 to Vw22 of the second-stage inverter units 1U2 to 1W2 are delayed by 30 ° with respect to the output voltages Vu21 to Vw21 of the first-stage inverter units 1U1 to 1W1, the above-described harmonics are cancelled.

  Next, a method for reducing the 11th and 13th harmonics will be described using the U-phase first-stage inverter unit 1U1 as an example.

  If two voltages are output with a certain phase shift, one specific harmonic can be eliminated. Therefore, one specific harmonic can be eliminated by shifting the phases of the two three-level voltages.

  On the other hand, the inverter unit 1U1 can output five-level voltages of -Vdc, -Vdc / 2, 0, + Vdc / 2, and + Vdc. This can be considered that a 5-level voltage is output by superimposing the 3-level voltages of −Vdc / 2, 0, and + Vdc / 2 output for each leg.

  On the other hand, if the phases of two three-level voltages are shifted so as to cancel the 12th harmonic (which is not originally superimposed on the output voltage), which is the middle of the 11th and 13th harmonics, the 11th and 13th harmonics Both can be reduced considerably. The phase for canceling the 12th harmonic is 180 ° / 12 = 15 °. Therefore, if the phases of the two three-level voltages are shifted by 15 °, the 11th and 13th harmonics can be reduced to a low level (for example, below the regulation value).

  With reference to FIG. 6, a specific control method of inverter unit 1U1 for reducing the 11th and 13th harmonics will be described. FIG. 6 is a timing chart showing the relationship between the switching patterns PT1 to PT9 and the secondary winding voltage Vu21 in the inverter unit 1U1.

  Here, only the switching patterns PT1 to PT9 of the four switching elements Su11, Su14, Su15, and Su18 are shown, and the other switching elements Su12, Su13, Su16, and Su17 are switched complementarily with the above switching elements. Not shown. The method for determining the switching patterns PT1 to PT9 is as described above with reference to the flowchart of FIG.

  As shown in FIG. 6, the phase at which the switching element Su11 and the switching element Su18 are turned on and off is shifted by 15 °. Similarly, the ON and OFF phases of the switching element Su12 and the switching element Su15 are shifted by 15 °. By switching in this way, the phase of the three-level voltage of the two legs can be shifted by 15 °. The 11th and 13th harmonics included in the generated voltage Vu21 are small.

  The secondary winding voltage Vu22 of the U-phase second-stage inverter unit 1U2 operates in the same manner as the inverter unit 1U1 except that the phase is delayed by 30 ° with respect to the voltage Vu21. By operating in this way, the amplitudes of the 11th and 13th harmonics included in the output voltage Vu22 of the U-phase second-stage inverter unit 1U2 are reduced similarly to the voltage Vu21.

  FIG. 7 shows the waveforms of the U-phase primary winding voltage Vu11 of the first-stage transformer TR1 and the U-phase and V-phase primary winding voltages Vu12, -Vv12 and the U-phase voltage Vu of the second-stage transformer TR2. FIG.

  The number of primary windings and secondary windings of the first-stage transformer TR1 is Nr, and the number of primary windings of the second-stage transformer TR2 is Nr. The number of windings of the next winding is √3Nr. Therefore, the primary side winding voltage Vu11 of the first-stage transformer TR1 has the same value as the secondary side winding voltage Vu21. The second-stage transformer TR2 has a winding configuration in which the phase is 30 ° more advanced than the first-stage transformer TR1 and the same amplitude as the primary-side winding voltage Vu11 appears in the first-stage transformer TR1. Therefore, the primary winding of the second-stage transformer TR2 includes a voltage Vu12 obtained by multiplying the secondary-side winding voltage Vu22 of the U-phase second-stage inverter unit 1U2 by 1 / √3, and a V-phase second-stage inverter unit. A voltage −Vv12 obtained by −1 / √3 of the secondary winding voltage Vu22 of 1V2 appears.

  As shown in FIG. 7, the U-phase voltage Vu has a stepped voltage waveform obtained by synthesizing the three voltages Vu11, Vu12, and -Vv12. The U-phase voltage Vu is a voltage in which the 5th, 7th, 17th, and 19th harmonics are canceled as described above, but the 3rd, 9th, 11th, 13th, 15th, 23rd, The 25th and higher harmonics are included. For the loads Lu, Lv, and Lw, the line voltage of the V-phase voltage Vv and the W-phase voltage Vw that are 120 ° out of phase with respect to the U-phase voltage Vu is supplied. Third, ninth, and fifteenth harmonics are cancelled. Furthermore, the 11th and 13th harmonics are greatly reduced in the output voltages Vu21 to Vw22 of the inverter units 1U1 to 1W2, as described above. For this reason, the voltages Vu, Vv, and Vw applied to the loads Lu, Lv, and Lw do not substantially include lower-order harmonics than the 23rd and 25th orders.

  Here, the case of n = 2 has been described in detail, but the above-described circuit configuration and control method can be generally applied even when n> 2. If the phase is shifted by 60 ° / n by the transformers TR1 to TRn at each stage and then the output voltage between the n stage inverter units is shifted in the opposite direction to the phase shifted by the transformers TR1 to TRn, 6n ± 1st harmonic Harmonics other than waves can be eliminated. Furthermore, if each of the inverter units 1U1 to 1Wn superimposes two three-level voltages shifted by 180 ° / 6n, the amplitude of the 6n ± 1st harmonic can be reduced. As a result, the voltages Vu, Vv, and Vw applied to the loads Lu, Lv, and Lw do not substantially include harmonics lower than 12n ± 1st order.

  According to the present embodiment, the neutral point clamp inverter 10 can efficiently reduce harmonics superimposed on the output voltage with a small number of transformers TR1 to TRn. Thereby, the neutral point clamp type inverter 10 has high manufacturing cost performance and can be downsized.

(Second Embodiment)
FIG. 8 is a configuration diagram showing the configuration of a neutral point clamp type inverter 10A according to the second embodiment of the present invention.

  First, the case where the number of stages n is 2 will be described.

  A neutral point clamp inverter 10A is obtained by replacing the transformers TR1 and TR2 with the transformers TR1A and TR2A, respectively, in the neutral point clamp inverter 10 according to the first embodiment shown in FIG. Other points are the same as in the first embodiment.

  The first-stage transformer TR1A is a first-stage transformer TR1 according to the first embodiment, in which the primary winding is staggered with a 15 ° phase delay. Other points are the same as those of the first-stage transformer TR1 according to the first embodiment.

  The second-stage transformer TR2A is a second-stage transformer TR2 according to the first embodiment, in which the primary winding is staggered with a 15 ° phase advance. Other points are the same as those of the second-stage transformer TR2 according to the first embodiment.

  Next, the configuration of the primary windings of the two transformers TR1A and TR2A will be described in detail.

  The primary winding of the first-stage transformer TR1A is configured as follows. The U-phase primary winding is wound from the negative direction of the W phase in the positive direction and then wound from the positive direction to the negative direction over the U phase. The number of turns of the W phase and the U phase is Nr × sin 15 ° and Nr × sin 45 °, respectively. The V-phase primary winding is wound in the positive direction from the negative direction of the U phase, and is wound in the negative direction from the positive direction over the V phase. The number of windings of the U phase and the V phase is set to Nr × sin 15 ° and Nr × sin 45 °, respectively. The W-phase primary winding is wound in the positive direction from the negative direction of the V phase, and is wound in the negative direction from the positive direction over the W phase. The turns ratio of the V phase and the W phase is Nr × sin 15 ° times and Nr × sin 45 ° times, respectively.

  The primary winding of the second-stage transformer TR2A is configured as follows. The U-phase primary winding is wound from the negative direction of the V-phase in the positive direction, and then wound from the positive direction to the negative direction over the U-phase. The number of turns of the V phase and the U phase is Nr × sin 15 ° and Nr × sin 45 °, respectively. The V-phase primary winding is wound in the positive direction from the negative direction of the W phase, and is wound in the negative direction from the positive direction over the V phase. The number of turns of the W phase and the V phase is Nr × sin 15 ° and Nr × sin 45 °. The W-phase primary winding is wound in the positive direction from the negative direction of the U-phase, and is wound in the negative direction from the positive direction over the W-phase. The number of windings of the U phase and the W phase is Nr × sin 15 ° and Nr × sin 45 °, respectively.

  By configuring the two transformers TR1A and TR2A in this way, the phase difference between the two transformers TR1A and TR2A becomes 30 °. The second stage transformer TR2A is the same as the first embodiment in that the phase of the second stage transformer TR2A is advanced by 30 ° with respect to the phase of the first stage transformer TR1A.

  The driving method of the switching element of each inverter unit 1U1 to 1W2 is the same as that of the first embodiment. By driving the switching elements of the inverter units 1U1 to 1W2 as in the first embodiment, the voltages Vu, Vv, and Vw applied to the loads Lu, Lv, and Lw have higher harmonics lower than the 23rd and 25th orders. Waves are not actually included.

  Also in the case where the number of stages n is 3 or more, the above-described configuration and control method can be generally applied as in the first embodiment.

  According to the present embodiment, in addition to the operational effects of the first embodiment, the following operational effects can be obtained.

  In the neutral point clamp type inverter 10A, the configuration of the primary winding of the first stage transformer TR1A and the second stage transformer TR2A is the same. Thus, the manufacturing cost of neutral point clamp type inverter 10A can be reduced by making 1st stage transformer TR1A and 2nd stage transformer TR2A into the same composition. For example, when a three-phase tripod iron core is used for the transformers TR1A and TR2A, the phase difference between the transformers TR1A and TR2A is set to 30 ° if the first and second U-phase and W-phase connections are reversed. Can do.

(Third embodiment)
FIG. 9 is a configuration diagram showing a configuration of a neutral point clamp inverter 10B according to the third embodiment of the present invention.

  First, the case where the number of stages n is 2 will be described.

  The neutral point clamp type inverter 10B is obtained by replacing the second stage transformer TR2 with the second stage transformer TR2B in the neutral point clamp type inverter 10 according to the first embodiment shown in FIG. Other points are the same as in the first embodiment.

  The second-stage transformer TR2B is the second-stage transformer TR2 according to the first embodiment, in which the primary winding is Δ-connected and the number of windings is √3Nr. Other points are the same as those of the second-stage transformer TR2 according to the first embodiment.

  Here, since the secondary winding voltage of the second stage transformer TR2B includes a multiple harmonic of 3, the amplitude of the multiple harmonic of 3 divided by the circulating current of the impedance of the second stage transformer TR2 is Δ. It flows in the connection. Accordingly, the switching elements of the second-stage inverter units 1U2, 1V2, and 1W2 are assumed to have a current rating that takes into consideration that a current in which a circulating current is superimposed on the fundamental wave current flows.

  The driving method of the switching element of each inverter unit 1U1 to 1W2 is the same as that of the first embodiment.

  The U-phase and V-phase line voltage Vuv includes the U-phase and V-phase primary winding voltages Vu11 and Vv11 of the first-stage transformer TR1 and the V-phase primary winding voltage Vv12B of the second-stage transformer TR2B, respectively. It is expressed as line voltage Vuv = Vu11−Vv11−Vv12B.

  A voltage Vu11-Vv11 obtained by subtracting the V-phase primary winding voltage Vv11 from the U-phase primary winding voltage Vu11 of the first-stage transformer TR1 is 30 ° phase with respect to the U-phase primary winding voltage Vu11 of the first-stage transformer TR1. Advances.

  A voltage −Vv12B obtained by inverting the sign of the V-phase primary winding voltage Vv12B of the second-stage transformer TR2B is −120 ° (phase difference between UVs) with respect to the U-phase primary winding voltage Vu11 of the first-stage transformer TR1. ) + 180 ° (positive / negative reversal) −30 ° (phase delayed by control of V-phase second stage inverter unit 1V2) = 30 ° phase advances. Therefore, the fundamental waves of the voltages Vu11-Vv11 and -Vv12B are in phase.

  Here, the control of the first-stage and second-stage inverter units 1U1 to 1W2 with respect to the 30 ° phase difference between the U-phase and V-phase line voltages of the first-stage transformer TR1 and the phase voltage of the second-stage transformer TR2B. Thus, since the phase of the output voltage between the first stage and the second stage is returned, the harmonics of 6k ± 1 (k = 1 or more integer) are canceled as in the first embodiment.

  Therefore, as in the first embodiment, the voltages applied to the loads Lu, Lv, and Lw substantially do not include lower-order harmonics than the 23rd and 25th orders.

  Also in the case where the number of stages n is 3 or more, the above-described configuration and control method can be generally applied as in the first embodiment.

  According to the present embodiment, in addition to the operational effects of the first embodiment, the following operational effects can be obtained.

  The neutral point clamp inverter 10B does not use a staggered connection transformer. The staggered wiring transformer has a complicated winding configuration, which increases the manufacturing cost. Therefore, the manufacturing cost can be reduced by configuring the neutral point clamp type inverter 10B without using the staggered connection transformer.

(Fourth embodiment)
FIG. 10 is a configuration diagram showing a configuration of a neutral point clamp type inverter 10C according to the fourth embodiment of the present invention.

  First, the case where the number of stages n is 2 will be described.

  A neutral point clamp inverter 10C is obtained by replacing the second stage transformer TR2 with two second stage transformers TR2Ca and TR2Cb in the neutral point clamp inverter 10 according to the first embodiment shown in FIG. . Other points are the same as in the first embodiment.

  In the second-stage transformer TR2Ca, the primary winding is an open Y connection and the secondary winding is a Δ connection. In the second stage transformer TR2Cb, the primary winding is Y-connected and the secondary winding is Δ-connected.

The first-stage transformer TR1 has Nr turns for each of the primary winding and the secondary winding. The two second-stage transformers TR2Ca and TR2Cb have Nr / √3 turns of the primary winding,
The number of secondary windings is Nr.

  The method for driving the switching elements of the first-stage inverter units 1U1, 1V1, and 1W1 is the same as that in the first embodiment. Although it is the same as that of the first embodiment in that the output voltage of the second stage inverter units 1U2, 1V2, and 1W2 is delayed by 30 ° from the output voltage of the first stage inverter unit, the switching element driving method is different.

  Next, a method for driving the switching elements Su21 to Su24 of the U-phase second-stage inverter unit 1U2 will be described with reference to FIGS.

  FIG. 11 is a configuration diagram showing a configuration of a U-phase second-stage inverter unit 1U2 according to the present embodiment. The configuration of inverter unit 1U2 shown in FIG. 11 is the same as the configuration of inverter unit 1Um shown in FIG.

  The output potential difference between the neutral point potential and the leg potential composed of the switching elements Su21 to Su24 is Vu22A, and the output potential difference between the neutral point potential and the leg potential composed of the switching elements Su25 to Su28 is Vu22B. .

  FIG. 12 is a timing chart showing the relationship between the switching patterns of the four switching elements Su21, Su24, Su25, and Su28 and the two voltages Vu22A and Vu22B. The other switching elements Su22, Su23, Su26, Su27 are not shown in the figure because they are switched complementarily to the switching elements Su21, Su24, Su25, Su28.

  The leg composed of the switching elements Su21 to Su24 outputs a three-level voltage Vu22A. The leg composed of the switching elements Su25 to Su28 outputs a three-level voltage Vu22B whose phase is delayed by 15 ° with respect to the three-level voltage Vu22A.

  Similarly, the V-phase and W-phase second-stage inverter units 1V2 and 1W2 output two three-level voltages whose phases are shifted by 15 ° between the two constituent legs.

  Since the secondary winding of the second-stage transformer TR2Ca is Δ-connected, the U-phase primary winding voltage Vu12a of the second-stage transformer TR2Ca is connected to the output voltage Vu22A and the V-phase of the U-phase second-stage inverter unit 1U2. A voltage in phase with the potential difference Vuv22A from the output voltage Vv22A of the second-stage inverter unit 1V2 appears. Similarly, the U-phase primary winding voltage Vu12b of the transformer TR2Cb has the same phase as the potential difference Vuv22B between the output voltage Vu22B of the U-phase second-stage inverter unit 1U2 and the output voltage Vv22B of the V-phase second-stage inverter unit 1V2. Appears.

  Therefore, the primary winding combined voltage of the U-phase of the two second-stage transformers TR2Ca and TR2Cb is Vu12a + Vu12b. The phase difference between the voltage Vu12a and the voltage Vu12b is 15 ° under the control of the second stage inverter units 1U2 and 1V2 shown in FIG. Therefore, the U-phase primary winding combined voltage Vu12a + Vu12b of the two second-stage transformers TR2Ca and TR2Cb is a voltage in which the 11th and 13th harmonics are reduced.

  The phase of the primary winding combined voltage Vu12a + Vu12b of the two second-stage transformers TR2Ca and TR2Cb is a line voltage between the U phase and the V phase, and therefore is advanced by 30 ° with respect to the U phase voltage. On the other hand, the phase of the output voltage Vv22 of the U-phase second-stage inverter unit 1U2 is delayed by 30 ° with respect to the output voltage Vu21 of the U-phase first-stage inverter unit 1U1. Therefore, the phase of the primary winding combined voltage Vu12a + Vu12b of the two second-stage transformers TR2Ca and TR2Cb is in phase with the primary winding voltage Vu11 of the first-stage transformer TR1. As a result, similar to the first embodiment, the harmonics of 6k ± 1 (k = 1 or more) are canceled.

  Therefore, as in the first embodiment, the voltages applied to the loads Lu, Lv, and Lw substantially do not include lower-order harmonics than the 23rd and 25th orders.

  Also in the case where the number of stages n is 3 or more, the above-described configuration and control method can be generally applied as in the first embodiment.

  According to the present embodiment, in addition to the operational effects of the first embodiment, the following operational effects can be obtained.

  The neutral point clamp inverter 10C does not use a staggered connection transformer. The staggered wiring transformer has a complicated winding configuration, which increases the manufacturing cost. Therefore, the manufacturing cost can be reduced by configuring the neutral point clamp type inverter 10B without using the staggered connection transformer.

  Further, since the line voltage is applied to the secondary windings of the two second-stage transformers TR2Ca and TR2Cb, the multiple harmonic of 3 is canceled. Therefore, a multiple harmonic of 3 does not flow through the secondary windings of the two second-stage transformers TR2Ca and TR2Cb. Therefore, the current rating of the switching elements of the second-stage inverter units 1U2, 1V2, and 1W2 can be reduced as compared with the case where multiple harmonics of 3 flow. Thereby, the manufacturing cost of the second stage inverter units 1U2, 1V2, 1W2 can be reduced.

  In addition, in each embodiment, although the control part which controls the neutral point clamp type | mold inverters 10-10C is not illustrated, you may provide anywhere. For example, the control unit may be provided in each of the inverters 1U1 to 1Wn, may be provided as a control device independent from these inverters, or may be provided in both of them. Various controls described in each embodiment are mainly performed by this control unit. The control unit is realized by a computer including an arithmetic processing unit and a storage unit.

  In each embodiment, the inverter units 1U1 to 1Wn are 5-level inverters. However, any number of multi-level inverters may be used as long as they are 5 levels or more.

  In addition, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1U1-1Wn ... Inverter unit, 2 ... DC power supply, 10 ... Neutral point clamp type inverter, TR1-TRn ... Transformer, Lu, Lv, Lw ... Three-phase alternating current load.

Claims (10)

A three-phase inverter circuit having n (n is 2 or more) stages including three phases of multi-level inverter circuits of 5 levels or more that output two voltages of three levels or more;
An n-stage transformer connected to each of the n-stage three-phase inverter circuits and advanced by 60 ° / n phase from the first stage to the n-th stage;
First control means for delaying the phase of the voltage of the n-stage three-phase inverter circuit by 60 ° / n phase advanced by the n-stage transformer respectively connected to the n-stage three-phase inverter circuit;
And a second control unit configured to control a phase shift of 30 ° / n between the two voltages of the multilevel inverter circuit. 2. The load-side winding of one of the n-stage transformers is Y-connected, and the load-side winding of the remaining n−1-stage transformer is staggered. The power converter described. The power converter according to claim 1, wherein the n-stage transformer has a load-side winding in a staggered connection. 4. The power converter according to claim 3, wherein the n-stage transformer has the same configuration of a load-side winding. 5. 2. The load-side winding of the first-stage transformer among the n-stage transformers is an open Y-connection, and the load-side winding of the first-stage transformer is a Δ-connection. Power conversion device. Among the n-stage transformers, the winding on the three-phase inverter circuit side of the one-stage transformer is an open Y-connection, and the one-stage transformer is composed of two transformers, and the three-phase of the two transformers The power converter according to claim 1, wherein windings on the inverter circuit side are connected by Δ connection. The multi-level inverter circuit is composed of a plurality of switching elements,
3. A third control unit that controls to select a switching pattern of the plurality of switching elements so as to suppress a neutral point potential fluctuation of the multilevel inverter circuit. Item 7. The power conversion device according to any one of Items 6 above. 8. The multi-level inverter circuit includes a plurality of switching elements, and outputs a zero-level voltage output in a switching pattern that minimizes the number of switching times of the plurality of switching elements. The power converter device according to any one of the above. Three levels of multi-level inverter circuits of 5 levels or more that are connected to n stages of transformers advanced by 60 ° / n phases from the 1st stage to the n stage and output two voltages of 3 levels or more are included. A control device that controls a power conversion device including an n (n is 2 or more) three-phase inverter circuit that is one stage,
First control means for delaying the phase of the voltage of the n-stage three-phase inverter circuit by 60 ° / n phase advanced by the n-stage transformer respectively connected to the n-stage three-phase inverter circuit;
And a second control means for controlling the phase difference between the two voltages of the multilevel inverter circuit by 30 ° / n. Three levels of multi-level inverter circuits of 5 levels or more that are connected to n stages of transformers advanced by 60 ° / n phases from the 1st stage to the n stage and output two voltages of 3 levels or more are included. A control method for controlling a power conversion device including a three-phase inverter circuit having n stages (n is 2 or more), which is one stage,
The phase of the voltage of the n-stage three-phase inverter circuit is delayed by 60 ° / n phase advanced by the n-stage transformer connected to the n-stage three-phase inverter circuit, respectively.
A method for controlling a power converter, comprising: shifting the phase between the two voltages of the multilevel inverter circuit by 30 ° / n.

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