JP2012094934A - Pulse width modulation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pulse width modulation device that allows repeated or dynamic adjustment to level balance between the precision of pulse width setting and the frequency of a modulated signal.SOLUTION: The pulse width modulation device includes: a counter 11 for counting pulses of a clock signal; a first digital value setting section 17 for setting a first digital value D1 determinative of the frequency of a modulated signal; a second digital value setting section for setting a second digital value D2 determinative of the pulse width of the modulated signal; and a comparison circuit 13 for comparing the count value of the counter 11 with the second digital value D2 in terms of magnitude and outputting a binary signal depending on the magnitude relationship. If the counter 11 is an up counter, when the clock signal is input after the count value reaches a maximum value determined on the basis of the first digital value D1, the count value is changed to an initial value smaller than the maximum value to start a recount.

Description

  The present invention relates to a pulse width modulation device.

  The output signal of the pulse width modulation device is used for applications such as LED driver ON / OFF control and voltage regulator output voltage control.

  For example, if the LED is turned on when the input signal to the LED driver is “H” and the LED is turned off when it is “L”, the appearance of the LED is changed by changing the pulse width to change the “H” period. The illuminance above is adjusted.

  Further, the output signal from the pulse width modulation device is converted into a direct current through a low-pass filter and input to the reference voltage of the voltage regulator, whereby the output voltage of the regulator is adjusted. This output voltage is used, for example, as a power supply voltage for electronic equipment.

  It has been conventionally known that such a pulse width modulation device is constituted by a combination of a counter and a comparator (see, for example, Patent Documents 1 and 2).

JP-A-5-227033 JP 2010-124454 A

  In the pulse width modulation device constituted by the counter and the comparator, when the pulse width setting accuracy is improved, the frequency of the generated modulation signal shifts to a lower side. On the other hand, in order to maintain the frequency of the generated signal at a sufficiently high level, it is necessary to take measures such as increasing the accuracy of setting the pulse width or increasing the frequency of the basic clock.

  However, in order to increase the frequency of the basic clock, a circuit such as a PLL is required separately, which is not preferable because it leads to an increase in manufacturing cost and an increase in device scale. That is, when the frequency of the basic clock is not increased, increasing the pulse width setting accuracy and increasing the frequency of the modulation signal are mutually contradictory events.

  This point will be examined from the mode of use of the modulation signal. When a modulation signal is used for the above-described LED light control or power supply voltage setting, it is obvious that the higher the pulse width setting accuracy, the better. On the other hand, regarding the frequency, in the former example (LED dimming), if the frequency is extremely low, blinking of the LED is visually recognized as flickering. In the latter example (power supply voltage setting), if the frequency is low, the low-pass filter for converting to DC becomes large. Therefore, it can be seen that in any case, a higher frequency is desirable.

  Therefore, considering the use application of the modulation signal, it is required to ensure a high value for both the accuracy of setting the pulse width and the frequency of the modulation signal. However, as described above, these are mutually contradictory as mounting restrictions. For this reason, in most cases, the accuracy of setting the pulse width and the frequency of the pulse width modulation signal are determined in consideration of the balance between the two.

  However, it is difficult to adjust the balance between accuracy and frequency once determined again or dynamically. Conventionally, although there is no basic clock processing, there is an example in which an optimum clock is selected from several basic clocks to try to achieve both accuracy and frequency (see Patent Document 1).

  It is an object of the present invention to provide a pulse width modulation device that can adjust the balance between the accuracy of pulse width setting and the frequency level of a modulation signal again or dynamically.

The present invention is a pulse width modulation device that forms and outputs a modulation signal in which the pulse width and frequency of an input clock signal are changed,
A counter for counting the number of pulses of the clock signal;
A first digital value setting unit for setting a first digital value for determining the frequency of the modulation signal;
A second digital value setting unit for setting a second digital value for determining the pulse width of the modulation signal;
A comparison circuit that compares the count value of the counter with the second digital value and outputs a binary signal corresponding to the magnitude relationship;
When the counter is an up counter, the count value is smaller than the maximum value when the clock signal is input after the count value reaches the maximum value determined based on the first digital value. Change to the initial value and count again,
When the counter is a down counter, when the clock signal is input after the count value reaches the minimum value determined based on the first digital value, the count value is larger than the minimum value. It is a configuration that changes to the initial value and counts again,
The modulation signal is characterized in that the binary signal itself output from the comparison circuit or a signal obtained by performing signal processing on the binary signal.

  When the counter provided in this apparatus is an up counter, when counting the number of pulses of the input clock signal, the counter is incremented by 1 from the initial value and reaches the maximum value determined based on the first digital value. Then, it returns to the initial value again, and the above operation is repeated thereafter. In the case of a down counter, the counter is counted down by one from the initial value, and when it reaches the minimum value determined based on the first digital value, it returns to the initial value again, and the above operation is repeated thereafter. .

  Here, the comparison circuit compares the second digital value with the count value of the counter and outputs a binary signal corresponding to the magnitude relationship.

  When the counter is an up counter, if the second digital value is set to a value between the initial value and the maximum value of the counter, the count value of the counter exceeds or is equal to the second digital value. At that time, the level of the output signal of the comparison circuit is inverted. The comparison circuit then maintains the level of the output signal, but after the count value of the counter reaches the maximum value determined on the basis of the first digital value, when the clock signal is further input to return to the initial value again. Since the magnitude relationship between the count value and the second digital value is inverted, the level of the output signal of the comparison circuit is inverted again.

  That is, the frequency of the output signal of the comparison circuit can be adjusted by changing the first digital value, and the pulse width of the output signal of the comparison circuit can be adjusted by changing the second digital value. .

  Therefore, according to the configuration of the present invention, it is possible to easily and dynamically adjust the frequency of the modulation signal and the accuracy of the pulse width setting by appropriately adjusting the first digital value and the second digital value.

In addition to the above configuration, the present invention includes a first register for temporarily holding the first digital value,
The counter is configured to determine the maximum value or the minimum value based on the first digital value held in the first register;
Another feature is that, when the count value of the counter reaches a specific value, the first register reads the first digital value from the first digital value setting unit and updates the hold value. To do.

  According to this configuration, regardless of the timing at which the first digital value is changed in the first digital value setting unit, the maximum value of the counter (in the case of an up counter) or the minimum value (of the down counter) is determined at a predetermined timing. If). For this reason, for example, in the up counter, it is possible to avoid a situation in which the maximum value is set to a value smaller than the count value at the time as a result of the first digital value being changed at a certain time.

In addition to the above configuration, the present invention includes a second register for temporarily holding the second digital value,
The comparison circuit is configured to compare the second digital value held in the second register with the count value of the counter;
Another feature is that, when the count value of the counter reaches a specific value, the second register reads the second digital value from the second digital value setting unit and updates the hold value. To do.

  According to this configuration, regardless of the timing at which the second digital value setting unit changes the second digital value, the setting as the comparison reference value of the comparison circuit is performed at a predetermined timing. For this reason, for example, in the up counter, as a result of the second digital value being changed at a certain point in time, the output is already inverted in the comparison circuit. It is possible to avoid a situation in which the output is inverted again by this time and an output signal having a short pulse width is generated.

  In addition to the above configuration, the present invention is characterized in that the specific value is the initial value.

  In addition to the above configuration, the present invention further includes a DFF (D-flip-flop) for shaping the binary signal output from the comparison circuit and synchronizing it with a clock signal. And

  According to the configuration of the present invention, a pulse width modulation device capable of easily and dynamically adjusting the frequency of a modulation signal and the accuracy of pulse width setting is realized.

1 is a conceptual block diagram of a pulse width modulation device according to a first embodiment. An example of a timing diagram of each signal in the pulse width modulation device of the first embodiment Another example of timing chart of each signal in the pulse width modulation device of the first embodiment Conceptual block diagram of a pulse width modulation apparatus according to the second embodiment An example of a timing diagram of each signal in the pulse width modulation device of the second embodiment An example of a timing diagram of each signal of a pulse width modulation device configured as a comparative example of the second embodiment An example of a timing diagram of each signal of a pulse width modulation device configured as a comparative example of the second embodiment

[First Embodiment]
A first embodiment of the pulse width modulation device of the present invention will be described. FIG. 1 is a block diagram schematically showing the configuration of the present apparatus.

  As shown in FIG. 1, the pulse width modulation device 1 modulates the pulse width of a clock signal input from a clock signal input terminal 3 (hereinafter referred to as “input terminal 3” as appropriate), and outputs a modulated signal output terminal 5 ( Hereinafter, a modulation signal is output from “output terminal 5” as appropriate. The apparatus 1 includes an N-ary counter 11, a comparison circuit 13, a DFF (D-flip flop) 15, a first digital value setting unit 17, and a second digital value setting unit 19.

  The N-ary counter 11 counts (counts) the input clock signal. In this embodiment, the N-ary counter 11 is composed of an up counter, and increases the count value by 1 when the clock signal is input once. The count value is sequentially incremented by 1 from 0 to (N-1). When the clock signal is input after counting (N-1), the count value is returned to 0 again. This is repeated below. Note that the name “N-ary counter” is a name given because this configuration is equivalent to expressing the count value in N-ary notation, and is not composed of a special counter. In the case of an up-counter, it may be configured to repeatedly count at a value between an initial value (here, 0) and a maximum value (here, N-1).

  The first digital value setting unit 17 determines the maximum count value (N−1) counted by the N-ary counter 11. Hereinafter, the numerical value set by the first digital value setting unit 17 is referred to as “first digital value D1”.

  In the present embodiment, the first digital value setting unit sets the N value as the first digital value D1. That is, when D1 = 64 is set, the N-ary counter 11 repeats counting from 0 to 63 (= 64-1). Here, the initial value of the N-ary counter 11 is set to zero.

  The comparison circuit 13 compares the count value of the N-ary counter 11 with the value set by the second digital value setting unit 19. Assuming that the count value is Vcount and the setting value (second digital value) in the second digital value setting unit 19 is D2, the comparison circuit 13 outputs “1” when Vcount <D2, and otherwise. In this configuration, “0” is output.

  The DFF 15 is configured to receive the output signal from the comparison circuit 13 and the clock signal, and has an effect of shaping the output waveform of the comparison circuit 13 and synchronizing it with the clock signal. Although the pulse width modulation device 1 of the present embodiment is configured to include the DFF 15, it is not an indispensable element for realizing the functions of the present invention.

  FIG. 2 is an example of a timing diagram of each signal in the pulse width modulation apparatus of the first embodiment. Here, as an example, it is assumed that D1 = 64 is set in the first digital value setting unit 17 and D2 = 12 is set in the second digital value setting unit 19.

  When the count value Vcount = 0, the comparison circuit 13 outputs “1” to the DFF 15. The DFF 15 outputs this output signal to the output terminal 5 at the first rising timing of the clock signal input thereafter.

  The N-ary counter 11 increases the count value Vcount every time a clock signal is input. The comparison circuit 13 continues to output “1” over a period in which Vcount is smaller than the second digital value D2 (= 12), that is, a period in which Vcount is 11 or less. While “1” is input from the comparison circuit 13, the DFF 15 outputs “1” to the output terminal 5 at the first rising timing of the clock signal input thereafter.

  When the N-ary counter 11 counts Vcount = 12, the comparison circuit 13 changes the output value from “1” to “0”. Actually, the timing at which the output signal of the comparison circuit 13 changes from “1” to “0” depends on the arithmetic processing capability of the N-ary counter 11 and the comparison circuit 13, and therefore is constant in FIG. It is shown with a width. When “0” is input from the comparison circuit 13, the DFF 15 outputs “0” to the output terminal 5 at the first rising timing of the clock signal input thereafter.

  Thereafter, the N-ary counter 11 increases the count value Vcount each time a clock signal is input. Until Vcount = 63, since the value of Vcount is increasing, the comparison circuit 13 continues to output “0” and the DFF 15 also outputs “0”.

  When the clock signal is input in a state where the count value Vcount = 63, the N-ary counter 11 returns Vcount to 0 as described above. When Vcount = 0, the comparison circuit 13 detects that Vcount has become smaller than D2, and changes the output signal from “0” to “1”. For the same reason as when changing from “1” to “0”, the timing at which the output signal of the comparison circuit 13 changes from “0” to “1” is given a certain width in FIG. . When “1” is input from the comparison circuit 13, the DFF 15 outputs “1” to the output terminal 5 at the first rising timing of the clock signal input thereafter. Thereafter, the same operation is repeated.

  At this time, the modulation signal obtained from the output terminal 3 indicates “1” (H level) over a time corresponding to the number of 12 clocks and “0” (L level) over a time corresponding to the number of 52 clocks. Therefore, according to the above setting, a modulation signal having H: L = 12: 52 and a duty ratio of 12/64 is generated at a frequency 1/64 of the clock signal input from the input terminal 3.

  FIG. 3 is another example of a timing diagram of each signal in the pulse width modulation apparatus of the first embodiment. Here, it is assumed that D1 = 16 and D2 = 10.

  In this case, as in the case of FIG. 2, when the count value Vcount = 0, the comparison circuit 13 outputs “1” to the DFF 15, and the DFF 15 The output signal “1” is output to the output terminal 5.

  The N-ary counter 11 increases the count value Vcount every time a clock signal is input. The comparison circuit 13 continues to output “1” until the N-ary counter 11 reaches the count value Vcount = 9, and the DFF 15 also continues to output “1” from the comparison circuit 13 thereafter. “1” is output to the output terminal 5 at the first rising timing of the input clock signal.

  When the N-ary counter 11 counts Vcount = 10, the comparison circuit 13 outputs “0”. When “0” is input from the comparison circuit 13, the DFF 15 outputs “0” to the output terminal 5 at the first rising timing of the clock signal input thereafter.

  Thereafter, until Vcount = 15, since the value of Vcount is increasing, the comparison circuit 13 continues to output “0” and the DFF 15 also outputs “0”. When the clock signal is input in a state where the count value Vcount = 15, the N-ary counter 11 returns Vcount to 0, and the comparison circuit 13 detects that Vcount is smaller than D2 and outputs an output signal. Is changed to “1”. When “1” is input from the comparison circuit 13, the DFF 15 outputs “1” to the output terminal 5 at the first rising timing of the clock signal input thereafter. Thereafter, the same operation is repeated.

  In the case of FIG. 3, the modulation signal obtained from the output terminal 3 shows “1” (H level) over a time corresponding to 10 clocks and “0” (L level) over a time equivalent to 6 clocks. . Therefore, according to the above setting, a modulation signal having H: L = 10: 6 and a duty ratio of 10/16 is generated by the frequency of 1/16 of the clock signal input from the input terminal 3.

  Based on the above, according to the pulse width modulation device 1 of the present embodiment, the frequency of the modulation signal is set to 1 / D1 of the clock signal by the first digital value D1 and the second digital value D2, and the H level and the L level. It can be seen that the pulse width ratio can be adjusted to D2: (D1-D2) and the duty ratio can be adjusted to D2 / D1. If D2 = 0, a signal of “0” output is always obtained as a modulation signal. If D2 = D1, a signal of “1” output is always obtained as a modulation signal.

  According to the example of FIG. 2, if the first digital value D1 = 64 is set by the first digital value setting unit 17, the frequency of the modulation signal is reduced to 1/64, but the resolution (pulse width setting accuracy) is As high as 64. Further, according to the example of FIG. 3, if the first digital value D1 = 16 is set by the first digital value setting unit 17, the frequency of the modulation signal becomes 1/16 higher than in the case of FIG. The resolution is as low as 16.

  In other words, if priority is given to increasing the frequency of the modulation signal, the first digital value setting unit 17 may set the first digital value D1 to a small value, and the resolution (pulse width setting accuracy) should be increased. If priority is to be given, the first digital value D1 may be set to a large value. As described above, even if the first digital value D1 is changed, it is possible to generate a modulation signal having a desired duty ratio by adjusting the second digital value D2 by the second digital value setting unit 19. is there.

[Second Embodiment]
A second embodiment of the pulse width modulation apparatus of the present invention will be described. FIG. 4 is a block diagram schematically showing the configuration of the present apparatus.

  The pulse width modulation device 1A of this embodiment shown in FIG. 4 is different from the pulse width modulation device 1 of the first embodiment in that it further includes a first register 21 and a second register 23. Other components are the same as those in the first embodiment.

  The first register 21 temporarily holds the first digital value D1 set by the first digital value setting unit 17. When the register update request signal Srld is given from the N-ary counter 11, the first register 21 reads the first digital value D1 to the first digital value setting unit 17 and updates the held data.

  The second register 23 temporarily holds the second digital value D2 set by the second digital value setting unit 19. When the register update request signal Srld is given from the N-ary counter 11, the second register 23 reads the second digital value D2 to the second digital value setting unit 19 and updates the held data.

  The N-ary counter 11 is the same as in the first embodiment in that the maximum value (N-1) of the count value to be counted is determined based on the first digital value D1. However, unlike the first embodiment, the maximum value is determined based on the first digital value D1 held in the first register 21. When the count value reaches the maximum value (N−1), the N-ary counter outputs a register update request signal Srld to the first register 21 and the second register 23.

  Further, the comparison circuit 13 is similar to the first embodiment in that the count value Vcount of the N-ary counter 11 is compared with the second digital value D2. However, unlike the first embodiment, the second digital value D2 held in the second register 23 and the count value Vcount of the N-ary counter 11 are compared.

  FIG. 5 is an example of a timing diagram of each signal in the pulse width modulation apparatus of this embodiment. Here, with respect to the values of D1 and D2, a timing diagram is shown in a case where D1 = 64 and D2 = 12, and then changed to D1 = 16 and D2 = 10.

  The first register 21 receives the register update request signal Srld from the N-ary counter 11 and reads and holds the first digital value D1 from the first digital value setting unit 17. Similarly, the second register 23 receives the register update request signal Srld and reads and holds the second digital value D2 from the second digital value setting unit 23. In this embodiment, since the register update request signal Srld is given when the count value of the N-ary counter 11 reaches the maximum value (N−1), each register has a count value of one clock after that. The held digital value is updated at the timing when the initial value returns to zero.

  It should be noted that the values set in the first digital value setting unit 23 and the second digital value setting unit 19 after the reading by the registers 21 and 23 are read out again. It doesn't matter.

  As in the first embodiment, the N-ary counter 11 increases the count value Vcount each time a clock signal is input. The comparison circuit 13 compares the count value Vcount with the second digital value D2 held in the second register 23, and outputs “1” while Vcount <D2. Here, since D2 = 12 is set first, the comparison circuit 13 outputs “1” while Vcount is 11 or less, and changes the output to “0” when Vcount = 12.

  Then, every time a clock signal is input, since the value of Vcount is increasing, the comparison circuit 13 continues to output “0”.

  The N-ary counter 11 recognizes the maximum value of the count value from the first digital value D1 held in the first register 21. Here, since D1 = 64 is held in the first register 21, the N-ary counter 11 repeatedly counts from 0 to 63 (= 64-1).

  When the count value reaches the maximum value (63 in this case), the N-ary counter 11 outputs a register update request signal Srld to the first register 21 and the second register 23.

  When the next clock signal is input to the N-ary counter 11, the count value Vcount returns to 0, as in the first embodiment. Further, the first register 21 reads and holds the first digital value D1 from the first digital value setting unit 17 when the clock signal is input at the next timing when the input of the register update request signal Srld is received. Update the value. Similarly, the second register 23 reads the second digital value D2 from the second digital value setting unit 19 at the same timing, and updates the held value.

  Here, at this time point, D1 = 16 is set in the first digital value setting unit 17 and D2 = 10 is set in the second digital value setting unit 19. Therefore, D1 = 16 is held in the first register 21, and D2 = 10 is held in the second register 23.

  When Vcount of the N-ary counter becomes 0, the comparison circuit 13 changes the output signal to “1” because Vcount <D2. Thereafter, the N-ary counter 11 increases the count value Vcount each time a clock signal is input. The comparison circuit 13 compares the count value Vcount with the second digital value D2 held in the second register 23, and outputs “1” while Vcount <D2. Since D2 = 10 is currently set, the comparison circuit 13 outputs “1” while Vcount is 9 or less, and changes the output to “0” when Vcount = 10.

  Then, as before, since the value of Vcount is increasing every time a clock signal is input thereafter, the comparison circuit 13 continues to output “0”.

  The N-ary counter 11 recognizes the maximum value of the count value from the first digital value D1 held in the first register 21. At this time, since D1 = 16 is held in the first register 21, the N-ary counter 11 repeatedly counts from 0 to 15 (= 16-1).

  Then, the N-ary counter 11 outputs a register update request signal Srld to the first register 21 and the second register 23 when the count value reaches the maximum value (15 in this case) as before.

  When the next clock signal is input to the N-ary counter 11, the count value Vcount returns to zero. The first register 21 reads the first digital value D1 from the first digital value setting unit 17 when the clock signal is input at the next timing when the input of the register update request signal Srld is received, and the value of the held value is stored. Update. The second register 23 also reads the first digital value D2 from the second digital value setting unit 19 at the same timing, and updates the held value. Here, since the same value as before is set in the first digital value setting unit 17 and the second digital value setting unit 19, D1 = 16 in the first register 21 and D2 = in the second register 23. 10 is held.

  Similarly, the output signal of the comparison circuit 13 changes between “0” and “1” according to the value of Vcount. The function of the DFF 15 is the same as that of the first embodiment.

  According to the present embodiment, the set values (D1, D2) are taken into the first register 21 and the second register 23 in accordance with the timing at which the N-ary counter 11 transmits the register update request signal Srld. The N-ary counter 11 and the comparison circuit 13 are configured to operate based on the digital values (D1, D2) held in these registers 21, 23. Therefore, even if the setting value D1 in the first digital value setting unit 17 and the setting value D2 in the second digital value setting unit 19 are changed at any timing, stable pulse width modulation operation is ensured.

  The functions of the first register 21 and the second register 23 provided in the pulse width modulation device 1A of the present embodiment will be described with reference to a timing chart when these registers are not provided.

  FIG. 6 is an example of a timing diagram in a configuration in which the second register 23 is excluded from the modulation device 1A of FIG. Here, the first digital value D1 = 64 is fixed, and the second digital value D2 is set to 12 at the first stage and then changed to 48 at a certain timing. Since the second register 23 is not provided, the comparison circuit 13 compares the count value Vcount with the second digital value D2 directly read from the second digital value setting unit 19, as in the configuration of FIG. .

  Since D2 = 12 is set in the first stage, the comparison circuit 13 outputs “1” while Vcount indicates 11 or less, and changes the output to “0” when Vcount = 12.

  However, after that, the second digital value setting unit 19 changes D2 = 48. In the timing chart of FIG. 6, it is assumed that this change is made at a timing indicating Vcount = 30.

  At this time, the comparison circuit 13 changes the output to “1” in order to detect that Vcount <D2 (reference numeral E1 in the figure). The DFF 15 also changes the modulation signal to H level after one clock and outputs it.

  When Vcount reaches 48, which is the same value as D2, the comparison circuit 13 changes the output to “0” (symbol E2 in the figure). The DFF 15 also changes the modulation signal to L level and outputs it after one clock.

  Thereafter, when the count value reaches the maximum value (63 in this case), the N-ary counter 11 returns to 0. At this time, the comparison circuit 13 changes the output to “1” in order to detect that Vcount <D2. The DFF 15 also changes the modulation signal to L level and outputs it after one clock.

  After that, if the values of D1 and D2 are fixed, the comparison circuit 13 changes the output to “0” at the timing of Vcount = 48 and changes to “1” at the timing of Vcount = 0. repeat.

  According to the example of FIG. 6, an output signal with a duty ratio of 12/64 should be obtained under the conditions set as D1 = 64 and D2 = 12, but the timing when the value of D2 is changed to 48 This causes a problem that the pulse rises and a desired modulation signal cannot be obtained at this point.

  This is a problem to be solved by changing the value of D2 to 48 in the range of Vcount> 48. However, this means that it is necessary to pay attention to the timing of setting change in the second digital value setting unit 19, and the value of D2 is changed in the second digital value setting unit 19 at any timing. It can be seen that the configuration of FIG.

  FIG. 7 is an example of a timing diagram in a configuration in which the first register 21 is excluded from the modulation device 1A of FIG. Here, the second digital value D2 = 12 is fixed, and the first digital value D1 is set to 64 at the first stage and then changed to 16 at a certain timing. Since the first register 21 is not provided, the N-ary counter 11 determines the maximum value of the count value based on the first digital value D1 directly read from the first digital value setting unit 17, as in the configuration of FIG. To do.

  The N-ary counter 11 increases the count value Vcount by 1 each time a clock signal is input. Since D2 = 12 is set, the comparison circuit 13 outputs “1” while Vcount is 11 or less, and changes the output to “0” when Vcount = 12.

  Here, it is assumed that the first digital value setting unit 17 changes to D1 = 16 at a timing indicating Vcount = 16. Then, the N-ary counter 11 detects that the maximum value of the count value Vcount is 15 (16-1) at this time.

  However, since the count value Vcount has already exceeded 16 at this time, the N-ary counter 11 loses sight of the set value for returning the count value Vcount to 0. As a result, the N-ary counter 11 increases the count value Vcount. During this time, since Vcount ≧ D2, the comparison circuit 13 continues to output “0”. As a result, as shown in FIG. 7, the “L” level signal for a long time is output from the comparison circuit 13 and the DFF 15 (reference E3).

  In FIG. 7, it is assumed that the N-ary counter 11 is configured to return to “0” when it reaches the maximum count value X that can be designed. In this case, once Vcount returns to 0, a desired modulation signal is output according to the settings of D1 = 16 and D2 = 12. However, it takes a long time to return to the correct operation in this way, and during that time, a signal different from the desired signal continues to be output.

  Even in this case, the problem can be solved by changing the value of D1 to 12 in the range of Vcount <12. However, this means that it is necessary to pay attention to the timing of setting change in the first digital value setting unit 17, and the value of D1 is changed in the first digital value setting unit 17 at any timing. It can be seen that the configuration of FIG.

[Another embodiment]
Hereinafter, another embodiment will be described.

  <1> The N-ary counter 11 may be a down counter. In this case, the N-ary counter 11 decreases the count value by 1 when the clock signal is input once. The count value is sequentially counted down from (N-1) to 0, and when the clock signal is input after counting 0, the count value is returned to (N-1) again. This is repeated below.

  <2> The first digital value setting unit 17 may set the value of (N−1) that is the maximum value of the count value as the first digital value D1. In this case, if D1 = 63 is set, the N-ary counter 11 is configured to repeatedly count from 0 to 63.

Further, when it is configured to set the width of the count value of the N-ary counter 11 in 2 ^alpha may set the value of this alpha as a first digital value D1. In this case, if D1 = 6 is set, the N-ary counter 11 is configured to repeatedly count from 0 to 63 (= 2 ⁶ −1) as described above.

  <3> The pulse width modulation device 1A shown in the second embodiment is configured to include both the first register 21 and the second register 23, but may be configured to include only one of them. is there. However, as described above, it is preferable to provide both registers in that the timing for changing the set value can be freely set for both the first digital value D1 and the second digital value D2.

  <4> In the second embodiment, the N-ary counter 11 transmits the register update request signal Srld when the count value Vcount reaches the maximum count value determined by the first digital value D1. .

  However, the transmission timing of the signal Srld does not necessarily have to be when Vcount reaches the maximum value. For example, it may be the time when a value obtained by subtracting a predetermined number from the maximum value is reached. Furthermore, a configuration may be adopted in which the update timings of the first register 21 and the second register can be appropriately designated by separately providing an external control signal.

  <5> In the pulse width modulation device 1A of the second embodiment shown in FIG. 4, the register update request signal Srld is transmitted from the N-ary counter 11 to the first register 21 and the second register 23. It is not limited to. For example, the register update request signal Srld is transmitted from the N-ary counter 11 only to the first register 21 which is one of the registers, and the first register 21 receives the signal Srld and receives the second register update request. A signal is output to the second register 23. In this case, the digital value of the second register 23 is updated one clock or more later than the first register 21, but the same operation as in the second embodiment is possible.

  <6> In the above embodiment, the comparison circuit 13 outputs “1” when Vcount <D2, and “0” otherwise, regarding the magnitude relationship between the count value Vcount of the counter 11 and the second digital value D2. However, the signal generation rule of the comparison circuit 13 is not limited to this content. For example, a certain positive or negative integer P may be used so that “1” is output when Vcount <D2−P and “0” is output otherwise. Furthermore, in the above rules, the rules for outputting “1” and “0” may be switched.

1, 1A: Pulse width modulation device of the present invention 3: Clock signal input terminal 5: Modulation signal output terminal 11: N-ary counter 13: Comparison circuit 15: DFF
17: First digital value setting unit 19: Second digital value setting unit 21: First register 23: Second register

Claims (5)

A pulse width modulation device that forms and outputs a modulation signal in which the pulse width and frequency of an input clock signal are changed,
A counter for counting the number of pulses of the clock signal;
A first digital value setting unit for setting a first digital value for determining the frequency of the modulation signal;
A second digital value setting unit for setting a second digital value for determining the pulse width of the modulation signal;
A comparison circuit that compares the count value of the counter with the second digital value and outputs a binary signal in accordance with the magnitude relationship;
When the counter is an up counter, the count value is smaller than the maximum value when the clock signal is input after the count value reaches the maximum value determined based on the first digital value. Change to the initial value and count again,
When the counter is a down counter, when the clock signal is input after the count value reaches the minimum value determined based on the first digital value, the count value is larger than the minimum value. It is a configuration that changes to the initial value and counts again,
The pulse width modulation device, wherein the modulation signal is the binary signal itself output from the comparison circuit or a signal obtained by subjecting the binary signal to signal processing. A first register for temporarily holding the first digital value;
The counter is configured to determine the maximum value or the minimum value based on the first digital value held in the first register;
The first register is configured to update the held value by reading the first digital value from the first digital value setting unit when the count value of the counter reaches a specific value. Item 2. The pulse width modulation device according to Item 1. A second register for temporarily holding the second digital value;
The comparison circuit is configured to compare the second digital value held in the second register with the count value of the counter;
The second register is configured to read the second digital value from the second digital value setting unit and update a held value when a count value of the counter reaches a specific value. Item 3. The pulse width modulation device according to Item 1 or 2.   4. The pulse width modulation device according to claim 2, wherein the specific value is the initial value.   5. The pulse width modulation device according to claim 1, further comprising a DFF configured to shape the binary signal output from the comparison circuit and synchronize with the clock signal.

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