JP2012003339A - Processor, processor generation device and processor generating system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a processor with required functions and properties at low cost by eliminating unused circuits in the processor.SOLUTION: A processor which is designed and determined to generate a dedicated processor in which an instruction is read out from a memory device and analyzed by a decoder to sequentially perform processing based on the analysis includes at least a configuration definition description which is directed to the instruction and a circuit description for defining circuits in the dedicated processor. The processor is configured to be capable of eliminating arbitrary instructions from pre-provided instructions and also eliminating unnecessary circuits as a result of the elimination of the arbitrary instructions.

Description

  Embodiments described herein relate generally to a processor, a processor generation device, and a processor generation system.

  In recent years, circuit design using a custom LSI has become common in system development due to the spread of field programmable gate arrays (FPGAs). The FPGA is a type of custom LSI configured so that the user can define and change the circuit configuration.

  The system developer is in charge of various designs according to the use of the system, but hardly designs the circuit of the processor itself. Developing a processor requires advanced expertise, enormous resources, and costs, including not only circuit design, but also development tools such as an assembler, compiler, and debugger for the processor. is there.

  Therefore, when a processor is mounted on a custom LSI during system development, the system developer has the necessary functions and sufficient performance from among several processor IP cores (Intellectual Property Core), as well as development tools and costs. A processor IP core that satisfies the conditions is selected and installed. For this reason, processor IP cores provided by vendors and the like are often general-purpose processor IP cores adopting a standard architecture so as to be compatible with various systems.

  However, since the general-purpose processor IP core is designed to be adaptable to various systems, the system developer is dissatisfied with unnecessary functions that are not used, thereby incurring unnecessary costs. You may feel it. For example, there is a project to develop a system that performs integer arithmetic processing at ultra-high speed, and a high-performance processor that satisfies this project is required. High-performance general-purpose processor IP cores often have unnecessary functions. For example, when the general-purpose processor IP core has a floating-point number arithmetic function in addition to the integer arithmetic processing function, this floating-point number arithmetic function is unnecessary in a system that performs integer arithmetic processing. However, the extra circuit cost associated with floating point arithmetic that is not used cannot be deleted even if it is recognized as being useless.

  Therefore, some general-purpose processor IP cores are configured so that custom instructions can be added and deleted. If the floating-point arithmetic instruction can be deleted by the customization function, the extra circuit cost related to the floating-point arithmetic in the above example can be reduced.

JP 2007-25010 A JP 2009-015867 A

  However, a general-purpose processor IP core having a customization function has few degrees of freedom of selectable instructions and functions. The reason why the general-purpose processor IP core has the customization function is mainly because it is aimed at improving the performance, and it is considered that the reduction of the circuit cost is not so important. That is, since the unused circuit scale occupying the entire circuit scale of the custom LSI is small, it is estimated that it is judged that the cost reduction effect is low even if the unused circuit is deleted by customization. In fact, there is a background that as the miniaturization of semiconductor processes progresses, the manufacturing cost of a custom LSI remains the same regardless of whether a small circuit is mounted or not.

  But this situation is already changing. One reason for this is that so-called multiprocessors, in which a plurality of processors are mounted on one custom LSI, are being promoted. The number of processors mounted on one custom LSI varies depending on the system project, but there are many from about a few to a dozen. Recently, however, there are cases where hundreds or more processors are mounted on a single custom LSI. A slight circuit cost that does not become a problem with a single processor accumulates for the number of processors in a multiprocessor. For this reason, the above-described increase in circuit cost cannot be ignored.

  In the above description, the customization target of the processor is limited to only the arithmetic instruction, but the circuit constituting the processor is not only the circuit that processes the instruction. It is desirable that other circuits such as a circuit related to an arithmetic register and a circuit related to an interrupt can be deleted if not used.

  Further, from the viewpoint of power consumption, the presence of unused circuits may increase not only circuit costs but also various costs. Specifically, unused circuits that consume useless power generate extra heat, which affects cooling costs, package costs, board mounting costs, power supply costs, and the like.

  Accordingly, there is a need to delete unused circuits in the processor and to provide a processor having necessary functions and performance at a low cost.

  According to an embodiment of the present invention for solving the above-described problem, a design description for generating a dedicated processor that reads an instruction from a storage device, interprets the instruction by a decoder, and sequentially proceeds with processing based on the interpretation. The processor includes a configuration definition description for at least an instruction and a circuit description for defining a circuit in the dedicated processor, and the processor includes an arbitrary instruction among pre-installed instructions. There is provided a processor capable of deleting an instruction and deleting a circuit which becomes unnecessary by the deletion.

The figure for demonstrating the structure and operation | movement of the conventional customizable processor which concerns on embodiment of this invention. The figure for demonstrating the structure and operation | movement of the processor production | generation system which concern on embodiment of this invention. The figure which shows the example of description of CS processor which concerns on embodiment of this invention. The figure for demonstrating the structure and operation | movement of the processor production | generation system which concern on embodiment of this invention. The figure which shows the example of customization of the circuit which concerns on the register | resistor which concerns on embodiment of this invention. The figure for demonstrating the customization method which concerns on embodiment of this invention. The figure which illustrates customization of S processor concerning an embodiment of the present invention.

(First embodiment)
Before describing the processor according to the embodiment of the present invention, a general customizable processor will be described.
FIG. 1 is a diagram for explaining the configuration and operation of a conventional customizable processor 1. The upper part of FIG. 1 shows a functional block diagram of the processor 1, and the lower part shows an example of a customizable arithmetic circuit.

  The processor 1 includes a controller 11, a decoder 12, a switch 13, a calculator 14, and a register file 15. The processor 1 exchanges information with the instruction memory 2 and the data memory 3 to execute processing operations.

  The instruction memory 2 stores an instruction (Instruction) of a program that controls the operation of the processor 1. Instructions are sequentially taken out from the instruction memory 2 and sent to the decoder 12. The decoder 12 interprets the fetched instruction and generates a signal for controlling the operation of the processor 1. A signal from the decoder 12 is input to the controller 11, and the controller 11 controls the operation of each unit of the processor 1 in accordance with an instruction interpreted by the decoder 12. A signal from the decoder 12 is output to each part in the processor 1.

  A signal from the decoder 12 is input to the calculator 14 via the switch 13. The signal from the decoder 12 is temporarily stored in the register file 15 and then input to the arithmetic unit 14 via the switch 13. The arithmetic unit 14 is an ALU (Arithmetic Logical Unit) that performs arithmetic operation or logical operation on an input signal. The switch 13 switches the signal corresponding to the type of calculation and outputs it to the calculator 14. The calculation result is stored in the data memory 3. Depending on the type of calculation, the calculation result is fed back to the switch 13 and the register file 15.

  The data memory 3 has an input / output function for external signals as well as data storage. That is, a signal from the processor 1 is output to the outside via the data memory 3, and a signal from the outside is taken into the processor 1 via the data memory 3. In FIG. 1, the instruction memory 2 and the data memory 3 are separated from each other. However, they can be configured integrally.

Next, the customization function of the processor 1 will be described using the calculator 14 as an example.
When the arithmetic unit 14 has four arithmetic operations (addition, subtraction, multiplication, division) and logical operation (product, sum) functions as basic arithmetic functions, when the processor 1 is constructed, the customization function is used for the basic arithmetic functions. In addition, complex number arithmetic, floating point number arithmetic, DSP (Digital Signal Processing) arithmetic, SIMD (Single Instruction Multiple Data) arithmetic, and user-defined arithmetic can be appropriately selected and added.

The general-purpose processor IP core that can be customized in this way generally has the following instruction configuration.
[Basic instructions] + [Optional instructions] + [User-defined instructions]
In other words, an optional instruction and a user-defined instruction are added as needed based on the basic instruction.

  Of these, basic instructions consist of control instructions, data transfer instructions, logical operation instructions, and simple integer operation instructions, and cannot be customized, that is, deleted. Optional instructions are composed of complex integer arithmetic instructions, floating point number arithmetic instructions, DSP arithmetic instructions, SIMD arithmetic instructions, and the like, and can be customized by adding to basic instructions.

  User-defined instructions can be customized as well as optional instructions. The difference between the option instruction and the user-defined instruction is that the former has a dedicated arithmetic circuit prepared in advance, whereas the latter has to prepare the arithmetic circuit by the user. In any case, there is no difference in the structure of the processor in realizing the customization function, with the option instruction and the user-defined instruction being different only in the provider of the arithmetic circuit.

  The problem here is that a processor having a customization function can be customized only to specific operation instructions as shown in FIG. The reason for customizing is limited to the operation instruction because the operation instruction is not easily influenced by the control mechanism inside the processor. For example, control instructions such as branch instructions and data transfer instructions are instructions that form the basis of the processor and work in close cooperation with various control circuits inside the processor. Customization of calculation instructions only requires switching between three or four data paths in the processor, while control-related instructions need to switch not only the data path but also the control path, and the points and timings to be switched for each instruction. Will change. Control instructions are often linked with development tools such as compilers, and customization of these instructions has a great impact on development tools. Therefore, these commands are positioned as basic commands and excluded from customization.

  Even if the instruction can be customized, the degree of freedom is not great. For example, when a floating point arithmetic instruction is selected as an optional instruction, the unit of the selection is "instruction group related to single precision floating point arithmetic", "instruction group related to double precision floating point arithmetic", etc. Thus, the instruction group unit. Even when only specific instructions are used, selection must be made in units of instruction groups including related instructions.

  As described above, in the conventional customization function, instructions that can be customized are limited to specific instructions.

FIG. 2 is a diagram for explaining the configuration and operation of the processor generation system 20 according to the embodiment of this invention.
The operation of the processor generation system 20 will be described. The processor generation system 20 generates an execution code, which is a code processed by the dedicated processor 35, from the source code of the user program 30, and outputs the execution code to the ROM / RAM 34 in the system board or system LSI. Here, the dedicated processor 35 is a processor generated as a dedicated product for executing the user program 30.

  Further, the processor generation system 20 generates a reconfiguration processor 31 (details will be described later). The reconfiguration processor 31 includes a circuit description for only the circuits necessary for executing the user program 30. In other words, a circuit description about a circuit that the user program 30 does not need is not included. The synthesizer 32 generates a dedicated processor 35 by synthesizing (logic synthesis) the reconfigurable processor 31.

  The generated dedicated processor 35 is provided in a system board or LSI. The dedicated processor 35 operates according to the execution code stored in the ROM / RAM 34. The dedicated processor 35 in FIG. 2 corresponds to the processor 1 in FIG. 1, and the ROM / RAM 34 corresponds to the instruction memory 2 and the data memory 3 in FIG.

  The processor generation system 20 includes a software development tool 21, an execution code file 22, a list file 23, a map file 24, a configurable and synthesizeable processor 25 (hereinafter referred to as “CS processor”), and a processor configuration tool 26 (hereinafter referred to as “CS processor”). And a user-defined file 27.

  The software development tool 21 includes an assembler, a compiler, a linker, and the like, and assembles or compiles the user program 30 to generate an execution code. The generated execution code is output to the ROM / RAM 34 in the system board or system LSI. The execution code file 22 is a file for storing the execution code generated by the software development tool. The list file 23 is a file for storing a list. The map file 24 is a file that stores data representing the use state of a memory such as a register.

  The CS processor 25 is designed and described in HDL (hardware Description Language) or the like, and becomes the basis for configuring (generating) the dedicated processor 35. That is, the CS processor 25 is a processor that is configurable (configurable) and synthesizeable (logic synthesis is possible). The CS processor 25 includes all design descriptions for the circuits constituting the dedicated processor 35. The processor generation device 26 investigates the usage status of instructions and various resources based on the data stored in the execution code file 22, the list file 23, and the map file 24. Based on the investigation result, the processor generation device 26 processes the CS processor 25 to generate a reconfigurable processor 31 adapted to the user program 30.

Next, the processor generation device 26 and the CS processor 25 will be described in detail.
The processor generation device 26, from the execution code file 22, the list file 23, the map file 24, etc. generated by the software development tool 21, the type of instruction used in the user program 30, the type and range of registers used, Check the type and range of interrupts used and the type and range of address spaces used. Then, the processor generation device 26 defines the configuration based on the result and generates the reconfiguration processor 31.

  The CS processor 25 is the basis of a configuration designed and described in HDL (hardware Description Language) or the like. FIG. 3 is a diagram illustrating an example of the description of the CS processor 25.

  `Ifdef INST_SLEEP on line 00001 is a directive that means" If the sleep instruction is necessary, the subsequent description is valid. " INST_SLEEP is one of the configuration definitions described above, and is defined when the processor generation device 26 determines that the dedicated processor 35 needs a sleep instruction. The statement 1 on the 00002 line indicates the circuit description actually necessary for executing the sleep instruction. Similarly, `ifdef INST_JUMP_JUMPF_LINK_LINKF on the 00005 line is a directive that means" if any jump, jumpf, link, or linkf instruction is required, the subsequent description is valid ". This INST_JUMP_JUMPF_LINK_LINKF is also one of the configuration definitions defined by the processor generation device 26, and the description after the 0006th line indicates the circuit description actually necessary for executing the jump, jumpf, link, and linkf instructions.

  As described above, the processor generation device 26 defines various configurations according to the instruction used by the user program 30 and the type of resource. Based on the definition, necessary circuits and unnecessary circuits are classified from the description of the CS processor 25 to generate the reconfiguration processor 31.

  In the case of a general customized processor, the instructions to be configured are limited to some arithmetic instructions, whereas in the method for generating the dedicated processor 35 of the present embodiment, all instructions are configured. It is possible to target. Furthermore, not only instructions but also resources such as registers, interrupts, and address spaces can be similarly configured.

  For example, the register usage status can be checked by referring to the execution code file 22 shown in FIG. The processor generation device 26 performs configuration definition such as REG_LINK, REG_3, REG_4... Based on the registers actually used. These definitions are referred to as, for example, `ifdef REG_LINK on the 0006 line in FIG. In this example, when the link register is used, the circuit description of statement2 is validated, and when the link register is not used, the circuit description of statement3 is validated. Only such necessary register circuits can be implemented by such definitions and circuit descriptions.

As described above, it is possible to generate the dedicated processor 35 which requires a minimum necessary circuit according to the contents of the user program 30. The basic configuration of the processor of the present embodiment is as follows.
[Advanced processor]-[Unused instruction]-[Unused resource]
That is, the configuration is such that unused instructions and unused resources are deleted based on a high-function processor.

  In the present embodiment, not only the user program 30 but also a command or function that the user deletes in advance or a command or function that is not deleted is directly defined, and the dedicated processor 35 is based on the definition. It is also possible to remove unnecessary circuits or leave circuits that may be used in the future. For example, as shown in FIG. 2, a user definition file 27 that directly defines a command or function to be deleted by the user is provided. The processor generation device 26 refers to the user definition file 27 in addition to the execution code file 22, the list file 23, and the map file 24, and generates the reconfiguration processor 31.

  For many common customization processors, software development and processor customization are independent of each other. For this reason, the user always has to advance the system design so that the content of the user program matches the customization content. In contrast, the present embodiment is characterized in that software development and processor generation can be executed in association with each other in a series of business flows. Accordingly, the present invention is not limited to the case where a user program is newly created, and even when the created user program is changed, a dedicated processor can be generated each time the change is made. As a result, it is not necessary for the user to study the processor for a long time to customize the processor, and the efficiency of business can be dramatically improved.

(Variation of the first embodiment)
In the first embodiment shown in FIG. 2, the ROM / RAM 34 and the dedicated processor 35 are separate from each other, but they can be configured as an integral unit. Specifically, the means for writing / downloading from the execution code file 22 to the ROM / RAM 34 and the ROM / RAM 34 are eliminated, and the reconfigurable processor 31 and the dedicated processor 35 instead have a circuit corresponding to the ROM / RAM 34 inside. It becomes a form that includes. The processor generation device 26 determines the configuration of the ROM / RAM based on the data stored in the execution code file 22, the list file 23, and the map file 24, and generates a ROM / RAM integrated dedicated processor.

  When the ROM / RAM 34 is provided separately, there are restrictions on the capacity of the ROM / RAM 34 to be used. On the other hand, in the variation, the capacity of the ROM / RAM 34 can be flexibly configured from a large capacity to a small capacity corresponding to the user program 30. Therefore, it is possible to obtain a remarkable effect that the degree of freedom of design in system development is increased.

(Second Embodiment)
FIG. 4 is a diagram for explaining the configuration and operation of the processor generation system 20 according to the second embodiment of this invention.
The second embodiment is different from the first embodiment in that a feedback route from the processor generation device 26 to the software development tool 21 is added. Accordingly, the same parts as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the second embodiment, the customization target is a target other than an instruction, for example, a circuit related to an arithmetic register, a circuit related to an interrupt, or the like.

  For example, suppose that there is a processor having 32 arithmetic registers as a standard. If only 20 operation registers are actually used, the remaining 12 operation registers are useless. Assume that there is a processor that supports 256 interrupts as a standard. In reality, if only 10 are sufficient, the remaining 246 circuits are wasted. Depending on the system project, even an interrupt function may not be required. In addition, if only 12 bits are actually used in the 32-bit address space, the remaining 20-bit circuit is wasted.

  In the processor generation system 20 shown in the first embodiment, unnecessary registers can be reduced to some extent even in such a case, but in the second embodiment, further reduction can be achieved.

FIG. 5 is a diagram illustrating an example of customization of a circuit related to a register in the second embodiment.
For example, it is assumed that there are 32 registers from No. 0 to No. 31 and the user program 30 uses No. 0 to No. 5 and No. 15 of them. Looking at the minimum and maximum numbers of the registers used, the numbers are 0 and 15, respectively, and 16 registers 0 to 15 are sufficient for the register circuit. Therefore, the circuits of the registers No. 15 to No. 15 are left and the other registers are removed, but since there are actually seven registers, nine registers No. 6 to No. 14 are unused. However, it remains as a useless circuit.

  The processor generation device 26 shown in FIG. 4 grasps the usage status of resources (registers) based on the execution code file 22, the list file 23, and the map file 24 and records the result in the report file 41. The analysis unit 42 refers to the report file 41 and checks how the resources can be changed to reduce the circuit. In the above example, if the number 15 register is changed to the number 6 register, useless circuits can be reduced.

  Therefore, the analysis unit 42 instructs the software development tool 21 to change the number of the 15th register to the 6th register. The software development tool 21 changes the register number according to the feedback instruction and regenerates the execution code and the like. As a result, the minimum and maximum numbers of the registers used are 0 and 6, respectively, and the operation of the processor generation system 20 described in the first embodiment leaves the circuits of registers 0 to 6 and others. The circuit is removed.

  According to the second embodiment, it is possible to further reduce useless circuits. In the first and second embodiments, the circuit that can be reduced is not limited to the circuit of the register itself, but of course includes a circuit related to the register. That is, in the above-described example, it is possible to reduce at least a part of the registers and functions related to the registers.

  The same applies not only to registers but also to a specific range of memory, interrupt and I / O allocation, exception processing (for example, 0 divide) circuit, and memory address index processing circuit.

  In the second embodiment, the ROM / RAM 34 and the dedicated processor 35 described in the variations of the first embodiment can be adopted as an integral unit.

(Third embodiment)
In the first embodiment, the usage instructions and usage resources of the user program 30 are statically examined, and customization is performed based on the results. On the other hand, in the third embodiment, the use instruction and the use resource are dynamically examined and customized based on the result. The method will be described. In addition, the same code | symbol is attached | subjected to the site | part same as 1st Embodiment, and the detailed description is abbreviate | omitted.

FIG. 6 is a diagram for explaining a customization method according to the third embodiment.
The processor to be customized is premised on a synthesizeable processor 50 (hereinafter referred to as “S processor”) whose description is allowed to be changed. The S processor 50 does not need to be configurable like the CS processor 25 shown in FIG. 2, and does not require a description as shown in FIG.

  After the selection of the processor and the development of the user program are completed, the user program 30 is executed on the simulator or on the actual machine. At that time, as shown in FIG. 6, some or all of the control signals in the S processor 50 are connected to the customization monitor 51. This customization monitor 51 may be connected only when customizing the S processor 50.

  The customization monitor 51 records each control signal of the S processor 50 that is executing the user program. By examining the change (transition) of each control signal recorded by the customization monitor 51, the usage status of the circuit of the S processor 50 can be grasped. Specifically, if there is a signal transition, it means that the control signal has been activated, and indicates that the circuit controlled by the control signal has been used by the user program 30. On the other hand, if there is no signal transition, it indicates that the circuit controlled by the control signal is a useless circuit that did not function in executing the user program 30.

  After the execution of the user program 30 and the signal recording by the customization monitor 51 are sufficiently completed, customization is performed using the S processor 50. Specifically, among the control signals of the S processor 50, the control signals obtained by the customization monitor 51 that do not change during recording are disconnected and replaced with a fixed value of 0 or 1.

FIG. 7 is a diagram illustrating customization of the S processor 50. 7A is an original description of the S processor 50, and FIG. 7B is a description after customization.
FIG. 7 shows an example in which there is no transition of the control signal BBB on the recording by the customization monitor 51 and the value remains unchanged at 1. Since the control signal BBB is always 1, in FIG. 7B, the part referring to the BBB on the 00009 line is replaced with 'b1 (binary 1). The customization of the S processor 50 is to replace a portion that refers to a control signal that has not changed with a fixed value.

  After the customization of the S processor 50 is completed, a customized processor can be obtained by following a general logic synthesis procedure. A circuit description given a fixed value at the stage of logic synthesis is optimized and disappears by logic optimization, and a processor customized to the minimum circuit necessary for executing the user program 30 can be obtained.

  In the third embodiment, when executing customization, it is not necessary to know in detail the instruction, register, interrupt, address space, etc. used. Since the necessity / unnecessity of the circuit ahead is determined only by whether or not the control signal is activated, all the circuits can be customized.

  Note that the S processor 50 used in the present embodiment may be a type of processor whose description is allowed to be changed. That is, customization is possible if the processor is of a type that allows description changes. Since there are many such types of processors, this customization method can be widely applied.

[The invention's effect]
According to the embodiment described above, various effects can be achieved.

  According to the present embodiment, it is possible to provide a processor that has functions necessary for system development, eliminates useless circuits, and minimizes circuit costs. As a result, it is possible to reduce the manufacturing cost of a custom LSI on which this processor is mounted. Further, when a multiprocessor configuration is adopted, more processors can be mounted, which leads to an improvement in performance.

  At the same time, thanks to the fact that a large number of circuits can be mounted on a single custom LSI due to the miniaturization of semiconductor processes, the increase in power consumption and heat generation of LSIs has become a problem in system development. Since the processor of this embodiment can reduce power consumption by eliminating unnecessary circuits, it can be expected to reduce cooling costs, package costs, board mounting costs, power supply costs, and the like. In particular, in the case of adopting a multiprocessor configuration, the accumulation of useless circuits is eliminated, and the effect becomes remarkable.

  Note that the functions described in the above-described embodiments are not limited to being configured using hardware, and can be realized by causing a computer to read a program describing each function using software. Each function may be configured by appropriately selecting either software or hardware.

Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage.
Various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine suitably the component covering different embodiment.

  DESCRIPTION OF SYMBOLS 1 ... Processor, 2 ... Instruction memory, 3 ... Data memory, 9 ... Register, 11 ... Controller, 12 ... Decoder, 13 ... Switch, 14 ... Operation unit, 15 ... Register file, 20 ... Processor generation system, 21 ... Software Development tool, 22 ... executable code file, 23 ... list file, 24 ... map file, 25 ... synthesizeable processor, 26 ... processor configuration tool (processor generator), 27 ... user definition file, 30 ... user program, 31 ... Reconfigurable processor, 32 ... synthesizer, 34 ... RAM / ROM, 35 ... dedicated processor, 41 ... report file, 42 ... analysis unit, 50 ... synthesizeable processor, 51 ... customized monitor.

Claims (7)

In a processor described in the design for generating a dedicated processor that reads an instruction from a storage device, interprets the instruction in a decoder, and sequentially proceeds based on the interpretation.
The processor has a configuration definition description for at least an instruction and a circuit description for defining a circuit in the dedicated processor,
The processor is characterized in that an arbitrary instruction can be deleted from pre-installed instructions and a circuit that becomes unnecessary due to the deletion can be deleted. The processor can delete a circuit related to a part or all of a specific function among the functions provided in advance,
The specific function that can be deleted is a function related to a register, a function related to a specific arithmetic unit, a function related to interrupt / exception processing, a function indicating a memory space in a specific range, or a memory address index calculation. The processor according to claim 1, wherein the processor is a related function. In the processor production | generation apparatus which produces | generates a new processor from the processor of Claim 1 or 2,
An analysis unit that statically analyzes at least the usage of the instruction based on an instruction code generated by a software development tool including an assembler and a compiler from a software program for operating the dedicated processor;
An extraction unit that extracts an instruction that can be deleted from the processor based on the analysis result;
A processor generation device comprising: a generation unit that deletes an extracted instruction from the processor and generates a new processor by deleting a circuit that becomes unnecessary due to the deletion of the instruction from the processor. In the processor production | generation apparatus which produces | generates a new processor from the processor of Claim 1 or 2,
Based on a definition file that defines at least an instruction to be deleted from the processor, the defined instruction is deleted from the processor, and a circuit unnecessary due to the deletion of the instruction is deleted from the processor to generate a new processor A processor generation device comprising a generation unit that performs the above-described operation. In the processor production | generation apparatus which produces | generates a new processor from the processor of Claim 1 or 2,
An analysis unit that statically analyzes at least the usage of the instruction based on an instruction code generated by a software development tool including an assembler and a compiler from a software program for operating the dedicated processor;
A first extraction unit that extracts an instruction that can be deleted from the processor based on the analysis result;
A second extraction unit that extracts an instruction that can be deleted from the processor based on a definition file that defines at least an instruction to be deleted from the processor;
And a generation unit that deletes the instructions extracted by the first and second extraction units from the processor, and generates a new processor by deleting a circuit that is unnecessary due to the deletion of the instructions from the processor. A featured processor generator. A processor according to claim 1 or 2, and
An assembler that generates an instruction code from a software program for operating the dedicated processor, a software development tool including a compiler, and
A processor generation system comprising: the processor generation device according to claim 3.   The processor generation system according to claim 6, further comprising a change instruction unit that instructs the software development tool to further reduce the circuits based on an analysis result of the processor generation device. .

Images