JP2011244128A - Clock generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock generation circuit capable of making a lock-up time short.SOLUTION: The clock generation circuit 1 comprises: a spread spectrum clock generation circuit 10 generating a modulation clock SCLK with a frequency modulated based on a reference clock RCLK; and a phase comparator 20 that outputs a H level lock signal LOCK when detecting phase coincidence between the reference clock RCLK and the modulation clock SCLK. Moreover, the clock generation circuit 1 comprises a selector 50 that selects the reference clock RCLK as an output clock CLK until the H level lock signal LOCK is output, and selects the modulation clock SCLK in response to the output of the H level lock signal.

Description

  The present invention relates to a clock generation circuit.

  In recent years, with the increase in speed and integration of semiconductor devices, electromagnetic radiation from the devices has become a problem. In view of this, it has been practiced to slightly spread the operation clock of the semiconductor device, thereby performing spectrum spread of the clock and reducing electromagnetic radiation (for example, see Patent Document 1). A clock generation circuit that generates such a clock is called a spread spectrum clock generator (SSCG).

JP 2004-104655 A

  However, since SSCG has a slow frequency response, the lockup time becomes long. For this reason, in a semiconductor device equipped with SSCG, it is necessary to wait until the operation clock is stabilized, and there is a problem that wasteful current consumption increases.

  According to one aspect of the present invention, a spread spectrum clock generation circuit that generates a modulation clock having a frequency modulated based on a reference clock, and detecting that the phase of the reference clock matches the phase of the modulation clock A phase comparator that outputs a detection signal when the detection signal is output, and the reference clock is selected as an output clock until the detection signal is output, and the modulation clock is selected as the output clock in response to the output of the detection signal And a selection circuit.

  According to one aspect of the present invention, the lockup time can be shortened.

The block diagram which shows the clock generation circuit of 1st Embodiment. The block diagram which shows the internal structural example of SSCG of 1st Embodiment. The wave form diagram for demonstrating the modulation degree setting of SSCG. FIG. 3 is a block circuit diagram showing an example of an internal configuration of the phase comparator according to the first embodiment. Explanatory drawing for demonstrating the switch setting of a phase comparator. The wave form diagram for demonstrating operation | movement of a phase comparator. The wave form diagram for demonstrating operation | movement of a clock generation circuit. The block diagram which shows the clock generation circuit of 2nd Embodiment. The block diagram which shows the internal structural example of SSCG of 2nd Embodiment. Explanatory drawing which shows the relationship between a modulation degree and detection sensitivity.

(First embodiment)
Hereinafter, a first embodiment will be described with reference to FIGS.
As shown in FIG. 1, the clock generation circuit 1 includes a spread spectrum clock generation circuit (SSCG) 10, a phase comparator 20, a D-flip flop circuit (D-FF circuit) 40, and a selector 50.

  The SSCG 10 is a clock generation circuit with a frequency modulation function that generates a modulation clock SCLK whose frequency is modulated. Based on the reference clock RCLK, the SSCG 10 generates a modulation clock SCLK whose frequency is slightly changed around the frequency corresponding to the frequency of the reference clock RCLK.

  The phase comparator 20 outputs a lock signal LOCK corresponding to the comparison result between the phase of the reference clock RCLK and the phase of the modulation clock SCLK to the D-FF circuit 40. Specifically, the phase comparator 20 outputs a lock signal LOCK having a predetermined pulse width when the phases of the reference clock RCLK and the modulation clock SCLK (the falling edge in this example) match. Note that the pulse width of the lock signal LOCK is set to be longer than, for example, a half cycle of the reference clock RCLK.

  The high potential side power supply voltage VDD is supplied to the input terminal D of the D-FF circuit 40. The lock signal LOCK is supplied from the phase comparator 20 to the enable terminal EN of the D-FF circuit 40. Further, the reference clock RCLK is supplied to the clock terminal CK of the D-FF circuit 40. When the reference clock RCLK rises when the H-level lock signal LOCK is supplied, the D-FF circuit 40 selects the power supply voltage VDD input to the input terminal D in synchronization with the rising edge. The signal SEL is output to the selector 50. The D-FF circuit 40 outputs an L level selection signal SEL to the selector 50 until the power supply voltage VDD is latched.

  The selector 50 outputs the reference clock RCLK or the modulation clock SCLK as an output clock CLK to an internal circuit (not shown) according to the selection signal SEL. Specifically, the selector 50 outputs the reference clock RCLK as the output clock CLK in response to the L level selection signal SEL, and outputs the modulation clock SCLK as the output clock CLK in response to the H level selection signal SEL. To do. That is, the selector 50 outputs the reference clock RCLK as the output clock CLK until the phases of the reference clock RCLK and the modulation clock SCLK match. The selector 50 switches the output clock CLK from the reference clock RCLK to the modulation clock SCLK when the phase of the reference clock RCLK matches the phase of the modulation clock SCLK. Thereafter, the selector 50 outputs the modulation clock SCLK as the output clock CLK.

Next, an example of the internal configuration of the SSCG 10 will be described with reference to FIG.
As shown in FIG. 2, the SSCG 10 includes a 1 / N frequency divider 11, a frequency phase comparator 12, a charge pump 13, a loop filter 14, a voltage controlled oscillator (VCO) 15, and a 1 / M frequency divider. And a control circuit 17.

  The 1 / N frequency divider 11 supplies a signal obtained by dividing the reference clock RCLK by 1 / N times (N is an integer) to the frequency phase comparator 12. The 1 / M frequency divider 16 supplies the frequency phase comparator 12 with a signal obtained by frequency-dividing the modulation clock SCLK output from the VCO 15 by 1 / M times (M is an integer).

  The frequency phase comparator 12 supplies the charge pump 13 with a phase difference signal corresponding to the phase difference between the reference clock RCLK divided by 1 / N and the modulation clock SCLK divided by 1 / M.

  The charge pump 13 outputs a signal based on the phase difference signal from the frequency phase comparator 12 to the loop filter 14. The loop filter 14 generates a smoothed voltage signal by removing high-frequency component noise and the like from the output signal of the charge pump 13, and supplies the voltage signal to the VCO 15. The loop filter 14 includes a resistor R1 and a capacitor C1.

  The VCO 15 generates a modulation clock SCLK having a frequency corresponding to the voltage signal from the loop filter 14. The VCO 15 includes a voltage-current converter (VI converter) 15a, a current digital-analog converter (IDAC) 15b, and a current-controlled oscillator (ICO) 15c.

  The VI converter 15a converts the voltage signal from the loop filter 14 into a current signal and supplies the current signal to the IDAC 15b. The IDAC 15b changes and outputs the current value of the current signal input from the VI converter 15a based on the modulation signal from the control circuit 17. The ICO 15c oscillates and outputs the modulation clock SCLK having a frequency corresponding to the current value of the current signal changed in the IDAC 15b to the 1 / M frequency divider 16 and the phase comparator 20 shown in FIG. As described above, the VCO 15 modulates the frequency of the modulation clock SCLK by periodically or randomly changing the current signal for controlling the oscillation frequency in the IDAC 15b. For example, as shown in FIG. 3, the control circuit 17 modulates the current signal by periodically varying ± 0.5%, ± 1.0%, ± 1.5%, ± 0% in the IDAC 15b. The frequency (output frequency) of the clock SCLK is modulated to ± 0.5%, ± 1.0%, ± 1.5%, and ± 0%. As a result, the period of the generated modulation clock SCLK varies in a predetermined cycle, centering on a period M / N times the period of the reference clock RCLK.

Next, an example of the internal configuration of the phase comparator 20 will be described with reference to FIG.
As shown in FIG. 4, the phase comparator 20 includes two-input NANDs 21 to 23, a feedback circuit 24, a three-input AND 27, an inverter 28, and a two-input AND 30. The phase comparator 20 includes two-input NANDs 31 to 33, a feedback circuit 34, a three-input AND 37, an inverter 38, and a switch control circuit 39.

  A reference clock RCLK is input to the NAND 21 and an output signal of the three-input AND 27 is input via the inverter 28. The output signal of the NAND 21 is output to the NAND 22, the 2-input NAND 25 in the feedback circuit 24, and the 3-input AND 27.

  The NAND 22 outputs a result obtained by performing a NAND operation on the output signal of the NAND 21 and the output signal of the NAND 23 to the NAND 23, the NAND 25, and the 3-input AND 27. The NAND 23 outputs a result obtained by performing a NAND operation on the output signal of the NAND 22 and the output signal of the feedback circuit 24 to the NAND 22.

The feedback circuit 24 includes the two-input NAND 25, a delay circuit 26 having buffers 26a to 26c, and switches S1a to S4a.
The NAND 25 outputs a result obtained by performing a NAND operation on the output signals of the NANDs 21 and 22 to the buffer 26a and also to the three-input AND 27 through the switch S1a.

  The buffer 26a outputs a delayed signal obtained by delaying the output signal of the NAND 25 by a predetermined time to the next-stage buffer 26b and also to the three-input AND 27 via the switch S2a. The buffer 26b outputs a delayed signal obtained by further delaying the delayed signal from the preceding buffer 26a by a predetermined time to the next buffer 26c and also to the 3-input AND 27 via the switch S3a. The buffer 26c outputs a delay signal obtained by further delaying the delay signal from the preceding buffer 26b by a predetermined time to the 3-input AND 27 via the switch S4a.

  A switch control signal SC is supplied from the switch control circuit 39 to the control terminals of the switches S1a to S4a. The switches S1a to S4a are on / off controlled according to the switch control signal SC.

  The 3-input AND 27 performs an AND operation on the output signals of the NANDs 21 and 22 and the output signal of the feedback circuit 24. The output signal of the 3-input AND 27 is fed back to the NAND 21 via the inverter 28 and is output to the 2-input AND 30.

  The NAND 31 receives the modulation clock SCLK and the output signal of the three-input AND 37 via the inverter 38. The output signal of the NAND 31 is output to the NAND 32, the 2-input NAND 35 in the feedback circuit 34, and the 3-input AND 37.

  The NAND 32 outputs a NAND operation result of the output signal of the NAND 31 and the output signal of the NAND 33 to the NAND 33, the NAND 35, and the 3-input AND 37. The NAND 33 outputs a result obtained by performing a NAND operation on the output signal of the NAND 32 and the output signal of the feedback circuit 34 to the NAND 32.

The feedback circuit 34 includes the two-input NAND 35, a delay circuit 36 having buffers 36a to 36c, and switches S1b to S4b.
The NAND 35 outputs a result obtained by performing a NAND operation on the output signals of the NANDs 31 and 32 to the buffer 36a and also to the three-input AND 37 via the switch S1b.

  The buffer 36a outputs a delay signal obtained by delaying the output signal of the NAND 35 by a predetermined time to the next-stage buffer 36b and also to the 3-input AND 37 via the switch S2b. The buffer 36b outputs a delay signal obtained by further delaying the delay signal from the previous buffer 36a by a predetermined time to the next buffer 36c and also to the AND 37 via the switch S3b. The buffer 36c outputs a delay signal obtained by further delaying the delay signal from the preceding buffer 36b by a predetermined time to the three-input AND 37 via the switch S4b.

  A switch control signal SC is supplied from the switch control circuit 39 to the control terminals of the switches S1b to S4b. The switches S1b to S4b are on / off controlled according to the switch control signal SC. Here, the switch control circuit 39 switches on the switch control signal SC so as to turn on one of the switches S1a to S4a and one of the switches S1b to S4b based on a switch setting signal supplied from the outside. (See FIG. 5). Specifically, as shown in FIG. 5, when the switch setting signal that is a 2-bit signal is “00”, the switch control circuit 39 switches the switch control signal to turn on only the switch S4a and the switch S4b. Generate SC. The switch control circuit 39 turns on only the switches S3a and S3b when the switch setting signal is “01”, and turns on only the switches S2a and S2b when the switch setting signal is “10”. The switch control signal SC is generated so that the When the switch setting signal is “11”, the switch control circuit 39 generates the switch control signal SC so as to turn on only the switches S1a and S1b. Due to the on / off setting of the switches S1a to S4a and the switches S1b to S4b, the delay times of the delay circuits 26 and 36 are set, and the detection sensitivity of the phase comparator 20 is set. The detection sensitivity of the phase comparator 20, that is, the on / off settings of the switches S1a to S4a and S1b to S4b are set according to the modulation degree of the SSCG 10.

  As shown in FIG. 4, the 3-input AND 37 performs an AND operation on the output signals of the NANDs 31 and 32 and the output signal of the feedback circuit 34. The output signal of the 3-input AND 37 is fed back to the NAND 31 via the inverter 38 and is output to the 2-input AND 30.

  The 2-input AND 30 outputs a result obtained by performing an AND operation on the output signals of the 3-input ANDs 27 and 37 as a detection signal DS. Then, a lock signal LOCK having a predetermined pulse width is generated based on the H level detection signal DS.

  In the phase comparator 20 configured as described above, the 2-input NANDs 21 to 23, the 3-input AND 27 and the inverter 28 are included in the first flip-flop circuit, and the 2-input NANDs 31 to 33, the 3-input AND 37 and the inverter 38 are the second. Included in the flip-flop circuit. The output signals of the feedback circuits 24 and 34 function as signals that reset the internal state of the phase comparator 20 (first and second flip-flop circuits).

  Next, the operation of the clock generation circuit 1 configured as described above will be described with reference to FIGS. 6 and 7, the vertical axis and the horizontal axis are enlarged or reduced as appropriate for the sake of brevity.

First, the operation of the phase comparator 20 will be described with reference to FIG.
Before describing the actual phase comparison operation, the case where both the reference clock RCLK and the modulation clock SCLK are at the L level will be described.

  When both the reference clock RCLK and the modulation clock SCLK are at L level (time t1), the output signals of the NAND 21 and NAND 31 are both at H level. At this time, when the output signals of the NANDs 22 and 32 are at the L level, the output signals of the 3-input ANDs 27 and 37 are both at the L level. For this reason, the 2-input AND 30 outputs an L level detection signal DS. On the other hand, when the output signals of the NANDs 22 and 32 are at the H level, the output signals of the NANDs 25 and 35 are at the L level, and the output signals of the feedback circuits 24 and 34 are at the L level. Therefore, the output signals of the 3-input ANDs 27 and 37 become L level, and the output signal of the 2-input AND 30 becomes L level. Further, the output signals of the NANDs 23 and 33 to which the L level output signals are respectively input from the feedback circuits 24 and 34 become the H level. For this reason, the output signals of the NANDs 22 and 32 are at the L level.

  As described above, when both the reference clock RCLK and the modulation clock SCLK are at the L level, the L level output signal is output from the NANDs 22 and 32, and the L level detection signal DS is output from the 2-input AND 30. The

  Thereafter, when the reference clock RCLK becomes H level (time t2), the output signal of the NAND 21 becomes L level and the output signal of the NAND 22 becomes H level. When the modulation clock SCLK becomes H level (time t3), the output signal of the NAND 31 becomes L level and the output signal of the NAND 32 becomes H level.

  Next, an actual phase comparison operation will be described. First, as shown in FIG. 6, a case will be described in which the reference clock RCLK first falls and then the modulation clock SCLK falls after a predetermined time T1.

  First, when the reference clock RCLK falls, the output signal of the NAND 21 becomes H level in response to the fall. At this time, since the output signal of the NAND 22 and the output signal of the feedback circuit 24 are also at the H level, the output signal of the 3-input AND is at the H level.

  Further, when the output signal of the NAND 21 becomes H level, the output signal of the NAND 25 in the feedback circuit 24 changes from H level to L level. Thereafter, when the delay time T2 by the delay circuit 26 (buffers 26a to 26c) has elapsed, the output signal of the feedback circuit 24 transitions from the H level to the L level. Then, the output signal of the 3-input AND 27 changes from the H level to the L level. When an L level output signal is output from the feedback circuit 24, the output signal of the NAND 23 becomes H level, the output signal of the NAND 22 becomes L level, and the output signal of the NAND 25 transits from L level to H level. Thus, the NAND 25 outputs an L level output signal reflecting the delay time T2 from the delay circuit 26.

  On the other hand, when the modulation clock SCLK falls before the delay time T2 elapses after the output signal of the NAND 25 transitions to the L level (time t5), the output signal of the NAND 31 becomes H in response to the fall. Become a level. At this time, since the output signal of the NAND 32 and the output signal of the feedback circuit 34 are at the H level, the output signal of the 3-input AND 37 is at the H level. As a result, since the output signals of the three-input ANDs 27 and 37 are both at the H level, the detection signal DS at the H level is output from the two-input AND 30. Then, a lock signal LOCK having a predetermined pulse width is generated in response to the H level detection signal DS. That is, the phase comparator 20 in this case detects that the phases of the reference clock RCLK and the modulation clock SCLK are the same.

  Next, the case where the reference clock RCLK first falls and then the modulation clock SCLK falls after a predetermined time T3 (> T2) longer than the delay time T2 will be described. The operation caused by the falling edge of the reference clock RCLK is the same as the above-described operation, and thus detailed description thereof is omitted here.

  First, when the reference clock RCLK falls (time t6), in response to the fall, the output signal of the 3-input AND 27 changes from L level to H level, and the output signal of the NAND 25 changes from H level to L level. . Thereafter, when the delay time T2 by the delay circuit 26 elapses, the output signal of the feedback circuit 24 transitions from the H level to the L level, and accordingly, the output signal of the 3-input AND 27 transitions from the H level to the L level.

  Subsequently, when the modulation clock SCLK falls (time t7), the output signal of the 3-input AND 27 transitions from the L level to the H level in response to the fall. However, at this time, since the output signal of the 3-input AND 27 has already transitioned to the L level, the detection signal DS output from the 2-input AND 30 remains at the L level. For this reason, the lock signal LOCK is not generated. That is, the phase comparator 20 in this case detects that the phases of the reference clock RCLK and the modulation clock SCLK do not match.

  As described above, the phase comparator 20 is configured so that the time corresponding to the phase difference between the reference clock RCLK and the modulation clock SCLK (predetermined time T1 in the above example) is shorter than the delay time T2 by the delay circuit 26. It is detected that the phases of both clocks RCLK and SCLK are the same. Although not described here, the same applies to the case where the modulation clock SCLK falls first and then the reference clock RCLK falls. That is, in this case, the delay time T2 in the delay circuit 26 in the above description only changes to the delay time in the delay circuit 36.

  Here, when the on / off of the switches S1a to S4a is switched, the length of the delay time T2 changes and the detection sensitivity of the phase comparator 20 changes. More specifically, when only the switches S4a and S4b are turned on, the delay time T2 of the delay circuits 26 and 36 becomes the longest. For this reason, even if the phase difference between the reference clock RCLK and the modulation clock SCLK is large due to the longer delay time T2, it is detected that the phases of both the clocks RCLK and SCLK match. In other words, in this case, the detection accuracy when detecting the coincidence of the phases of both clocks RCLK and SCLK is the lowest, so the detection sensitivity of the phase comparator 20 is “minimum” (see FIG. 5). On the contrary, when only the switches S1a and S1b are turned on, the delay time T2 of the delay circuits 26 and 36 becomes the shortest. For this reason, in this case, unless the phase difference between the reference clock RCLK and the modulation clock SCLK is small, it is not detected that the phases of the two clocks RCLK and SCLK are the same. In other words, in this case, since the detection accuracy when detecting the coincidence of the phases of both clocks RCLK and SCLK is the highest, the detection accuracy of the phase comparator 20 is “maximum” (see FIG. 5). As described above, the detection accuracy of the phase comparator 20 is set according to the modulation degree of the SSCG 10.

Next, the operation of the entire clock generation circuit 1 will be described with reference to FIG.
As shown in FIG. 7, when the clock generation circuit 1 is activated (time t11), the phase comparator 20 outputs an L level detection signal DS because the phases of the reference clock RCLK and the modulation clock SCLK do not match. The Thereby, since the L level selection signal SEL is supplied to the selector 50, the selector 50 outputs the reference clock RCLK as the output clock CLK.

  After a while, the modulation clock SCLK is stably output (time t12). Subsequently, when the falling edges of the reference clock RCLK and the modulation clock SCLK coincide (time t13), the phase comparator 20 detects the coincidence of the phases and outputs the H level lock signal LOCK for a predetermined time. Thereafter, when the reference clock RCLK rises while the H-level lock signal LOCK is input, the D-FF circuit 40 outputs the H-level selection signal SEL in synchronization with the rising edge. In response to the H level selection signal SEL, the selector 50 switches the output clock CLK from the reference clock RCLK to the modulation clock SCLK. Thereafter, the modulation clock SCLK continues to be output as the output clock CLK.

According to this embodiment described above, the following effects can be obtained.
(1) When the clock generation circuit 1 is activated, the reference clock RCLK is selected as the output clock CLK. Thereby, a stable output clock CLK can be output immediately after the clock generation circuit 1 is started. That is, the lock-up time of the clock generation circuit 1 can be greatly shortened, and no waiting time is required until the modulation clock SCLK is stabilized. Accordingly, it is possible to suppress generation of useless current consumption during the standby time.

  (2) Here, when the reference clock RCLK and the modulation clock SCLK are simply switched, that is, when the reference clock RCLK and the modulation clock SCLK are switched at an arbitrary timing, the cycle-to-cycle (C-to-C) jitter increases. A new problem arises. On the other hand, in this embodiment, when the phase of the reference clock RCLK and the modulation clock SCLK coincide with each other, the reference clock RCLK is switched to the modulation clock SCLK. Thereby, since clock switching is performed when the phase difference between the reference clock RCLK and the modulation clock SCLK is small, it is possible to suitably suppress the occurrence of a hazard due to clock switching. Therefore, C-to-C jitter due to clock switching can be reduced.

  (3) The detection sensitivity of the phase comparator 20 is set according to the modulation degree of the SSCG 10. Thereby, C-to-C jitter due to clock switching can be suppressed according to the modulation degree of the SSCG 10.

(Second Embodiment)
The second embodiment will be described below with reference to FIGS. Hereinafter, the difference from the first embodiment will be mainly described. The same members as those shown in FIGS. 1 to 7 are denoted by the same reference numerals, and detailed description of these elements is omitted.

  As shown in FIG. 8, the clock generation circuit 1a includes an SSCG 10a, a phase comparator 20a, a D-FF circuit 40, and a selector 50. The clock generation circuit 1a is different from the first embodiment in that the setting signal Se is commonly supplied to the SSCG 10a and the phase comparator 20a. The setting signal Se is a signal supplied from the outside, for example.

  As shown in FIG. 9, in the SSCG 10a, the setting signal Se is supplied to the control circuit 17a. The control circuit 17a outputs a modulation signal corresponding to the setting signal Se to the IDAC 15b. That is, the control circuit 17a varies the current value in the IDAC 15b so that the modulation degree specified by the setting signal Se is obtained. In the phase comparator 20a, the setting signal Se is supplied to the switch control circuit 39 instead of the switch setting signal shown in FIG. Therefore, in the phase comparator 20a, the switches S1a to S4a and the switches S1b to S4b are set on / off based on the setting signal Se, that is, the detection sensitivity of the phase comparator 20a is set.

  Thus, in the clock generation circuit 1a of the present embodiment, the modulation degree of the SSCG 10a and the detection sensitivity of the phase comparator 20a are set by the common setting signal Se. Specifically, as shown in FIG. 10, when the setting signal Se that is a multi-bit signal (in this example, a 2-bit signal) is “00”, the modulation degree of the SSCG 10a is set to 3% (maximum). Set. When the setting signal Se is “00”, only the switches S4a and S4b are set to be turned on so that the detection sensitivity of the phase comparator 20a is “minimum”. In this case, when the phase difference between the reference clock RCLK and the modulation clock SCLK is smaller than “500 ps”, the phase comparator 20a detects that the phases of both the clocks RCLK and SCLK are the same.

  Similarly, when the setting signal Se is “01”, the modulation degree of the SSCG 10a is set to 2% and only the switches S3a and S3b are turned on so that the detection sensitivity of the phase comparator 20a is “low”. Set to When the setting signal Se is “10”, the modulation degree of the SSCG 10a is set to 1% and only the switches S2a and S2b are turned on so that the detection sensitivity of the phase comparator 20a is “medium”. Set as follows.

  When the setting signal Se is “11”, the SSCG 10a is set to no modulation (minimum), and only the switches S1a and S1b are turned on so that the detection sensitivity of the phase comparator 20a becomes “maximum”. Set as follows. In this case, the phase comparator 20a detects that the phases of the two clocks match until the phase difference between the reference clock RCLK and the modulation clock SCLK is “200 ps”.

According to this embodiment described above, in addition to the effects (1) to (3) of the first embodiment, the following effects can be obtained.
(4) The detection sensitivity of the phase comparator 20a is lowered as the modulation degree of the SSCG 10a increases (as the phase difference between the reference clock RCLK and the modulation clock SCLK increases). Thereby, since the detection sensitivity of the phase comparator 20a suitable for the modulation degree of the SSCG 10a can be set, C-to-C jitter due to clock switching can be more suitably suppressed.

  (5) The modulation degree of the SSCG 10a and the detection sensitivity of the phase comparator 20a are set by a common setting signal Se. Thereby, the detection sensitivity of the phase comparator 20a can be set and changed in conjunction with the setting change of the modulation degree of the SSCG 10a.

(Other embodiments)
In addition, the said embodiment can also be implemented in the following aspects which changed this suitably.
The setting signal Se of the second embodiment may be a signal supplied from, for example, an external terminal setting register. The setting signal Se may be adjustable in a programmable manner.

  The internal configuration of the phase comparators 20 and 20a in each of the above embodiments is particularly limited to the circuit configuration shown in FIG. 4 as long as it can detect that the phases of the reference clock RCLK and the modulation clock SCLK match. Not.

  The internal configuration of the SSCGs 10 and 10a in each of the above embodiments is a circuit configuration shown in FIGS. 2 and 9 as long as it is a clock generation circuit that receives the reference clock RCLK and performs spectrum spreading of the modulation clock SCLK according to the modulation signal. There are no particular restrictions.

  In the above embodiments, the enable terminal EN of the D-FF circuit 40 may be omitted, and the lock signal LOCK output from the phase comparators 20 and 20a may be supplied to the clock terminal of the D-FF circuit 40.

  In each of the above embodiments, the high potential side power supply voltage VDD is supplied to the input terminal D of the D-FF circuit 40 as a signal of a predetermined level, but the present invention is not limited to this.

1, 1a clock generation circuit 10, 10a spread spectrum clock generation circuit 20, 20a phase comparator 24, 34 feedback circuit 26, 36 delay circuit 40 D-flip flop circuit 50 selector (selection circuit)
RCLK Reference clock SCLK Modulation clock CLK Output clock (operation clock)
DS detection signal LOCK Lock signal (detection signal)

Claims (5)

A spread spectrum clock generation circuit that generates a modulation clock having a frequency modulated based on a reference clock; and
A phase comparator that outputs a detection signal when it is detected that the phase of the reference clock matches the phase of the modulation clock;
A selection circuit that selects the reference clock as an output clock until the detection signal is output, and selects the modulation clock as the output clock in response to the output of the detection signal;
A clock generation circuit comprising:   The clock generation circuit according to claim 1, wherein the detection sensitivity of the phase comparator is set to be lower as the modulation degree of the spread spectrum clock generation circuit is larger.   3. The clock generation circuit according to claim 2, wherein the detection sensitivity of the phase comparator is set based on a setting signal for setting a modulation factor of the spread spectrum clock generation circuit.   The phase comparator includes a feedback circuit that generates a signal that resets the internal state of the phase comparator, and controls the detection sensitivity of the phase comparator by controlling the delay amount of the delay circuit in the feedback circuit. The clock generation circuit according to claim 1, wherein:   5. The flip-flop circuit according to claim 1, further comprising a flip-flop circuit in which the detection signal is supplied to an enable terminal, the reference clock is supplied to a clock terminal, and a predetermined level signal is supplied to an input terminal. The clock generation circuit according to any one of the above.

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