JP2011061518A - Semiconductor integrated circuit and operating method of the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accurately suppress speed variations caused by a comparatively small supply voltage, and to speedily suppress speed variations caused by a comparatively large power supply voltage. <P>SOLUTION: A semiconductor integrated circuit includes first and second functional blocks MOD00, MOD01, a clock producing circuit PLL, and a clock supplying circuit CS0. First and second supply voltages VDD00, VDD01 whose voltage values are different form each other are supplied to the first and second functional blocks MOD00, MOD01. The MOD00 includes a first internal circuit BUF00 and a first logical circuit MFF00 capable of supplying one of the power supply voltage VDD01, and the MOD01 includes a second internal circuit BUF01 and a second logical circuit MFF01 capable of supplying the other of the supply voltage VDD00. The clock supply circuit CS0 includes a fine adjustment delay stage circuit FC0 and a rough adjustment delay stage circuit CC0, and a phase difference measuring circuit RSM0 while the RSM0 controls a delay time TF0 of the FC0 and a delay time TC0 of the CC0 according to a phase difference between first and second operation clock signals COUT00, COUT01. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit and a method for operating the same, and in particular, when realizing synchronization by reducing an operation speed difference inside a semiconductor chip, suppresses signal speed fluctuation caused by a relatively large power supply voltage fluctuation. Therefore, the present invention relates to a technique effective in reducing an increase in the chip occupation area and suppressing a speed fluctuation due to a relatively small fluctuation in power supply voltage with high accuracy.

  Since the power consumption of the transistor incorporated in the semiconductor integrated circuit is proportional to the square of the power supply voltage, it is effective to lower the power supply voltage in order to reduce power consumption. On the other hand, since the switching operation speed (operation frequency) of the transistor is substantially proportional to the power supply voltage, when the operation frequency of the logic circuit does not need to be high, reducing the power supply voltage and reducing the operation frequency is a semiconductor. This is an effective means for reducing power consumption in an integrated circuit. A technique for controlling the power supply voltage and the operating frequency in this way is known as a dynamic voltage frequency control technique (DVFS).

  Thus, although DVFS control is a very effective concept for reducing power consumption, there are various problems in mounting this technology on a semiconductor chip.

  As one of the problems, when DVFS control is performed in a part of a plurality of power supply regions inside the semiconductor chip, signal transmission between the DVFS control region and other power supply regions becomes a problem. Generally, when the power supply voltage changes, the operating frequency of the transistor changes substantially linearly as described above, while the signal propagation delay time of the transistor, which is the inverse of the operating frequency, changes in inverse proportion to the power supply voltage. Therefore, if the power supply voltage is changed by DVFS control, the operation speed of the DVFS control area and the operation speed of the DVFS non-control area are greatly different, and thus it is difficult to cope with the synchronization design that is generally used for signal transmission / reception. Become. In order to realize synchronization in such a situation, a technique for reducing the phase of the clock signal distributed to the DVFS control area and the clock signal distributed to the DVFS non-control area is important. As described above, the synchronization design can reduce the waiting time (latency) in signal transmission / reception, which is a disadvantage of the asynchronous design, and simplifies the signal transmission / reception protocol.

  Another problem in mounting DVFS control on a semiconductor chip is the problem of maintaining synchronization during power supply voltage change. Since the power supply voltage drive capability is often relatively small when changing the power supply voltage, it takes a very long time to change the power supply voltage. Therefore, if the synchronization during the power supply voltage change is not maintained, it is necessary to stop the operation during this period, resulting in a significant deterioration in processing performance.

  Non-Patent Document 1 and Non-Patent Document 2 below describe a dynamic deskewing system (DDS) as a technique for reducing the phase of the clock signal distributed to the DVFS control area and the clock signal distributed to the DVFS non-control area. Is described. A variable power supply voltage is supplied to the DVFS control area, while a fixed power supply voltage is supplied to the DVFS non-control area. A clock signal is directly supplied to the DVFS non-control area, while a delay clock delayed by a delay control circuit (DDC) is supplied to the DVFS control area. The delay control circuit (DDC) includes a first delay generation unit, a second delay generation unit, and a skew measurement unit, and the first feedback signal from the DVFS control region is directly supplied to the first input terminal of the skew measurement unit. On the other hand, the second feedback signal from the DVFS control region is supplied to the second input terminal of the skew measurement unit via the second delay generation unit. By controlling the delay amounts of the first and second delay generation units by the output signal of the skew measurement unit, the clock skew between the DVFS control area and the DVFS non-control area is reduced.

  On the other hand, the following Patent Document 1 describes a clock wiring device and a clock wiring method for realizing the clock signal phase reduction technology described in Non-Patent Document 1 and Non-Patent Document 2 described above.

  Patent Document 2 listed below describes a multi-power supply semiconductor device configured to compensate for a difference in delay amount due to power supply voltage fluctuation between a high threshold transistor block and a low threshold transistor block by a variable delay circuit. ing.

  Further, Patent Document 3 below describes that in a semiconductor integrated circuit adopting DVFS control, a difference in delay between a variable power supply voltage circuit block and a fixed power supply voltage circuit block is compensated by a phase comparison circuit and a variable delay circuit. ing. The phase of the clock signal supplied to the two blocks is detected by the phase comparison circuit, and the delay of the variable delay circuit that supplies the clock to the fixed power supply voltage circuit block is controlled according to the detection result, thereby compensating for the difference in clock delay. Is done.

  Patent Document 4 below discloses a semiconductor including a first power supply region supplied with a first power supply voltage and having a first clock wiring network and a second power supply region supplied with a second power supply voltage and having a second clock wiring network. In the integrated circuit, it is described that the phase of the reference clock, the clock signal at the end point of the first clock wiring network, and the clock signal at the end point of the second clock wiring network are matched. For this purpose, the phase of the reference clock and the end clock signal of the first clock wiring network are supplied to the first PLL circuit, while the phase of the reference clock and the end clock signal of the second clock wiring network are supplied to the second PLL circuit. The

  Further, Patent Document 5 described below describes a semiconductor device including first and second system modules, an internal power supply circuit, and a delay adjustment circuit. The first system module is supplied with the variable internal power supply voltage from the internal power supply circuit and the adjustable internal clock signal from the delay adjustment circuit. The second system module is directly supplied with the external power supply voltage and the external clock signal. The The delay adjustment circuit detects the amount of timing difference between the first and second clock signals supplied from the first and second system modules, and adjusts the delay of the internal clock signal.

  Patent Document 6 listed below describes a semiconductor integrated circuit including first and second cores, a clock generation circuit, and a power supply voltage supply circuit. A variable power supply voltage is supplied from the power supply voltage supply circuit to the first core, and an external power supply voltage is directly supplied to the second core. The clock generation circuit includes a PLL circuit, first and second buffers, and a selector, and a clock input signal is supplied to an input of the PLL circuit. The output clock of the PLL circuit is supplied to the second core that operates at an external power supply voltage of 1.25 V via the second buffer. On the other hand, when the first core operates at 1.00 V from the power supply voltage supply circuit, the output clock of the PLL circuit is directly supplied to the first core by the selection operation by the selector without passing through the first buffer. When the first core operates with an external power supply voltage of 1.25 V, the output clock of the PLL circuit is supplied to the first core via the first buffer by the selection operation by the selector. Here, the delay value of the first buffer is designed to be the same as the difference in propagation delay of the clock signal when the power supply voltage of the first core is changed from 1.00 V to 1.25 V.

JP 2006-293856 A International Publication No. 2005/008777 JP 2008-227397 A JP 2006-041129 A JP 2006-086455 A JP 2005-1000026 A

Toshihide Fujiyoshi et al, “A 63-mW H.264 / MPEG-4 Audio / Visual Codec LSI With Module—Wise Dynamic Voltage / Frequency Scaling”, IEIE LIFI OTE IJIT OLIIT 41, NO. 1, JANUARY 2006, PP. 54-62. Takeshi Kitahara et al, "Low-Power Design Methodology for Module -wise Dynamic Voltage and Frequency Scaling with Dynamic De-skewing Systems", 2006 IEEE Asia and South Pacific Conference on Design Automation, 5D-1, 24-27 Jan. 2006, PP. 533-540.

As described above, the control of the power supply voltage by the DVFS control is a very effective technique for reducing the power consumption of the semiconductor integrated circuit. However, not only the fluctuation of the power supply voltage due to DVFS control but also the fluctuation of the power supply voltage (switching ripple) caused by the switching operation of the switching power supply voltage regulator and the load state of the functional circuit block change suddenly inside the semiconductor chip. There is a power supply voltage fluctuation (load fluctuation ripple) due to. The voltage fluctuation duration and voltage fluctuation width in these three types of power supply voltage fluctuations generally differ greatly as follows.
(1) Power supply voltage fluctuation by DVFS control: fluctuation period is 1 MHz or less, fluctuation width is several hundred millivolts.
(2) Switching ripple: The fluctuation period is about 1 MHz or less, and the fluctuation width is several tens of millivolts.
(3) Load fluctuation ripple: The fluctuation period is 10 MHz to 100 MHz, and the fluctuation width is about 100 millivolts or less.

  The prior art described in Non-Patent Document 1 and Non-Patent Document 2 includes a plurality of stages of delay elements that measure the absolute value of the operating speed caused by power supply voltage fluctuations in order to measure the operating speed difference of the transistors. The propagation delay time per delay element determines the measurement accuracy of the operation speed difference and the adjustment accuracy of the delay amount. For example, if the propagation delay time per delay element is set to 5 picoseconds, Both the measurement accuracy and the delay adjustment accuracy are 5 picoseconds. On the other hand, when the difference in the operation speed of the transistors is 3 nanoseconds at the maximum, 600 delay elements are required at the minimum, and the chip occupation area of the operation speed measurement circuit is remarkably increased. Therefore, by using a delay element having a large propagation delay time, the number of delay element stages can be reduced and the chip occupation area of the measurement circuit can be reduced. However, the measurement accuracy and the adjustment accuracy of the delay amount are sacrificed. However, it has been clarified by studies by the present inventors. Furthermore, the present inventors have also studied the problem that it is difficult to suppress a relatively small difference in operating speed such as the switching ripple of (2) and the load fluctuation ripple of (3). It was made clear.

  The present invention has been made as a result of the examination by the present inventors prior to the present invention as described above.

  Therefore, an object of the present invention is to reduce the speed fluctuation of signal propagation caused by a relatively large fluctuation of the power supply voltage when reducing the operation speed difference inside the semiconductor chip and realizing the synchronization. The object is to reduce the increase of the occupied area and to suppress the speed fluctuation due to the relatively small fluctuation of the power supply voltage with high accuracy.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  A typical one of the inventions disclosed in the present application will be briefly described as follows.

  That is, the semiconductor integrated circuit (CHIP0) according to the representative embodiment of the present invention includes a first functional block (MOD00), a second functional block (MOD01), a clock generation circuit (PLL), and a clock supply circuit (CS0). ).

  A clock signal (CRIN0) is generated from the clock generation circuit (PLL).

  First and second power supply voltages (VDD00, VDD1) having different voltage values are supplied to the first functional block (MOD00) and the second functional block (MOD01).

  The first functional block (MOD00) includes a first internal circuit (BUF00) capable of supplying one power supply voltage (VDD01) of the first and second power supply voltages (VDD00, VDD1) and a first internal block (BUF00). Logic circuit (MFF00).

  The second functional block (MOD01) includes a second internal circuit (BUF01) capable of supplying the other power supply voltage (VDD00) of the first and second power supply voltages (VDD00, VDD1), and a second function block (MOD01). Logic circuit (MFF01).

  The clock signal (CRIN0) is supplied to the first functional block (MOD00) via the clock supply circuit (CS0) and the first internal circuit (BUF00) of the first functional block (MOD00). The signal is transmitted to the first logic circuit (MFF00) as a first operation clock signal (COUT00).

  The clock signal (CRIN0) is supplied to the second logic circuit (MFF01) of the second functional block (MOD01) through the second internal circuit (BUF01) of the second functional block (MOD01). Is transmitted as a second operation clock signal (COUNT01).

  The clock supply circuit (CS0) includes a fine delay stage circuit (FC0), a coarse delay stage circuit (CC0), and a phase difference measurement circuit (RSM0).

  The clock signal (CRIN0) is connected to the serial path of the fine delay stage circuit (FC0) and the coarse delay stage circuit (CC0) of the clock supply circuit (CS0) and the first function block (MOD00). The first operation clock signal (COUT00) can be transmitted to the first logic circuit (MFF00) of the first functional block (MOD00) via the first internal circuit (BUF00).

  The fine change width of the fine delay time (TF0) of the fine delay stage circuit (FC0) of the clock supply circuit (CS0) is the coarse delay of the coarse delay stage circuit (CC0) of the clock supply circuit (CS0). It can be set to a value smaller than the coarse adjustment range of time (TC0).

  The phase difference measuring circuit (RSM0) of the clock supply circuit (CS0) responds to the phase difference between the first operation clock signal (COUT00) and the second operation clock signal (COUT01). The fine delay time (TF0) of the delay stage circuit (FC0) and the coarse delay time (TC0) of the coarse delay circuit (CC0) can be controlled (see FIG. 1, see FIG.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to the present invention, when the synchronization is realized by reducing the operation speed difference in the semiconductor chip, the chip occupation area is reduced in order to suppress the speed fluctuation of the signal propagation caused by the relatively large power supply voltage fluctuation. It is possible to reduce the increase and to suppress the speed fluctuation due to the relatively small fluctuation of the power supply voltage with high accuracy.

FIG. 1 is a diagram showing a configuration of a semiconductor chip CHIP0 according to the first embodiment of the present invention. FIG. 2 is a diagram showing the configuration of the semiconductor chip CHIP0 according to the first embodiment of the present invention in more detail than FIG. FIG. 3 shows that when the second power supply voltage VDD01 changes by DVFS control in the semiconductor chip CHIP0 according to the first embodiment of the present invention shown in FIGS. 1 and 2, the clock synchronization circuit CS0 changes the fine delay stage circuit FC0. The propagation delay time TF0 of the first and second functional blocks MOD00 and MOD01 is controlled by controlling the propagation delay time TF0 of the first and second functional blocks MOD00 and MOD01 (TM00−TM01). It is a figure which annihilates the operation | movement which absorbs). FIG. 4 is a diagram showing how signals change in each part of the semiconductor chip CHIP0 according to the first embodiment of the present invention shown in FIG. 1 and FIG. FIG. 5 is a diagram for explaining the operation of the phase difference information decoder DEC0 of the delay control circuit DCTL0 of the coarse adjustment delay stage circuit CC0 of the semiconductor chip CHIP0 according to the first embodiment of the present invention shown in FIG. FIG. 6 is a diagram showing a configuration of the semiconductor chip CHIP0 according to the second embodiment of the present invention. FIG. 7 shows the propagation delay of the fine delay stage circuit FC0 when the second power supply voltage VDD01 changes by the DVFS control in the semiconductor chip CHIP0 according to the second embodiment of the present invention shown in FIG. Controls the time TF0 and the propagation delay time TC0 of the coarse delay stage circuit CC0 to absorb the difference (TM00-TM01) between the propagation delay times of the first and second functional blocks MOD00 and MOD01 and the clock buffers BUF00 and BUF01. FIG. FIG. 8 is a diagram showing a configuration of a semiconductor chip CHIP0 according to the third embodiment of the present invention. FIG. 9 shows the propagation delay of the fine delay stage circuit FC1 when the third power supply voltage VDD02 is changed by the DVFS control in the semiconductor chip CHIP0 according to the third embodiment of the present invention shown in FIG. By controlling the time TF1 and the propagation delay time TC1 of the coarse delay stage circuit CC1, the difference between the propagation delay times (TM01-TM02) of the clock buffers BUF01 and BUF02 in the second and third functional blocks MOD01 and MOD02 is absorbed. FIG.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. The reference numerals of the drawings referred to with parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A semiconductor integrated circuit (CHIP0) according to a representative embodiment of the present invention includes a first functional block (MOD00), a second functional block (MOD01), a clock generation circuit (PLL), a clock And a supply circuit (CS0).

  A clock signal (CRIN0) can be generated from the clock generation circuit (PLL).

  The first functional block (MOD00) and the second functional block (MOD01) can be supplied with first and second power supply voltages (VDD00, VDD1) having different voltage values.

  The first functional block (MOD00) includes a first internal circuit (BUF00) capable of supplying one power supply voltage (VDD01) of the first and second power supply voltages (VDD00, VDD1) and a first internal block (BUF00). Logic circuit (MFF00).

  The second functional block (MOD01) includes a second internal circuit (BUF01) capable of supplying the other power supply voltage (VDD00) of the first and second power supply voltages (VDD00, VDD1), and a second function block (MOD01). Logic circuit (MFF01).

  The clock signal (CRIN0) generated from the clock generation circuit (PLL) passes through the clock supply circuit (CS0) and the first internal circuit (BUF00) of the first functional block (MOD00). , And can be transmitted to the first logic circuit (MFF00) of the first functional block (MOD00) as a first operation clock signal (COUNT00).

  The clock signal (CRIN0) generated from the clock generation circuit (PLL) passes through the second function block (MOD01) via the second internal circuit (BUF01) of the second function block (MOD01). ) Can be transmitted to the second logic circuit (MFF01) as the second operation clock signal (COUNT01).

  The clock supply circuit (CS0) includes a fine delay stage circuit (FC0), a coarse delay stage circuit (CC0), and a phase difference measurement circuit (RSM0).

  The clock signal (CRIN0) generated from the clock generation circuit (PLL) is connected to the serial path of the fine delay stage circuit (FC0) and the coarse delay stage circuit (CC0) of the clock supply circuit (CS0) and the The first operation clock signal is sent to the first logic circuit (MFF00) of the first functional block (MOD00) via the first internal circuit (BUF00) of the first functional block (MOD00). Transmission is possible as (COUT00).

  The fine change width of the fine delay time (TF0) of the fine delay stage circuit (FC0) of the clock supply circuit (CS0) is the coarse delay of the coarse delay stage circuit (CC0) of the clock supply circuit (CS0). It can be set to a value smaller than the coarse adjustment range of time (TC0).

  The phase difference measuring circuit (RSM0) of the clock supply circuit (CS0) responds to the phase difference between the first operation clock signal (COUT00) and the second operation clock signal (COUT01). The fine delay time (TF0) of the delay stage circuit (FC0) and the coarse delay time (TC0) of the coarse delay circuit (CC0) can be controlled (see FIG. 1, see FIG.

  According to the embodiment, speed fluctuation due to a relatively small power supply voltage can be suppressed with high accuracy, and speed fluctuation due to a relatively large power supply voltage can be suppressed at high speed.

  In a preferred embodiment, when the one power supply voltage (VDD01) supplied to the first functional block (MOD00) is lowered, the first internal circuit (MOD01) of the first functional block (MOD00) is reduced. When the first propagation delay time (TM00) of BUF00) increases, the phase difference measurement circuit (RSM0) of the clock supply circuit (CS0) causes the fine delay stage circuit (FC0) of the clock supply circuit (CS0). ) Of the fine adjustment delay time (TF0) and the coarse adjustment delay stage circuit (CC0) of the coarse adjustment delay time (TC0) is reduced (see FIG. 3).

  In another preferred embodiment, the response speed of the change of the fine delay time (TF0) of the fine delay stage circuit (FC0) of the clock supply circuit (CS0) is the coarse speed of the clock supply circuit (CS0). It is possible to set a higher speed than the response speed for changing the coarse adjustment delay time (TC0) of the adjustment delay stage circuit (CC0).

  The clock supply circuit (CS0) further includes a differential shift circuit (DS0) connected between the phase difference measurement circuit (RSM0) and the fine delay stage circuit (FC0).

  The coarse delay stage circuit (CC0) of the clock synchronization circuit (CS0) notifies the phase shift information (UD0) of the previous cycle to the difference shift circuit (DS0).

  The difference shift circuit (DS0) subtracts the first phase difference information (RD0) in the current cycle supplied from the phase difference measurement circuit (RSM0) and the phase difference information (UD0) in the previous cycle. The calculation result delay amount control signal (FD0) is notified to the fine delay stage circuit (FC0) (see FIGS. 1 and 2).

  In a more preferred embodiment, the first internal circuit (BUF00) of the first functional block (MOD00) is connected to the first logic circuit (MFF00) of the first functional block (MOD00). A first clock buffer (BUF00) for transmitting the first operation clock signal (COUT00) is included.

  The second internal circuit (BUF01) of the second functional block (MOD01) sends the second operation clock signal (COUNT01) to the second logic circuit (MFF01) of the second functional block (MOD01). ) Is transmitted (see FIG. 1 and FIG. 2).

  In another more preferred embodiment, the first logic circuit (MFF00) of the first functional block (MOD00) receives the first operation clock transmitted from the first clock buffer (BUF00). It includes a first flip-flop (MFF00) to which a signal (COUT00) is supplied to the trigger input terminal.

  The second internal circuit (BUF01) of the second functional block (MOD01) supplies the second operation clock signal (COUNT01) transmitted from the second clock buffer (BUF01) to the trigger input terminal. The second flip-flop (MFF01) is included (see FIGS. 1 and 2).

  The semiconductor integrated circuit (CHIP0) according to a specific embodiment further includes a third functional block (MOD02) that can supply a third power supply voltage (VDD02).

  The third functional block (MOD02) includes a third internal circuit (BUF02) and a third logic circuit (MFF02) that can supply the third power supply voltage (VDD02).

  The clock signal (CRIN0) generated from the clock generation circuit (PLL) passes through the clock supply circuit (CS0) and the third internal circuit (BUF02) of the third functional block (MOD02). The third functional block (MOD02) can be transmitted to the third logic circuit (MFF02) as a third operation clock signal (COUNT02).

  The clock supply circuit (CS0) further includes another fine delay stage circuit (FC1), another coarse delay stage circuit (CC1), and another phase difference measurement circuit (RSM1).

  The clock signal (CRIN0) generated from the clock generation circuit (PLL) is supplied from the other fine delay stage circuit (FC1) of the clock supply circuit (CS0) and the other coarse delay stage circuit (CC1). The third logic circuit (MFF02) of the third functional block (MOD02) is connected to the third logic circuit (MFF02) of the third functional block (MOD02) via a serial path and the third internal circuit (BUF02) of the third functional block (MOD02). The operation clock signal (COUT02) can be transmitted.

  The fine change width of the fine adjustment delay time (TF1) of the other fine adjustment delay stage circuit (FC1) of the clock supply circuit (CS0) is the other coarse adjustment delay stage circuit (CC1) of the clock supply circuit (CS0). The coarse adjustment delay time (TC1) can be set to a value smaller than the coarse adjustment change width.

  The other phase difference measurement circuit (RSM1) of the clock supply circuit (CS0) is responsive to the phase difference between the second operation clock signal (COUNT01) and the third operation clock signal (COUNT02). The fine delay time (TF1) of the other fine delay stage circuit (FC1) and the coarse delay time (TC1) of the other coarse delay stage circuit (CC1) can be controlled. (See FIG. 8).

  In a more specific embodiment, the third power supply voltage (VDD02) supplied to the third functional block (MOD02) increases to increase the third functional block (MOD02). When the third propagation delay time (TM02) of the internal circuit (BUF02) is increased, the other phase difference measuring circuit (RSM1) of the clock supply circuit (CS0) is changed to the other of the clock supply circuit (CS0). A total delay time of the fine delay time (TF1) of the fine delay stage circuit (FC1) and the coarse delay time (TC1) of the other coarse delay stage circuit (CC1) is reduced. (See FIG. 9).

  In another more specific embodiment, the response speed of changing the fine delay time (TF1) of the other fine delay stage circuit (FC1) of the clock supply circuit (CS0) is the clock supply circuit (CS0). ) Can be set faster than the response speed of the change of the coarse delay time (TC1) of the other coarse delay stage circuit (CC1).

  The clock supply circuit (CS0) further includes another differential shift circuit (DS1) connected between the other phase difference measurement circuit (RSM1) and the other fine delay stage circuit (FC1).

  The other coarse delay stage circuit (CC1) of the clock synchronization circuit (CS0) notifies the other differential shift circuit (DS1) of other phase difference information (UD1) of the previous cycle.

  The other differential shift circuit (DS1) includes second phase difference information (RD1) in the current cycle supplied from the other phase difference measurement circuit (RSM1) and the other phase difference information in the previous cycle ( The other delay amount control signal (FD1) resulting from the subtraction operation with UD1) is notified to the other fine delay stage circuit (FC1) (see FIG. 9).

  In the most specific embodiment, the first functional block (MOD00), the second functional block (MOD1), the third functional block (MOD02), and the clock generation circuit (PLL) The clock supply circuit (CS0) is constituted by a CMOS circuit.

  [2] A representative embodiment according to another aspect of the present invention includes a first functional block (MOD00), a second functional block (MOD01), a clock generation circuit (PLL), and a clock supply circuit ( CS0) and a semiconductor integrated circuit (CHIP0). This operation method has the following steps.

  Generating a clock signal (CRIN0) by the clock generation circuit (PLL);

  Supplying first and second power supply voltages (VDD00, VDD1) having different voltage values to the first functional block (MOD00) and the second functional block (MOD01);

  The clock signal (CRIN0) generated from the clock generation circuit (PLL) is supplied to the clock supply circuit (CS0) and the first internal circuit (BUF00) included in the first functional block (MOD00). And transmitting to the first logic circuit (MFF00) included in the first functional block (MOD00) as the first operation clock signal (COUT00).

  The clock signal (CRIN0) generated from the clock generation circuit (PLL) is transferred to the second functional block (BUF01) via the second internal circuit (BUF01) included in the second functional block (MOD01). (MOD01) is transmitted to the second logic circuit (MFF01) as the second operation clock signal (COUNT01).

  The clock signal (CRIN0) generated from the clock generation circuit (PLL) is connected to a series path of a fine delay stage circuit (FC0) and a coarse delay stage circuit (CC0) included in the clock supply circuit (CS0), and The first operation clock signal is sent to the first logic circuit (MFF00) of the first functional block (MOD00) via the first internal circuit (BUF00) of the first functional block (MOD00). Transmitting as (COUNT00).

  The fine change width of the fine delay time (TF0) of the fine delay stage circuit (FC0) of the clock supply circuit (CS0) is set as the coarse delay of the coarse delay stage circuit (CC0) of the clock supply circuit (CS0). A step of setting to a value smaller than the coarse tone change width of time (TC0).

  The phase difference measurement circuit (RSM0) included in the clock supply circuit (CS0) responds to the phase difference between the first operation clock signal (COUT00) and the second operation clock signal (COUT01). Controlling the fine delay time (TF0) of the fine delay circuit (FC0) and the coarse delay time (TC0) of the coarse delay circuit (CC0).

  One of the first and second power supply voltages (VDD00, VDD1) is supplied to the first internal circuit (BUF00) and the first logic circuit (MFF00) of the first functional block (MOD00). A power supply voltage (VDD01) can be supplied.

  The second internal circuit (BUF01) and the second logic circuit (MFF01) of the second functional block (MOD01) have the other one of the first and second power supply voltages (VDD00, VDD1). The power supply voltage (VDD00) can be supplied (see FIGS. 1 and 2).

  According to the embodiment, speed fluctuation due to a relatively small power supply voltage can be suppressed with high accuracy, and speed fluctuation due to a relatively large power supply voltage can be suppressed at high speed.

2. Details of Embodiment Next, the embodiment will be described in more detail. In all the drawings for explaining the best mode for carrying out the invention, components having the same functions as those in the above-mentioned drawings are denoted by the same reference numerals, and repeated description thereof is omitted.

[Embodiment 1]
<Structure of semiconductor chip>
FIG. 1 is a diagram showing a configuration of a semiconductor chip CHIP0 according to the first embodiment of the present invention.

  The semiconductor CHIP0 includes a phase synchronization circuit (phase locked loop) PLL, a clock synchronization circuit CS0, and first and second functional blocks MOD00 and MOD01. Further, the clock synchronization circuit CS0 includes a fine delay stage circuit FC0, a coarse delay stage circuit CC0, a differential shift circuit DS0, and a relative phase difference measurement circuit RSM0. Note that each of the phase synchronization circuit PLL, the clock synchronization circuit CS0, and the first and second functional blocks MOD00 and MOD01 incorporated in the semiconductor CHIP0 includes an N-channel MOS transistor and a P-channel MOS transistor, respectively. It is constituted by a CMOS circuit.

<Clock synchronization circuit>
The clock signal CRIN0 generated by the phase synchronization circuit PLL is directly supplied to the fine delay stage circuit FC0 and the second functional block MOD01 of the clock synchronization circuit CS0. The clock signal CRIN0 supplied to the clock synchronization circuit CS0 is delayed by the fine delay stage circuit FC0 having the delay time TF0, and the fine delay output clock signal CFC0 generated from the output of the fine delay stage circuit FC0 is the coarse delay stage circuit CC0. To be supplied. The delay time TF0 of the fine delay stage circuit FC0 can be specified by the delay amount control signal FD0 supplied from the differential shift circuit DS0 to the fine delay stage circuit FC0.

  The fine delay output clock signal CFC0 is delayed by the coarse delay stage circuit CC0 having the delay time TC0, and the coarse delay output clock signal CIN00 generated from the output of the coarse delay stage circuit CC0 is supplied to the first functional block MOD00. Supplied. The delay time TC0 of the coarse delay stage circuit CC0 can be specified by the phase difference information RS supplied from the relative phase difference measurement circuit RSM0 to the coarse delay stage circuit CC0.

《Function block》
In the first functional block MOD00, the first clock signal CIN00 generated from the output of the coarse adjustment delay stage circuit CC0 of the clock synchronization circuit CS0 is transmitted to the first propagation delay time TM00 by the plurality of first buffers BUF00. Is supplied to the trigger input terminal of the flip-flop MFF00. Note that the first propagation delay time TM00 of the plurality of first buffers BUF00 is inversely proportional to the voltage value of the second power supply voltage VDD01 supplied to the first functional block MOD00.

  Inside the second functional block MOD01, after the delay of the second propagation delay time TM01 in the plurality of second buffers BUF01, the clock signal CRIN0 generated by the phase synchronization circuit PLL is used as the second clock signal CIN01. It is supplied to the trigger input terminal of the flip-flop MFF01. The second propagation delay time TM01 of the plurality of second buffers BUF01 is inversely proportional to the voltage value of the first power supply voltage VDD00 supplied to the second functional block MOD01.

<< Dynamic control of power supply voltage >>
There are two types of power supply voltages supplied to the semiconductor chip CHIP0, the first power supply voltage VDD00 and the second power supply voltage VDD01. While the voltage of the first power supply voltage VDD00 is fixed, the processing load of the functional block ( The voltage of the second power supply voltage VDD01 is dynamically controlled by (DVFS control). Here, assuming that the processing load of the first functional block MOD00 varies greatly depending on the application, the variable second power supply voltage VDD01 is supplied to the first functional block MOD00, and the other circuit portion is a clock. A fixed first power supply voltage VDD00 is supplied to the synchronization circuit CS0 and the second functional block MOD01.

<Reducing clock phase difference>
Since the fixed first power supply voltage VDD00 is supplied to the second functional block MOD01, the second propagation delay times TM01 of the plurality of second buffers BUF01 in the second functional block MOD01 are substantially constant. On the other hand, since the second power supply voltage VDD01 that is dynamically controlled is supplied to the first functional block MOD00, the first buffers BUF00 of the plurality of first buffers BUF00 inside the first functional block MOD00 are supplied. The propagation delay time TM00 of 1 changes dynamically. However, in the semiconductor chip CHIP0 according to the first embodiment of the present invention shown in FIG. 1, the first and second supplied to the flip-flops MFF00 and MFF01 inside the first and second functional blocks MOD00 and MOD01. The fine delay stage circuit FC0 and the coarse delay stage circuit CC0 of the clock synchronization circuit CS0 absorb the time difference between the first and second propagation delay times TM00 and TM01 so that the phase difference from the clock signals COUT00 and COUT01 of the clock does not fluctuate. To do. For example, when the second power supply voltage VDD01 supplied to the first functional block MOD00 decreases and the first propagation delay times TM00 of the plurality of first buffers BUF00 in the first functional block MOD00 increase, the clock The total delay time of the delay time TF0 of the fine adjustment delay stage circuit FC0 of the synchronization circuit CS0 and the delay time TC0 of the coarse adjustment delay stage circuit CC0 decreases.

  In order to control the total delay time of the clock synchronization circuit CS0, the first and second clock signals COUT00 and COUT01 supplied to the flip-flops MFF00 and MFF01 in the first and second functional blocks MOD00 and MOD01 The phase difference is measured. That is, after the delay of the first propagation delay time TM00, the second clock after the delay of the first clock signal COUT00 and the second propagation delay time TM01 supplied to the flip-flop MFF00 in the first functional block MOD00. The second clock signal COUT01 supplied to the flip-flop MFF01 inside the functional block MOD01 is supplied to the relative phase difference measurement circuit RSM0. Accordingly, the first and second phase difference information RD and RS indicating the phase difference between the first clock signal COUT00 and the second clock signal COUT01 are generated from the output of the relative phase difference measurement circuit RSM0.

  The second phase difference information RS is supplied to the coarse delay stage circuit CC0, so that the delay time TC0 of the coarse delay stage circuit CC0 is set. The information of the first phase difference information RD is supplied to the fine delay stage circuit FC0 via the difference shift circuit DS0, thereby setting the delay time TF0 of the fine delay stage circuit FC0.

  The fine change width of the delay time TF0 of the fine adjustment delay stage circuit FC0 is smaller than the coarse adjustment change width of the delay time TC0 of the coarse adjustment delay stage circuit CC0. Further, the response speed of the delay time TF0 of the fine delay stage circuit FC0 is faster than the response speed of the delay time TC0 of the coarse delay stage circuit CC0. That is, the change of the delay time TF0 of the fine delay stage circuit FC0 is completed at the elapsed time of one cycle of the clock signal CRIN0, whereas the change of the delay time TC0 of the coarse delay stage circuit CC0 is 2 Elapsed time longer than the cycle is required.

  As described above, the first and second phase difference information RD and RS are generated from the output of the relative phase difference measurement circuit RSM0. In the fine delay stage circuit FC0, the delay time TF0 is changed after one cycle. In the coarse delay stage circuit CC0, the delay time TC0 is changed after two cycles, so that there is a difference in delay control latency between the fine delay stage circuit FC0 and the coarse delay stage circuit CC0. In such a case, the first phase difference information RD is directly used at the timing for controlling the delay time TC0 of the coarse adjustment delay stage circuit CC0 using the second phase difference information RS. When the delay amount TF0 is controlled, the coarse adjustment delay stage circuit CC0 is changed based on the second phase difference information RS of the previous cycle at the same timing as the same cycle. As a result, the phase difference between the first and second clock signals COUT00 and COUT01 supplied to the flip-flops MFF00 and MFF01 in the first and second functional blocks MOD00 and MOD01 is the fine delay stage of the clock synchronization circuit CS0. As a result, the clock jitter of the first clock signal CIN00 supplied to the first functional block MOD00 increases unnecessarily by the circuit FC0 and the coarse delay stage circuit CC0.

  Therefore, in the semiconductor chip CHIP0 according to the first embodiment of the present invention shown in FIG. 1, the coarse delay stage circuit CC0 of the clock synchronization circuit CS0 finely adjusts the phase difference information UD0 of the previous cycle with the relative phase difference measurement circuit RSM0. The difference shift circuit DS0 connected to the delay stage circuit FC0 is notified. Then, the differential shift circuit DS0 notifies the fine delay stage circuit FC0 of the delay amount control signal FD0 that is the calculation result of the subtraction of the phase difference information UD0 of the previous cycle from the first phase difference information RD in the current cycle. is there. That is, the delay change amount UD0 in the next cycle is notified from the coarse delay stage circuit CC0 having a large number of cycles necessary for changing the delay amount to the fine delay stage circuit FC0 having a small number of cycles necessary for changing the delay amount. By controlling the delay amount TF0 of the fine delay stage circuit FC0 by the net phase difference information FD0 obtained by subtracting the delay change amount UD0 from the phase difference information RD, an unnecessary increase in clock jitter is suppressed.

  As described above, the fine-adjustment delay stage circuit FC0 capable of controlling the amount of delay in the elapsed time of one cycle with a small fine-adjustment range of the delay time TF0 and the coarse-adjustment change width of the delay time TC0 is large and the elapsed time of two cycles. In addition, the coarse delay stage circuit CC0 capable of controlling the delay amount is combined, and the phase difference information UD0 in the previous clock cycle is notified from the coarse delay stage circuit CC0 to the fine delay stage circuit FC0 to absorb the difference delay amount. By controlling the fine delay stage circuit FC0 so that the synchronization is maintained, the synchronization between the functional blocks during the power supply voltage change can be realized with a small area and high accuracy.

<Detailed configuration of semiconductor chip>
FIG. 2 is a diagram showing the configuration of the semiconductor chip CHIP0 according to the first embodiment of the present invention in more detail than FIG.

  As shown in FIG. 2, the semiconductor CHIP0 includes a phase synchronization circuit PLL, a clock synchronization circuit CS0, and first and second functional blocks MOD00 and MOD01. Further, the clock synchronization circuit CS0 includes a fine delay stage circuit FC0, a coarse delay stage circuit CC0, a differential shift circuit DS0, and a relative phase difference measurement circuit RSM0.

  The fine adjustment delay stage circuit FC0 includes n unit fine adjustment delay stages FU00 to FU0n-1 and n path changeover switches SWF00 to SWF0n-1.

  The differential shift circuit DS0 includes a shift type switch SS0.

  The relative phase difference measurement circuit RSM0 includes 2n unit fine delay stages FUM00 to FUM0n-1, FUD00 to FUD0n-1, n path changeover switches SWM00 to SWM0n-1, phase difference information decoders RDEC00 to RDEC0n-1, n The flip-flops FFM00 to FFM0n-1 and two level shifters LS00 and LS01 are included.

  The coarse delay stage circuit CC0 includes one variable delay stage VU0, m coarse delay stages CU00 to CU0m-1, m path changeover switches SWC00 to SWC0m-1, and a delay control circuit DCTL0. The delay control circuit DCTL0 includes a variable delay stage control circuit VCTL0, a coarse delay stage control circuit CCTL0, a phase difference information decoder DEC0, p flip-flops FF0, and a subtraction circuit ABS0.

  The first and second functional blocks MOD00 and MOD01 are composed of clock buffers BUF00 and BUF01, and flip-flops MFF00 and MFF01. In FIG. 2, only a few clock buffers BUF00 and BUF01, and flip-flops MFF00 and MFF01 are shown for convenience, but any number of clock buffers BUF00 and BUF01 may be used.

  Here, the fine delay stage FU00 to FU0n-1 of the fine delay stage circuit FC0 and the unit fine delay stages FUM00 to FUM0n-1 and FUD00 to FUD0n-1 of the relative phase difference measuring circuit RSM0 are the propagation delay time per stage. It is configured with a capacity such as a high-speed buffer and a small capacitor so as to be sufficiently small. On the other hand, in the coarse delay stage circuit CC0, the variable delay stage VU0 is variably controlled by the control signal VFD0 of the variable delay stage control circuit VCTL0 with the propagation delay time per fine delay stage as the minimum unit. Further, in the coarse delay stage circuit CC0, m coarse delay stages CU00 to CU0m-1 controlled by the carry signal CR0 and the carry signal CB0 supplied to the coarse delay stage control block CCTL0 and m The delay time TC0 is controlled by the path switch SWC00 to SWC0m-1.

  The clock signal CRIN0 generated from the phase synchronization circuit PLL is supplied to the fine delay stage circuit FC0 and the second functional block MOD01. The clock signal CRIN0 supplied to the fine delay stage circuit FC0 is delayed by the delay time TF0 designated by the delay amount control signals FD00 to FD0n-1 from the differential shift circuit DS0, and the delayed clock signal CFC0 is coarsely delayed stage circuit CC0. To be supplied. The clock signal CFC0 supplied to the coarse adjustment delay stage circuit CC0 is delayed by the delay time TC0 specified by the delay amount information UD0, CR0, BR0, and the delayed clock signal CIN00 is supplied to the first functional block MOD00.

The first delay amount information UD0 is a decoding result of the second phase difference information RS00 to RS0n-1 by the phase difference information decoder DEC0, and controls the delay amount of the variable delay stage VU0. That is, the delay amount of the variable delay stage VU0 is variably controlled by the control signal VFD0 generated from the variable delay stage control circuit VCTL0 that responds to the delay amount information UD0. The next delay amount information CR0 and BR0 are also the decoding results of the phase difference information decoder DEC0, but when the delay amount of the variable delay stage VU0 is greater than or equal to the maximum delay amount 2p ^-1 or less than the minimum delay amount 0. This is the carry-up signal CR0 or the carry-down signal BR0 of the coarse delay stage circuit CC0 generated at the same time. In response to the carry signal CR0 or the carry signal BR0 from the phase difference information decoder DEC0, the delay control signals CD00 to CD0m-1 of the coarse adjustment delay stage control circuit CCTL0 change, and m coarse adjustment delay stages CU00 to CU00. The number of serial delay stages composed of CU0m-1 and m path switching switches SWC00 to SWC0m-1 is controlled.

  The delayed clock signal CIN00 generated from the coarse adjustment delay stage circuit CC0 is supplied to the first functional block MOD00. After this supply, the time required for the delayed clock signal CIN00 to propagate through the plurality of first buffers BUF00 in the first functional block MOD00 and reach the flip-flop MFF00 is a propagation delay time TM00.

  On the other hand, the clock signal CRIN00 generated from the phase synchronization circuit PLL is also supplied to the second functional block MOD01. After this supply, the time required for the clock signal CRIN00 to propagate through the plurality of first buffers BUF00BUF01 inside the second functional block MOD01 and reach the flip-flop MFF01 is a propagation delay time TM01. The first and second clock signals COUT00 and COUT01 supplied to the flip-flops MFF00 and MFF01 in the first and second functional blocks MOD00 and MOD01, respectively, are supplied to the relative phase difference measurement circuit RSM0, and the relative phase difference measurement circuit The first phase difference information RD00 to RD0n-1 and the second phase difference information RS00 to RS0n-1 are supplied from the RSM0 to the differential shift circuit DS0 and the coarse delay stage circuit CC0, respectively. In response to the delay amount information UD0 that is the result of decoding by the phase difference information decoder DEC0 of the second phase difference information RS00 to RS0n-1, the p flip-flops FF0 and the subtraction circuit ABS0 of the coarse delay stage circuit CC0 Notifies the difference shift circuit DS0 of the phase difference information SP0 between the previous clock cycle and the current clock cycle.

  Next, the clock synchronization circuit CS0 controls the propagation delay time TF0 of the fine adjustment delay stage circuit FC0 and the propagation delay time TC0 of the coarse adjustment delay stage circuit CC0, and the clocks inside the first and second functional blocks MOD00 and MOD01 The operation of each part of the clock synchronization circuit CS0 when absorbing the difference (TM00-TM01) in the propagation delay time between the buffers BUF00 and BUF01 will be described.

  First, the difference in propagation delay time in the current cycle ((TF0 + TC0 + TM00) −TM01) is measured by the relative phase difference measuring circuit RSM0. The first phase difference information RD00 to RD0n-1 and the second phase difference information RS00 to RS0n-1 as phase difference information, which are measurement results, are notified to the difference shift circuit DS0 and the phase difference information decoder DEC0.

  Here, in the second phase difference information RS00 to RS0n-1, the number of high levels from the RS00 side that is the LSB signal indicates the phase difference toward RS0n-1 that is the MSB signal. The signal of the first phase difference information RD00 to RD0n-1 is at the high level at the change point between the high level and the low level of the second phase difference information RS00 to RS0n-1, and all the signals are at the low level at other points. Become. The first phase difference information RD00 to RD0n-1 is corrected by the phase difference information SP0 for absorbing the difference in control latency as described above in the difference shift circuit DS0, and new phase difference information FD00 to FD0n- 1 controls the delay amount TF0 of the fine delay stage circuit FC0.

On the other hand, the phase difference information decoder DEC0 in the coarse delay stage circuit CC0 to which the second phase difference information RS00 to RS0n-1 is supplied is the high level and the low level of the second phase difference information RS00 to RS0n-1. The delay amount of the variable delay stage VU0 of the coarse adjustment delay stage circuit CC0 is controlled by the p-bit control signal UD0 so that the change point is exactly the center of the second phase difference information RS00 to RS0n-1. At this time, if the delay amount of the variable delay stage VU0 is not less than the maximum delay amount 2p ^-1 or not more than the minimum delay amount 0, the carry signal CR0 or the carry signal BR0 of the coarse delay stage circuit CC0. Is controlled to a high level, and the number of coarse delay stage circuits CC0 is increased by one or decreased by one. The variable delay stage control circuit VCTL0 is configured by a p-1 bit counter or the like that can be arbitrarily increased or decreased so that the delay amount of the variable delay stage VU0 can be controlled with 2 ^p-1 gradations. The coarse delay stage control circuit CCTL0 includes a shift register or the like so that the number of coarse delay stages CC0 can be increased or decreased by one stage. The differential shift circuit DS0 to which the phase difference information SP0 is supplied from the delay control circuit DCTL0 is a correction position in which the first phase difference information RD00 to RD0n-1 is right-shifted or left-shifted by the number of bits notified by the phase difference information SP0. The phase difference information FD00 to FD0n-1 is supplied to the fine delay stage circuit FC0.

  The relative phase difference measurement circuit RSM0 is provided with two level shifters LS00 and LS01. The first level shifter LS00 is added because the amplitude of the clock signal COUT00 supplied to the first functional module MOD00 is changed by DVFS control. The next level shifter LS01 is added to suppress the phase error of the clock signal due to the addition of the first level shifter LS00.

<< Absorption of delay time difference due to power fluctuation >>
FIG. 3 shows that when the second power supply voltage VDD01 changes by DVFS control in the semiconductor chip CHIP0 according to the first embodiment of the present invention shown in FIGS. 1 and 2, the clock synchronization circuit CS0 changes the fine delay stage circuit FC0. The propagation delay time TF0 of the first and second functional blocks MOD00 and MOD01 is controlled by controlling the propagation delay time TF0 of the first and second functional blocks MOD00 and MOD01 (TM00−TM01). It is a figure which annihilates the operation | movement which absorbs).

  As shown in FIG. 3A, in the second power supply voltage VDD01 supplied to the first functional block MOD00, a switching ripple is generated in the entire period TRIP_VR0, and it oscillates around the voltage V1 until time T0. In addition, after time T2, it vibrates with an amplitude of several tens of millivolts around the voltage V2. Further, assuming that the processing load of the first functional block MOD00 becomes a light load at the time T0 as a boundary, a load fluctuation ripple occurs at the time T0 to T1 (period TRIP_WC0), and the second power supply voltage VDD01 is The voltage increases rapidly from V1 to voltage V0. At subsequent times T1 to T2 (period TDVFS0), the change of the second power supply voltage VDD01 by the DVFS control is executed, and the second power supply voltage VDD01 gradually drops from the voltage V0 to the voltage V2.

  On the other hand, as shown in FIG. 3C, in the first power supply voltage VDD00 supplied to the second functional block MOD01, only the switching ripple occurs in the entire period (period TRIP_VR0), and the first power supply voltage VDD00 vibrates at several tens of millivolts around the voltage V3.

  FIG. 3B shows a fine delay stage circuit for the first functional block MOD00 when the second power supply voltage VDD01 supplied to the first functional block MOD00 changes as shown in FIG. It is a figure which shows the mode of change of propagation delay time TF0 of FC0, propagation delay time TC0 of coarse adjustment delay stage circuit CC0, and propagation delay time TM00 of clock buffer BUF00.

  As understood from FIG. 3B, when the second power supply voltage VDD01 decreases as shown in FIG. 3A, the propagation delay time TM00 of the clock buffer BUF00 of the first functional block MOD00 increases. Inversely, the total delay time of the propagation delay time TF0 of the fine delay stage circuit FC0 and the propagation delay time TC0 of the coarse delay stage circuit CC0 is reduced by the operation of the clock synchronization circuit CS0.

  On the other hand, as can be understood from FIG. 3D, the first power supply voltage VDD00 supplied to the second functional block MOD01 is substantially constant voltage V3 as shown in FIG. The propagation delay time TM01 of the clock buffer BUF01 of the functional block MOD01 is also maintained at a substantially constant delay amount.

  As a result, the clock synchronization circuit CS0 is finely adjusted so that the relationship TM00 + TC0 + TF0 = TM01 always holds between the total propagation delay time TM00 + TC0 + TF0 of the first functional block MOD00 and the total propagation delay time TM01 of the second functional block MOD01. It is understood that the total delay time of the propagation delay time TF0 of the delay stage circuit FC0 and the propagation delay time TC0 of the coarse adjustment delay stage circuit CC0 is dynamically controlled. In this way, even if the second power supply voltage VDD01 supplied to the first functional block MOD00 changes, the first and second functional blocks MOD00 and MOD01 are supplied to the flip-flops MFF00 and MFF01 in the MOD01, respectively. It can be understood that the relative phase difference between the first and second clock signals COUT00 and COUT01 is reduced.

  FIG. 4 is a diagram showing how signals change in each part of the semiconductor chip CHIP0 according to the first embodiment of the present invention shown in FIG. 1 and FIG.

  In the example of FIG. 4, it is assumed that the number n of the fine adjustment delay stage circuit FC0 is n = 16, and the number p of the flip-flops FF0 connected to the phase difference information decoder DEC0 of the delay control circuit DCTL0 is p = 4. The number of stages m of the delay stage circuit CC is 51. However, these variables can be any integer of 1 or more. However, if the number of stages n and the number p are set to a relationship of 2p = n, the numerical value of the phase difference information UD is advantageously reduced.

  In FIG. 4, the phases of the clock signals COUT00 and COUT01 are compared, and as a result, the first and second phase difference information RD0 and RS0 and the phase difference information UD0 change.

  In the example of FIG. 4, since there is no phase difference between the clock signals COUT00 and COUT01 at time T0, the first and second phase difference information RD0 and RS0 remain in the initial state as RD0 = 16′b00000000_10000000 and RS0 = 16′b11111111_00000000. Therefore, the phase difference information UD0 = 0 of the decoding result of the phase difference information decoder DEC0 (the propagation delay time TC0 of the coarse adjustment delay stage circuit CC0 is not changed).

  However, in the subsequent phase comparison of the clock signals COUT00 and COUT01, the rising edge of the clock signal COUT01 is T1, T6, T10, and the rising time of the clock signal COUT01 is T1, T6, T10, and T23. Since the phase of the clock signal CIN01 is ahead of the phase of the clock signal COUT00, the first and second phase difference information RD0 and RS0 reflect the phase difference, and time T3, T8, It changes at T12, T16, T20, and T24. As a result, the phase difference information UD0 of the phase difference information decoder DEC0 reflects the change of the first and second phase difference information RD0 and RS0, and the time difference TUD, the phase difference information UD0 of the phase difference information decoder DEC0 is It changes with 1, -1, -2, -2, -3, -3.

  In response to the change in the phase difference information UD0 of the phase difference information decoder DEC0, the phase difference information SP0 between the previous clock cycle and the current clock cycle is synchronized with the clock signal CRIN0 from the phase synchronization circuit PLL at times T5, T9, T13, T17. , T21, T25 change to 0, -1, 0, -1, 0, -1, 0.

  The control signal FD0 for controlling the delay amount TF0 of the fine delay stage circuit FC0 changes to 16′b00000000_10000000, 16′b00000000_01000000,... In response to the change of the phase difference information SP0.

  Further, the control signal VFD0 for controlling the delay amount of the variable delay stage VU0 of the coarse adjustment delay stage circuit CC0 is delayed by one cycle of the clock signal CRIN from the change of the phase difference information SP0 and the change of the control signal FD0, so , T13, T17, T21, and T25 change to 2, 1, 0, 14, 12, and 9, respectively.

  On the other hand, at time T12, the carry-down signal BR0 of the coarse adjustment delay stage circuit CC0 of the decoding result of the phase difference information decoder DEC0 becomes high level, and at time T17, the coarse adjustment delay stages CU00 to CU0m−1 of the coarse adjustment delay stage circuit CC0. By reducing the value of the delay control signal CD0 that controls the number of stages m from 45 to 44, an underflow of the control signal VFD0 that controls the propagation delay time of the variable delay stage VU0 of the coarse adjustment delay stage circuit CC0 is prevented. The change of the value of the delay control signal CD0 from 45 to 44 is executed by changing the high-level bit position of the 51-bit delay control signal CD0 from the 45th bit to the 44th bit.

  Among the control signals shown in FIG. 4, the phase information RS0, RD0, UD0, the carry signal CR0 and the carry signal BR0 are synchronized with the clock signals COUT00, COUT01, while the phase difference between the previous clock cycle and the current clock cycle. Information SP0, delay amount control signal FD0 of fine adjustment delay stage circuit FC0, control signal VFD0 of variable delay stage VU0 of coarse adjustment delay stage circuit CC0, and delay control signal CD0 for controlling the number m of coarse adjustment delay stages CU00 to CU0m-1 Is synchronized with the clock signal CRIN0 from the phase synchronization circuit PLL.

  FIG. 5 is a diagram for explaining the operation of the phase difference information decoder DEC0 of the delay control circuit DCTL0 of the coarse adjustment delay stage circuit CC0 of the semiconductor chip CHIP0 according to the first embodiment of the present invention shown in FIG.

  In the example of FIG. 5, the number n of fine delay stage circuit FC0 is set to n = 16, and the number p of flip-flops FF0 connected to phase difference information decoder DEC0 of delay control circuit DCTL0 is set to p = 4. Has been.

  In response to the 16-bit second phase difference information RS0, the phase difference information decoder DEC0 indicates how many bits the change point of 1 and 0 of the bit string of the phase difference information RS0 is shifted from the 8-bit position with a positive or negative sign. The value ΔUD is output. The value ΔUD of the positive / negative sign determines the delay change amount UD0 for controlling the delay amount TF0 of the fine delay stage circuit FC0 in the next cycle.

[Embodiment 2]
FIG. 6 is a diagram showing a configuration of the semiconductor chip CHIP0 according to the second embodiment of the present invention.

  The semiconductor chip CHIP0 according to the second embodiment of the present invention shown in FIG. 6 is different from the semiconductor chip CHIP0 according to the first embodiment of the present invention shown in FIG. 2 in that the semiconductor chip CHIP0 shown in FIG. In contrast, in the semiconductor chip CHIP0 shown in FIG. 6, the fixed first power supply voltage VDD00 is supplied to the first functional block MOD00, and the voltage is dynamically controlled by the DVFS control to the second functional block MOD01. The second power supply voltage VDD01 is supplied.

  The following differences are as follows.

  That is, in the semiconductor chip CHIP0 shown in FIG. 6, for example, the second power supply voltage VDD01 supplied to the second functional block MOD01 decreases, and the second of the plurality of second buffers BUF01 inside the second functional block MOD01. When the propagation delay time TM01 increases, the total delay time of the delay time TF0 of the fine adjustment delay stage circuit FC0 of the clock synchronization circuit CS0 and the delay time TC0 of the coarse adjustment delay stage circuit CC0 increases. Therefore, the clock synchronization circuit CS0 propagates the fine delay stage circuit FC0 so that the increase in the total propagation delay time TM00 + TC0 + TF0 in the first functional block MOD00 and the increase in the propagation delay time TM01 in the second functional block MOD01 coincide. The total delay time of the delay time TF0 and the propagation delay time TC0 of the coarse adjustment delay stage circuit CC0 is dynamically controlled. In this way, even if the second power supply voltage VDD01 supplied to the second functional block MOD01 changes, the first and second functional blocks MOD00 and MOD01 are supplied to the flip-flops MFF00 and MFF01 in the MOD01, respectively. It can be understood that the relative phase difference between the first and second clock signals COUT00 and COUT01 is reduced.

<< Absorption of delay time difference due to power fluctuation >>
FIG. 7 shows the propagation delay of the fine delay stage circuit FC0 when the second power supply voltage VDD01 changes by the DVFS control in the semiconductor chip CHIP0 according to the second embodiment of the present invention shown in FIG. Controls the time TF0 and the propagation delay time TC0 of the coarse delay stage circuit CC0 to absorb the difference (TM00-TM01) between the propagation delay times of the first and second functional blocks MOD00 and MOD01 and the clock buffers BUF00 and BUF01. FIG.

  As shown in FIG. 7A, in the second power supply voltage VDD01 supplied to the second functional block MOD01, a switching ripple is generated in the entire period TRIP_VR0, and it oscillates around the voltage V1 until time T0. In addition, after time T2, it vibrates with an amplitude of several tens of millivolts around the voltage V2. Further, assuming that the processing load of the second functional block MOD01 becomes a light load at the time T0 as a boundary, a load fluctuation ripple occurs at the time T0 to T1 (period TRIP_WC0), and the second power supply voltage VDD01 becomes the voltage. The voltage increases rapidly from V1 to voltage V0. At subsequent times T1 to T2 (period TDVFS0), the change of the second power supply voltage VDD01 by the DVFS control is executed, and the second power supply voltage VDD01 gradually drops from the voltage V0 to the voltage V2.

  On the other hand, as shown in FIG. 7C, in the first power supply voltage VDD00 supplied to the first functional block MOD00, only the switching ripple occurs in the entire period (period TRIP_VR0), and the first power supply voltage VDD00 vibrates at several tens of millivolts around the voltage V3.

  FIG. 7B shows how the second functional block MOD01 changes when the second power supply voltage VDD01 supplied to the second functional block MOD01 changes as shown in FIG. 7A. FIG.

  As can be understood from FIG. 7B, when the second power supply voltage VDD01 decreases as shown in FIG. 7A, the propagation delay time TM01 of the clock buffer BUF01 of the second functional block MOD01 increases. ing.

  On the other hand, as can be seen from FIG. 7D, the first power supply voltage VDD00 supplied to the first functional block MOD00 is substantially constant voltage V3 as shown in FIG. The propagation delay time TM00 of the clock buffer BUF00 of the functional block MOD00 is maintained at a substantially constant delay amount. However, as shown in FIG. 7D, the total delay time of the propagation delay time TF0 of the fine delay stage circuit FC0 and the propagation delay time TC0 of the coarse delay stage circuit CC0 is increased by the operation of the clock synchronization circuit CS0. The total propagation delay time TM00 + TC0 + TF0 of the first functional block MOD00 is increased.

  As a result, the clock synchronization circuit CS0 is finely adjusted so that the relationship TM00 + TC0 + TF0 = TM01 always holds between the total propagation delay time TM00 + TC0 + TF0 of the first functional block MOD00 and the total propagation delay time TM01 of the second functional block MOD01. It is understood that the total delay time of the propagation delay time TF0 of the delay stage circuit FC0 and the propagation delay time TC0 of the coarse adjustment delay stage circuit CC0 is dynamically controlled. In this way, even if the second power supply voltage VDD01 supplied to the second functional block MOD01 changes, the first and second functional blocks MOD00 and MOD01 are supplied to the flip-flops MFF00 and MFF01 in the MOD01, respectively. It can be understood that the relative phase difference between the first and second clock signals COUT00 and COUT01 is reduced.

[Embodiment 3]
FIG. 8 is a diagram showing a configuration of a semiconductor chip CHIP0 according to the third embodiment of the present invention. The phase synchronization circuit PLL, the clock synchronization circuit CS0, and the first and second functional blocks MOD00, MOD01, and MOD02 built in the semiconductor CHIP0 are respectively composed of an N channel MOS transistor and a P channel. A CMOS circuit including a MOS transistor is used.

  The semiconductor chip CHIP0 according to the third embodiment of the present invention shown in FIG. 8 is different from the semiconductor chip CHIP0 according to the first embodiment of the present invention shown in FIG. 2 in that the semiconductor chip CHIP0 shown in FIG. Similarly to the semiconductor chip CHIP0 shown in FIG. 8, the second power supply voltage VDD01 whose voltage is dynamically controlled by DVFS control is supplied to the first functional block MOD00, and the first functional block MOD01 is fixed to the first functional block MOD01. The third power supply voltage VDD00 is supplied, and the third power supply voltage VDD02 whose voltage is dynamically controlled by the DVFS control is also supplied to the third functional block MOD02.

  The following differences are as follows.

  That is, in the semiconductor chip CHIP0 shown in FIG. 8, the third functional block MOD02 is composed of the clock buffer BUF02 and the flip-flop MFF02, like the first and second functional blocks MOD00 and MOD01. Further, the semiconductor chip CHIP0 shown in FIG. 8 includes a fine delay stage circuit FC1, a coarse delay stage circuit CC1, a differential shift circuit DS1, and a relative phase difference measurement circuit RSM1 for the third functional block MOD02. Note that the fine delay stage circuit FC1, the coarse delay stage circuit CC1, the differential shift circuit DS1, and the relative phase difference measurement circuit RSM1 for the third functional block MOD02 have the same fine delay for the first functional block MOD00. Since the configuration is the same as that of the stage circuit FC0, the coarse delay stage circuit CC0, the difference shift circuit DS0, and the relative phase difference measurement circuit RSM0, detailed description is omitted.

<< Absorption of delay time difference due to power fluctuation >>
FIG. 9 shows the propagation delay of the fine delay stage circuit FC1 when the third power supply voltage VDD02 is changed by the DVFS control in the semiconductor chip CHIP0 according to the third embodiment of the present invention shown in FIG. Controls the time TF1 and the propagation delay time TC1 of the coarse delay stage circuit CC1 to absorb the difference (TM01-TM02) in the propagation delay times of the clock buffers BUF01 and BUF02 in the second and third functional blocks MOD01 and MOD02 FIG.

  9 (A), (B), (C), and (D) show DVFS in the semiconductor chip CHIP0 as in FIGS. 3 (A), (B), (C), and (D). When the second power supply voltage VDD01 is changed by the control, the clock synchronization circuit CS0 controls the propagation delay time TF0 of the fine adjustment delay stage circuit FC0 and the propagation delay time TC0 of the coarse adjustment delay stage circuit CC0 to control the first and second It shows how the operation of absorbing the difference (TM00-TM01) in the propagation delay time between the clock buffers BUF00 and BUF01 in the functional blocks MOD00 and MOD01 is extinguished.

  Further, as shown in FIG. 9E, in the third power supply voltage VDD02 supplied to the third functional block MOD02, a switching ripple occurs in the entire period TRIP_VR1, and it oscillates around the voltage V2 until time T3. . Further, assuming that the processing load of the third functional block MOD02 has changed from a light load to a heavy load at time T3 as a boundary, a change in the third power supply voltage VDD02 by DVFS control at times T3 to T4 (period TDVFS1) Is executed, and the third power supply voltage VDD02 gradually rises from the voltage V2 to the voltage V0. Thereafter, a load fluctuation ripple occurs at times T4 to T5 (period TRIP_WC1), and the third power supply voltage VDD02 rapidly decreases from the voltage V0 to the voltage V1. On the other hand, after time T5, the third power supply voltage VDD02 oscillates with an amplitude of several tens of millivolts around the voltage V2.

  FIG. 9F shows a fine delay stage circuit for the third functional block MOD02 when the third power supply voltage VDD02 supplied to the third functional block MOD02 changes as shown in FIG. It is a figure which shows the mode of change of propagation delay time TF1 of FC1, propagation delay time TC1 of coarse adjustment delay stage circuit CC1, and propagation delay time TM02 of clock buffer BUF02.

  As can be understood from FIG. 9F, when the third power supply voltage VDD02 increases as shown in FIG. 9E, the propagation delay time TM02 of the clock buffer BUF02 of the third functional block MOD02 decreases. Inversely, the total delay time of the propagation delay time TF1 of the fine delay stage circuit FC1 and the propagation delay time TC1 of the coarse delay stage circuit CC1 is increased by the operation of the clock synchronization circuit CS1.

  As a result, the clock synchronization circuit CS1 is finely adjusted so that the relationship TM02 + TC1 + TF1 = TM01 always holds between the total propagation delay time TM02 + TC1 + TF1 of the third functional block MOD02 and the total propagation delay time TM01 of the second functional block MOD01. It is understood that the total delay time of the propagation delay time TF1 of the delay stage circuit FC1 and the propagation delay time TC1 of the coarse adjustment delay stage circuit CC0 is dynamically controlled. In this way, even if the third power supply voltage VDD02 supplied to the third functional block MOD02 changes, the second and third functional blocks MOD01 and MOD02 are supplied to the flip-flops MFF01 and MFF02, respectively. It can be understood that the relative phase difference between the second and third clock signals COUT01 and COUT02 is reduced.

  As described above, according to the semiconductor chip CHIP0 according to the third embodiment of the present invention shown in FIG. 8, propagation from the phase synchronization circuit PLL as the supply clock source to the plurality of functional block flip-flops at the supply destination Since the delay times can be set substantially equal, there is an effect that the timing design of a semiconductor chip incorporating a large number of functional blocks becomes easy.

  As mentioned above, the invention made by the present inventor has been specifically described based on various embodiments. However, the present invention is not limited thereto, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the semiconductor chip CHIP0 according to the third embodiment of the present invention shown in FIG. 8, the number of functional blocks can be four or more, and the power supply voltages can be four or more.

  Furthermore, the present invention can not only reduce the difference in delay time of the plurality of functional blocks in the semiconductor chip when the power supply voltage is changed by DVFS control, but also can reduce the difference between the plurality of functional blocks in the semiconductor chip by the semiconductor chip manufacturing process. It is possible to reduce a difference in delay time depending on nonuniformity or nonuniformity of temperature distribution of a plurality of functional blocks inside a semiconductor chip.

  Furthermore, the first, second and third power supply voltages VDD00, VDD01 and VDD02 of the semiconductor chip CHIP0 are not only supplied from the outside of the semiconductor chip CHIP0 but also supplied from an on-chip voltage regulator built in the semiconductor chip CHIP0. It is also possible.

CHIP0 ... semiconductor chip PLL ... phase synchronization circuit VDD00, VDD01, VDD02 ... power supply voltage FC0 ... fine adjustment delay stage circuit FU00-FU0n-1 ... unit fine adjustment delay stage SWF00-SWF0n-1 ... path switch TF0 ... fine adjustment delay stage circuit FC0 Clock propagation delay time FD00 to FD0n-1 ... fine adjustment delay stage control signal DS0 ... difference shift circuit SS0 ... shift type switch RSM0 ... relative phase difference measurement circuit FDR0 ... fine adjustment delay stage adjustment circuit FUM00 to FUM0n-1 ... unit fine adjustment delay stage SWM00 ~ SWM0n-1 ... path changeover switch LS0, LS1 ... level shifter RD, RS ... phase difference information FFM00 to FFMM0n-1 ... phase difference information holding flip-flop FUD00 to FUD0n-1 ... unit fine adjustment delay stage CC0 ... coarse adjustment delay stage circuit VU0: variable delay stage circuit CU0: unit coarse adjustment delay stage circuit TC0: coarse propagation delay stage circuit CC0 clock propagation delay time VFD0: variable delay stage control signal CD00-CD0m-1 ... coarse adjustment delay stage control signal ABS0: subtraction circuit VCTL0 ... variable delay stage control circuit CCTL0 ... coarse delay stage control circuit CR0 ... carry-up signal BR0 ... carry-down signal DE0C ... phase difference information decoder SP0 ... phase difference information FF0 ... phase difference information holding flip-flop DCTL0 ... coarse delay Stage control unit MOD0, 1, 2, ... function block

Claims (18)

A first functional block, a second functional block, a clock generation circuit, and a clock supply circuit;
A clock signal can be generated from the clock generation circuit,
The first functional block and the second functional block can be supplied with first and second power supply voltages having different voltage values,
The first functional block includes a first internal circuit and a first logic circuit capable of supplying one of the first and second power supply voltages,
The second functional block includes a second internal circuit and a second logic circuit capable of supplying the other power supply voltage of the first and second power supply voltages,
The clock signal generated from the clock generation circuit is transferred to the first logic circuit of the first functional block via the clock supply circuit and the first internal circuit of the first functional block. It can be transmitted as the first operation clock signal,
The clock signal generated from the clock generation circuit is supplied to the second logic circuit of the second functional block via the second internal circuit of the second functional block. Can be communicated as
The clock supply circuit includes a fine delay stage circuit, a coarse delay stage circuit, and a phase difference measurement circuit,
The clock signal generated from the clock generation circuit passes through the series path of the fine delay stage circuit and the coarse delay stage circuit of the clock supply circuit and the first internal circuit of the first functional block. The first functional block can be transmitted to the first logic circuit as the first operation clock signal.
The fine change width of the fine delay time of the fine delay stage circuit of the clock supply circuit can be set to a value smaller than the coarse change width of the coarse delay time of the coarse delay stage circuit of the clock supply circuit. And
The phase difference measurement circuit of the clock supply circuit responds to a phase difference between the first operation clock signal and the second operation clock signal, and the fine delay time and the coarse adjustment of the fine delay stage circuit. A semiconductor integrated circuit characterized in that the coarse delay time of a delay stage circuit can be controlled. The semiconductor integrated circuit according to claim 1,
The clock supply circuit when the first propagation delay time of the first internal circuit of the first functional block increases due to a decrease in the one power supply voltage supplied to the first functional block The phase difference measuring circuit reduces a total delay time of the fine delay time of the fine delay stage circuit of the clock supply circuit and the coarse delay time of the coarse delay stage circuit. circuit. The semiconductor integrated circuit according to claim 2,
The response speed of changing the fine delay time of the fine delay stage circuit of the clock supply circuit can be set faster than the response speed of changing the coarse delay time of the coarse delay stage circuit of the clock supply circuit And
The clock supply circuit further includes a difference shift circuit connected between the phase difference measurement circuit and the fine delay stage circuit,
The coarse delay stage circuit of the clock synchronization circuit notifies the difference shift circuit of the phase difference information of the previous cycle,
The difference shift circuit outputs a delay amount control signal as a result of subtraction between the first phase difference information in the current cycle supplied from the phase difference measurement circuit and the phase difference information in the previous cycle, to the fine delay stage. A semiconductor integrated circuit characterized by notifying a circuit. The semiconductor integrated circuit according to claim 3,
The first internal circuit of the first functional block includes a first clock buffer that transmits the first operation clock signal to the first logic circuit of the first functional block;
The second internal circuit of the second functional block includes a second clock buffer that transmits the second operation circuit to the second logic circuit of the second functional block as the second operation clock signal. A semiconductor integrated circuit. The semiconductor integrated circuit according to claim 4,
The first logic circuit of the first functional block includes a first flip-flop to which the first operation clock signal transmitted from the first clock buffer is supplied to a trigger input terminal. ,
The second internal circuit of the second functional block includes a second flip-flop in which the second operation clock signal transmitted from the second clock buffer is supplied to a trigger input terminal. A semiconductor integrated circuit. The semiconductor integrated circuit according to claim 5,
A third functional block capable of supplying a third power supply voltage;
The third functional block includes a third internal circuit capable of supplying the third power supply voltage and a third logic circuit,
The clock signal generated from the clock generation circuit is transferred to the third logic circuit of the third functional block via the clock supply circuit and the third internal circuit of the third functional block. It can be transmitted as a third operation clock signal,
The clock supply circuit further includes another fine delay stage circuit, another coarse delay stage circuit, and another phase difference measurement circuit,
The clock signal generated from the clock generation circuit includes a serial path of the other fine adjustment delay stage circuit and the other coarse adjustment delay stage circuit of the clock supply circuit and the third internal of the third functional block. And the third operation clock signal can be transmitted to the third logic circuit of the third functional block via a circuit,
The fine change width of the fine delay time of the other fine delay stage circuit of the clock supply circuit is smaller than the coarse change width of the coarse delay time of the other coarse delay stage circuit of the clock supply circuit. It can be set,
The other phase difference measurement circuit of the clock supply circuit is responsive to a phase difference between the second operation clock signal and the third operation clock signal, and the fine delay time of the other fine delay stage circuit. And the coarse delay time of the other coarse delay stage circuit can be controlled. The semiconductor integrated circuit according to claim 6,
The clock supply when the third propagation delay time of the third internal circuit of the third functional block increases due to the increase of the third power supply voltage supplied to the third functional block. The other phase difference measurement circuit of the circuit reduces a total delay time of the fine delay time of the other fine delay stage circuit of the clock supply circuit and the coarse delay time of the other coarse delay stage circuit. A semiconductor integrated circuit. The semiconductor integrated circuit according to claim 7,
The response speed of changing the fine delay time of the other fine delay stage circuit of the clock supply circuit is higher than the response speed of changing the coarse delay time of the other coarse delay stage circuit of the clock supply circuit. It can be set at high speed,
The clock supply circuit further includes another difference shift circuit connected between the other phase difference measurement circuit and the other fine delay stage circuit,
The other coarse delay stage circuit of the clock synchronization circuit notifies the other phase shift information of the other phase difference information of the previous cycle,
The other difference shift circuit is a second delay of the subtraction result of the second phase difference information in the current cycle supplied from the other phase difference measurement circuit and the other phase difference information in the previous cycle. A semiconductor integrated circuit characterized in that a quantity control signal is notified to said other fine delay stage circuit. The semiconductor integrated circuit according to claim 8, comprising:
The semiconductor integrated circuit wherein the first functional block, the second functional block, the third functional block, the clock generation circuit, and the clock supply circuit are constituted by a CMOS circuit. circuit. An operation method of a semiconductor integrated circuit comprising a first functional block, a second functional block, a clock generation circuit, and a clock supply circuit,
Generating a clock signal by the clock generation circuit;
Supplying first and second power supply voltages having different voltage values to the first functional block and the second functional block;
The first logic block included in the first functional block receives the clock signal generated from the clock generation circuit via the clock supply circuit and the first internal circuit included in the first functional block. Transmitting to the circuit as a first operating clock signal;
The clock signal generated from the clock generation circuit is supplied to the second logic circuit included in the second functional block via the second internal circuit included in the second functional block. Transmitting as a clock signal;
The clock signal generated from the clock generation circuit is passed through a series path of a fine delay stage circuit and a coarse delay stage circuit included in the clock supply circuit and the first internal circuit of the first functional block. Transmitting to the first logic circuit of the first functional block as the first operation clock signal;
Setting a fine change width of the fine delay time of the fine delay stage circuit of the clock supply circuit to a value smaller than a coarse change width of the coarse delay time of the coarse delay stage circuit of the clock supply circuit; ,
In response to the phase difference between the first operation clock signal and the second operation clock signal by the phase difference measurement circuit included in the clock supply circuit, the fine delay time of the fine delay stage circuit and the coarse delay time Controlling the coarse delay time of the delay stage circuit,
One of the first and second power supply voltages can be supplied to the first internal circuit and the first logic circuit of the first functional block,
The second integrated circuit and the second logic circuit of the second functional block can be supplied with the other power supply voltage of the first and second power supply voltages. How it works. A method for operating a semiconductor integrated circuit according to claim 10, comprising:
The clock supply circuit when the first propagation delay time of the first internal circuit of the first functional block increases due to a decrease in the one power supply voltage supplied to the first functional block The phase difference measuring circuit reduces a total delay time of the fine delay time of the fine delay stage circuit of the clock supply circuit and the coarse delay time of the coarse delay stage circuit. How the circuit works. A method for operating a semiconductor integrated circuit according to claim 11, comprising:
The response speed of changing the fine delay time of the fine delay stage circuit of the clock supply circuit can be set faster than the response speed of changing the coarse delay time of the coarse delay stage circuit of the clock supply circuit And
The clock supply circuit further includes a difference shift circuit connected between the phase difference measurement circuit and the fine delay stage circuit,
The coarse delay stage circuit of the clock synchronization circuit notifies the difference shift circuit of the phase difference information of the previous cycle,
The difference shift circuit outputs a delay amount control signal as a result of subtraction between the first phase difference information in the current cycle supplied from the phase difference measurement circuit and the phase difference information in the previous cycle, to the fine delay stage. A method of operating a semiconductor integrated circuit, characterized by notifying a circuit. A method of operating a semiconductor integrated circuit according to claim 12, comprising:
The first internal circuit of the first functional block includes a first clock buffer that transmits the first operation clock signal to the first logic circuit of the first functional block;
The second internal circuit of the second functional block includes a second clock buffer that transmits the second operation circuit to the second logic circuit of the second functional block as the second operation clock signal. A method for operating a semiconductor integrated circuit. A method for operating a semiconductor integrated circuit according to claim 13, comprising:
The first logic circuit of the first functional block includes a first flip-flop to which the first operation clock signal transmitted from the first clock buffer is supplied to a trigger input terminal. ,
The second internal circuit of the second functional block includes a second flip-flop in which the second operation clock signal transmitted from the second clock buffer is supplied to a trigger input terminal. A method for operating a semiconductor integrated circuit. 15. A method for operating a semiconductor integrated circuit according to claim 14, comprising:
A third functional block capable of supplying a third power supply voltage;
The third functional block includes a third internal circuit capable of supplying the third power supply voltage and a third logic circuit,
The clock signal generated from the clock generation circuit is transferred to the third logic circuit of the third functional block via the clock supply circuit and the third internal circuit of the third functional block. It can be transmitted as a third operation clock signal,
The clock supply circuit further includes another fine delay stage circuit, another coarse delay stage circuit, and another phase difference measurement circuit,
The clock signal generated from the clock generation circuit includes a serial path of the other fine adjustment delay stage circuit and the other coarse adjustment delay stage circuit of the clock supply circuit and the third internal of the third functional block. And the third operation clock signal can be transmitted to the third logic circuit of the third functional block via a circuit,
The fine change width of the fine delay time of the other fine delay stage circuit of the clock supply circuit is smaller than the coarse change width of the coarse delay time of the other coarse delay stage circuit of the clock supply circuit. It can be set,
The other phase difference measurement circuit of the clock supply circuit is responsive to a phase difference between the second operation clock signal and the third operation clock signal, and the fine delay time of the other fine delay stage circuit. And the coarse adjustment delay time of the other coarse adjustment delay stage circuit can be controlled. A method for operating a semiconductor integrated circuit according to claim 15, comprising:
The clock supply when the third propagation delay time of the third internal circuit of the third functional block increases due to the increase of the third power supply voltage supplied to the third functional block. The other phase difference measurement circuit of the circuit reduces a total delay time of the fine delay time of the other fine delay stage circuit of the clock supply circuit and the coarse delay time of the other coarse delay stage circuit. A method for operating a semiconductor integrated circuit. A method for operating a semiconductor integrated circuit according to claim 16, comprising:
The response speed of changing the fine delay time of the other fine delay stage circuit of the clock supply circuit is higher than the response speed of changing the coarse delay time of the other coarse delay stage circuit of the clock supply circuit. It can be set at high speed,
The clock supply circuit further includes another difference shift circuit connected between the other phase difference measurement circuit and the other fine delay stage circuit,
The other coarse delay stage circuit of the clock synchronization circuit notifies the other phase shift information of the other phase difference information of the previous cycle,
The other difference shift circuit is a second delay of the subtraction result of the second phase difference information in the current cycle supplied from the other phase difference measurement circuit and the other phase difference information in the previous cycle. A method of operating a semiconductor integrated circuit, characterized in that a quantity control signal is notified to said other fine delay stage circuit. A method of operating a semiconductor integrated circuit according to claim 17,
The semiconductor integrated circuit wherein the first functional block, the second functional block, the third functional block, the clock generation circuit, and the clock supply circuit are constituted by a CMOS circuit. How the circuit works.

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