JP2009252798A - Carbon nanotube field-effect transistor and its fabrication process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for fabricating a carbon nanotube field-effect transistor which exhibits excellent electrical conduction characteristics with good reproducibility. <P>SOLUTION: At first, a carbon nanotube becoming a channel is arranged on a substrate and then the carbon nanotube is coated with a protective film. Subsequently, a contact hole for connecting a source electrode or a drain electrode electrically with the carbon nanotube is formed in the protective film and a part of the carbon nanotube is exposed. Finally, a source electrode and a drain electrode are formed on the contact hole, and electrically connected with the carbon nanotube, respectively. Since the carbon nanotube becoming a channel is not polluted in a field-effect transistor thus fabricated, excellent electrical conduction characteristics are exhibited stably. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a field effect transistor using a carbon nanotube as a channel and a method for manufacturing the same.

  A carbon nanotube (hereinafter referred to as “CNT”) is a tubular substance composed of carbon atoms that exhibits semiconducting or metallic properties due to chirality. Since CNT has a diameter of several nanometers and high current density, it enables formation of very thin wiring with one-dimensional conduction, and is expected to be applied to a quantum device operating at high speed. For example, research has been actively conducted in recent years in which CNTs having semiconductor characteristics are used as channels of field effect transistors (hereinafter referred to as “FETs”).

  A carbon nanotube field effect transistor (hereinafter referred to as “CNT-FET”) using a CNT channel is a method in which a CNT is grown from a catalyst formed on a substrate and then a source electrode and a drain electrode are formed on both ends of the CNT (direct growth). Method) or a method in which CNT dissolved in a solvent is dispersed on a substrate and then source and drain electrodes are formed on both ends of the CNT (dispersion method).

For example, Patent Document 1 discloses an n-type CNT-FET using CNT as a channel. In this invention, after forming a source electrode and a drain electrode on both ends of a CNT grown from a catalyst, a film of a nitrogen compound (for example, silicon nitride) is formed on the CNT, whereby a CNT- having an n-type channel is formed. An FET is manufactured.
JP 2006-222279 A

  However, the conventional manufacturing method has a problem that a CNT-FET that stably exhibits excellent electrical conduction characteristics cannot be manufactured with good reproducibility.

  In the above conventional manufacturing method, the CNTs that become the channels are exposed to cleaning chemicals or resists for patterning when the electrodes are formed, so that defects are formed or the resist residues are contaminated. End up. The defects formed in this way cause deterioration of the electrical conduction characteristics of the CNT-FET. In addition, CNTs with many defects are likely to adsorb atmospheric oxygen, water molecules, etc., so the defects formed are the cause of hysteresis characteristics for the gate bias of CNT-FETs along with contaminants that cannot be removed during the manufacturing process. It also becomes.

  The present invention has been made in view of such a point, and a method capable of producing a CNT-FET stably exhibiting excellent electrical conduction characteristics with good reproducibility, and a CNT-FET produced by the method. The purpose is to provide.

  The field effect transistor of the present invention includes a semiconductor substrate having an insulating film, a carbon nanotube disposed on the insulating film, a protective film covering the carbon nanotube, and a protective film covering the carbon nanotube, and A source electrode and a drain electrode, each of which is electrically connected to the carbon nanotube via a connection hole formed in the protective film.

  The field effect transistor manufacturing method of the present invention includes a step of preparing a semiconductor substrate having an insulating film, a step of disposing a carbon nanotube on the insulating film of the semiconductor substrate, and a step of forming a protective film on the carbon nanotube. And forming a connection hole in each of the source electrode formation planned region and the drain electrode formation planned region of the protective film to expose a part of the carbon nanotube, and electrically connecting the carbon nanotube through the connection hole Forming a source electrode on the source electrode formation planned region of the protective film so as to be connected to the carbon nanotube, and a drain electrode of the protective film so as to be electrically connected to the carbon nanotube through the connection hole Forming a drain electrode on the region to be formed.

  According to the present invention, a CNT-FET that stably exhibits excellent electrical conduction characteristics can be produced with good reproducibility without using a special apparatus. Therefore, according to the present invention, a large amount of CNT-FETs can be manufactured with a high yield using an existing general manufacturing apparatus.

1. CNT-FET of the present invention
A CNT-FET manufactured by the manufacturing method of the present invention (hereinafter also referred to as “CNT-FET of the present invention”) includes a semiconductor substrate having an insulating film, a CNT (channel) disposed on the insulating film, and the CNT , A source electrode and a drain electrode disposed on the protective film, and a gate electrode.

  FIG. 1 is a cross-sectional view of a CNT-FET of the present invention for illustrating an example of a positional relationship between a CNT serving as a channel, a protective film, and a source electrode and a drain electrode. In FIG. 1, the CNT-FET 100 includes a semiconductor substrate 110, a source electrode 120 and a drain electrode 130, a CNT 140 serving as a channel, and a protective film 150. In this example, the semiconductor substrate 110 has an insulating film 112 on one side thereof. In the CNT-FET 100, a current flowing between the source electrode 120 and the drain electrode 130 is controlled by a voltage applied to a gate electrode (not shown).

  As will be described later, in the method of manufacturing the CNT-FET 100 of the present invention, the source electrode formed on the protective film 150 is formed by forming a connection hole 152 in the protective film 150 covering the CNT 140 to expose a part of the CNT 140. 120 and the drain electrode 130 are each electrically connected to the CNT 140 through the connection hole 152. Therefore, in the CNT-FET 100 of the present invention, the source electrode 120 and the drain electrode 130 are disposed on the protective film 150, and the source electrode 120 and the drain electrode 130 are connected via the connection hole 152 formed in the protective film 150. Each of them is electrically connected to the CNT 140.

[Substrate]
The substrate included in the CNT-FET of the present invention is a semiconductor substrate, and at least the surface on which the source electrode and the drain electrode are arranged is covered with an insulating film. The material of the semiconductor substrate is not particularly limited. For example, group 14 elements such as silicon and germanium, III-V compounds such as gallium arsenide (GaAs) and indium phosphide (InP), and II- such as zinc telluride (ZnTe). And VI compounds. The size and thickness of the semiconductor substrate are not particularly limited and may be set as appropriate. The material of the insulating film is not particularly limited as long as it has an insulating property and a high dielectric constant. For example, inorganic compounds such as silicon oxide, silicon nitride, aluminum oxide, and titanium oxide, and organic compounds such as acrylic resin and polyimide are used. It is. The insulating film may have a multilayer structure, for example, a two-layer structure in which a silicon nitride film is stacked on a silicon oxide film. The thickness of the insulating film is not particularly limited as long as the insulating property can be ensured, and may be set as appropriate according to the position of the gate electrode. For example, when the insulating film has a two-layer structure in which a silicon nitride film is stacked on a silicon oxide film, the thickness of the silicon oxide film is preferably 10 nm to 1000 nm (for example, 80 nm), and the thickness of the silicon nitride film Moreover, it is preferable that it is 10 nm-1000 nm (for example, 100 nm). The insulating film may cover only one surface of the semiconductor substrate (the surface on which the source electrode and the drain electrode are disposed) or may cover both surfaces. The insulating film may cover the entire surface on which the source electrode and the drain electrode are disposed, or may cover a part (at least a region in which the CNT, the source electrode and the drain electrode are disposed). Also good.

[About channels]
In the CNT-FET of the present invention, the channel connecting the source electrode and the drain electrode is composed of CNTs. The CNT constituting the channel may be either single-wall CNT or multi-wall CNT, but single-wall CNT is preferable. Further, the source electrode and the drain electrode may be connected by a single CNT, or may be connected by a plurality of CNTs. For example, a plurality of CNTs may be folded and connected between the source electrode and the drain electrode, or the source electrode and the drain electrode may be connected by a bundle of CNTs.

[Protective film]
In the CNT-FET of the present invention, the CNT that becomes the channel is covered with a protective film. The material of the protective film is not particularly limited as long as it has insulating properties, and examples thereof include silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, and titanium oxide. The protective film may be formed only around the CNTs, or may be formed so as to cover all or part of the surface of the substrate on which the CNTs are arranged. The thickness of the protective film is not particularly limited as long as it can completely cover (protect) the CNT serving as a channel, but is preferably 10 nm to 100 nm (for example, 20 nm).

  As described above, the protective film has a connection hole for the source electrode or the drain electrode to be electrically connected to the CNT. The position of the connection hole is not particularly limited as long as the source electrode or the drain electrode can be connected to the CNT. For example, the connection hole may be formed in a direction perpendicular to the substrate surface at a position where the source or drain electrode and the CNT overlap with each other when viewed from the upper surface of the substrate (see FIG. 1). The distance between the connection hole for connecting the source electrode to the CNT and the connection hole for connecting the drain electrode to the CNT is not particularly limited, but is preferably 10 μm or less. This is because CNT may have a defect, but even in that case, if the length is 10 μm or less, there is a high possibility that the CNT does not contain a defect. The size of the connection hole (cross-sectional diameter) is not particularly limited as long as the source electrode and the drain electrode can be electrically connected to the CNT.

[About source and drain electrodes]
A source electrode and a drain electrode are disposed on the protective film of the CNT-FET of the present invention. The material of the source electrode and the drain electrode is, for example, a metal such as gold, platinum, chromium, titanium, aluminum, palladium, molybdenum, or a semiconductor such as polysilicon. The source electrode and the drain electrode may have a multilayer structure of two or more kinds of metals. For example, the source electrode and the drain electrode may be formed by stacking a gold layer on a titanium layer. The shape of the source and drain electrodes and the interval between the electrodes are not particularly limited, and may be set as appropriate according to the purpose.

  As described above, the source electrode and the drain electrode are each electrically connected to the CNT through the connection hole formed in the protective film. At this time, the source electrode and the drain electrode may be connected only to the side surface of the CNT (side contact structure), or may be connected only to the end surface (cut surface) of the CNT (end contact structure), You may connect to the side surface and end surface of CNT. As will be described later, when forming the connection hole in the protective film, if only the protective film is etched by wet etching, a CNT-FET having a side contact structure can be manufactured. If CNT is also etched, a CNT-FET having an end contact structure can be manufactured.

[About gate electrode]
As described above, the CNT-FET of the present invention has a gate electrode. The material of the gate electrode is, for example, a metal such as gold, platinum, chromium, titanium, brass, and aluminum. The gate electrode is formed by evaporating these metals at an arbitrary position, for example. Alternatively, a separately prepared electrode (for example, a gold thin film) may be arranged at an arbitrary position to serve as a gate electrode. The position at which the gate electrode is disposed is not particularly limited as long as the current (source-drain current) flowing between the source electrode and the drain electrode disposed on the substrate can be controlled by the voltage, and the position is appropriately disposed according to the purpose. That's fine. For example, the CNT-FET of the present invention can adopt a top gate type, a side gate type, and a back gate type depending on the position of the gate electrode.

2. Manufacturing method of CNT-FET of the present invention The manufacturing method of CNT-FET of the present invention is as follows. (1) After CNT is arranged on an insulating film of a semiconductor substrate and before forming a source electrode and a drain electrode, A protective film to be covered is formed, and (2) a source electrode and a drain electrode are electrically connected to the CNTs through connection holes formed in the protective film, respectively. Steps such as “CNT placement” and “gate electrode formation” can be performed by appropriately applying conventional techniques.

[Preparation of substrate]
First, a substrate is prepared. The substrate is preferably a semiconductor substrate having the aforementioned insulating film. As will be described later, when an etching solution containing hydrofluoric acid (HF) is used when forming the connection hole by wet etching, the insulating film is a two-layer structure in which a silicon nitride film is stacked on a silicon oxide film. It is preferable that This is because the silicon nitride film functions as a wet etching stopper and can prevent the insulating film and the semiconductor substrate from being etched. In this case, the silicon oxide film has a function of improving the adhesion between the semiconductor substrate and the silicon nitride film.

[CNT arrangement]
A CNT to be a channel is disposed on the prepared insulating film of the substrate. As a method for arranging CNTs on a substrate, a conventionally known method such as the above-described direct growth method or dispersion method may be used as appropriate. For example, a plurality of catalyst layers for growing CNTs are formed at arbitrary positions on the insulating film of the substrate, and the CNTs are formed (arranged) by connecting the catalyst layers by growing the CNTs by chemical vapor deposition. )can do. At this time, the CNTs are arranged at positions where the source electrode and the drain electrode can be easily connected by forming the catalyst layer so as to be located immediately below the source electrode formation scheduled region and the drain electrode formation scheduled region. Can do.

[Formation of protective film]
After the CNTs are arranged on the substrate, the CNTs on the substrate are covered with a protective film. The method for forming the protective film is not particularly limited, but a method in which the thermal damage and chemical damage of the CNTs are small is preferable. Examples of such a method include a catalytic CVD method and an ALD (Atomic Layer Deposition) method which do not use plasma and have a low reaction temperature. In the ALD method, water molecules adsorbed on the CNTs can be removed in the course of film formation, so that the hysteresis characteristics of the CNT-FET can be reduced. In addition, in the ALD method, since the protective film is laminated for each monoatomic layer, the uniformity of the film and the step coverage are high, and the protective film can be formed so as to extend not only to the upper side surface but also to the lower side surface.

  The material of the protective film is not particularly limited as long as it has insulating properties. For example, the protective film may be a film made of silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, or titanium oxide. The thickness of the protective film is not particularly limited as long as it can completely cover (protect) the CNT serving as a channel, but is preferably 10 nm to 100 nm (for example, 20 nm).

  As described above, the manufacturing method of the present invention is characterized in that the CNT to be a channel is covered with the protective film before the process for forming the source electrode and the drain electrode is started. Therefore, the CNT that becomes the channel is physically and chemically protected in the subsequent manufacturing process. This protective film can also function as a protective film for the final FET device.

[Formation of connection holes]
After forming the protective film for covering the CNTs, a connection hole in a direction substantially perpendicular to the substrate surface is formed in the protective film to expose a part of the CNTs covered with the protective film. Since the exposed portion of the CNT becomes a connection portion with the source electrode and a connection portion with the drain electrode, at least two connection holes (for the source electrode and for the drain electrode) are formed. The position where the connection hole is formed is not particularly limited as long as the source electrode or the drain electrode can be connected to the CNT. For example, it may be a region where the source electrode is to be formed and a region where the drain electrode is to be formed. The distance between the connection hole for connecting the source electrode to the CNT and the connection hole for connecting the drain electrode to the CNT is not particularly limited, but is preferably 10 μm or less. The size of the connection hole (cross-sectional diameter) is not particularly limited as long as the source electrode and the drain electrode can be electrically connected to the CNT.

  A method for forming the connection hole is not particularly limited, and a conventionally known method such as wet etching or dry etching may be appropriately used. For example, when forming a connection hole using wet etching on a protective film made of silicon oxide, hafnium oxide, zirconium oxide or the like, after masking a region other than the region where the connection hole is to be formed on the surface of the protective film with a resist film, Etching may be performed with an etchant containing hydrofluoric acid. At this time, if the insulating film of the substrate is a two-layer structure in which a silicon nitride film is laminated on a silicon oxide film, the silicon nitride film functions as a stopper for wet etching, so that the insulating film and the semiconductor substrate are etched. Can be prevented. By performing wet etching in this way, the protective film in the region not masked with the resist film (region where the connection hole is to be formed) is removed, and the side surface of the CNT existing immediately below this region is exposed. Similarly, when the connection hole is formed using dry etching, the region other than the region where the connection hole is to be formed on the surface of the protective film may be masked with a resist film and then etched. When dry etching is performed, not only the protective film in the region not masked by the resist film (parts where connection holes are to be formed), but also CNTs are removed, so that the end surfaces (cut surfaces) of the CNTs are formed on the side surfaces of the connection holes. Exposed.

  As described above, if the connection hole is formed by etching only the protective film, the side surface of the CNT is exposed in the connection hole, and if the connection hole is formed by etching the protective film and CNT, The end surface (cut surface) of the CNT is exposed to the surface. This can be used to control the connection form of the source and drain electrodes and the CNT. That is, if the source electrode and the drain electrode are formed with the side surface of the CNT exposed in the connection hole, the source electrode and the drain electrode are connected only to the side surface of the CNT that becomes the channel (side contact structure). Further, if the source electrode and the drain electrode are formed with the end face of the CNT exposed in the connection hole, the source electrode and the drain electrode are connected only to the end face (cut face) of the CNT that becomes the channel (end). Contact structure).

[Formation of source and drain electrodes]
After forming the connection hole in the protective film, the source electrode and the drain electrode are formed. At this time, the source electrode and the drain electrode are formed so that the source electrode and the drain electrode can be electrically connected to the CNT through the connection holes, respectively. The material of the source electrode and the drain electrode is, for example, a metal such as gold, platinum, chromium, titanium, aluminum, palladium, molybdenum, or a semiconductor such as polysilicon. The source electrode and the drain electrode may have a multilayer structure of two or more kinds of metals. For example, the source electrode and the drain electrode may be formed by stacking a gold layer on a titanium layer. The shape of the source and drain electrodes and the interval between the electrodes are not particularly limited, and may be set as appropriate according to the purpose.

  A method of forming the source electrode and the drain electrode in the electrode formation planned region of the protective film is not particularly limited, and a conventionally known method may be appropriately used. For example, a region other than the electrode formation planned region of the protective film is masked with a resist film, a metal such as gold, platinum, titanium, chromium, aluminum, palladium, molybdenum, or a semiconductor such as polysilicon is deposited, and the resist film is removed ( By performing lift-off, the source electrode and the drain electrode can be formed on the protective film. Alternatively, a metal such as gold, platinum, titanium, chromium, aluminum, palladium, molybdenum, or a semiconductor such as polysilicon is deposited on the protective film, and the electrode formation region is masked with a resist film, and then etching is performed. The drain electrode can be formed on the protective film.

[Arrangement of gate electrode]
A method for arranging the gate electrode is not particularly limited, and a conventionally known method may be appropriately used. For example, similarly to the source electrode and the drain electrode, metal or the like may be deposited using photolithography. In addition, when a separately prepared electrode is used as a gate electrode, the electrode may be disposed at a desired position.

  As described above, in the manufacturing method of the present invention, the protective film that covers CNT is formed before the source electrode and the drain electrode are formed on the substrate. Contamination can be suppressed. The clean CNT channel realized in this way makes the best use of the one-dimensional electrical conduction of CNTs and exhibits FET characteristics superior to those of conventional CNT-FETs. Moreover, since the CNT-FET of the present invention manufactured in this way protects CNTs from adsorption of water molecules and the like by the protective film, the hysteresis characteristics can be reduced. That is, according to the manufacturing method of the present invention, the CNT-FET of the present invention stably exhibiting excellent electrical conduction characteristics can be manufactured with good reproducibility without using a special apparatus.

  In order to industrially produce a large amount of the CNT-FET of the present invention, for example, the following may be performed.

  First, a semiconductor substrate having an insulating film having a size capable of producing a plurality of CNT-FETs of the present invention is prepared. The semiconductor substrate is preferably substantially circular and has an orientation flat or notch. In the following description, it is assumed that a substantially circular semiconductor substrate having an orientation flat or notch is prepared.

  Next, the prepared semiconductor substrate is partitioned into a lattice shape to form a region for forming the CNT-FET of the present invention. The same number of CNT-FETs as the number of regions formed are formed from one substrate.

  Next, at least two catalyst layers for growing CNTs are formed on the insulating film of the substrate in each region partitioned in a lattice pattern. The position where the catalyst layer is formed is not particularly limited, but it is preferably formed so as to be located within the region where the source electrode is to be formed and the region where the drain electrode is to be formed as viewed from the top surface of the substrate. By doing in this way, CNT can be formed in the position which can connect a source electrode and a drain electrode easily. Moreover, it is preferable that the positions where the catalyst layer is formed in each region (that is, the positions of the source electrode formation scheduled region and the drain electrode formation planned region) are the same. By doing so, the relationship between the position of the orientation flat or notch of the substrate and the position of the catalyst (the area where each electrode is to be formed) in each region (that is, the direction of the CNT that becomes the channel) can be made uniform. It is.

  Next, the substrate on which the catalyst layer is formed is placed in a CVD furnace, and CNTs are grown so as to connect the catalyst layers in each region of the substrate by chemical vapor deposition. In the case where a plurality of substrates are installed in a CVD furnace, the substrates can be installed with the orientation flats or notches used as marks to align the directions of the substrates.

  Thereafter, in each region, in the same manner as described above, a protective film is formed, a connection hole is formed, a source electrode and a drain electrode are formed, a gate electrode is formed, and each element is separated, thereby the present invention. The CNT-FET can be industrially produced in large quantities. The timing of dividing (dicing) each element is usually performed after confirming the electrical characteristics of each element for each substrate, but is not limited thereto.

  Thus, the CNT-FET of the present invention can be industrially produced in large quantities using a commercially available semiconductor substrate.

  Embodiments of the present invention will be described below with reference to the drawings, but the present invention is not limited to these embodiments.

(Embodiment 1)
The first embodiment shows an example of a back gate type CNT-FET having insulating films on both sides of a semiconductor substrate.

  FIG. 2 is a cross-sectional view showing the configuration of the CNT-FET according to Embodiment 1 of the present invention. In FIG. 2, the CNT-FET 200 includes a semiconductor substrate 110, a source electrode 120, a drain electrode 130, a CNT 140, a protective film 150, a catalyst layer 210, and a gate electrode 220.

  The semiconductor substrate 110 is a substrate made of a semiconductor whose both surfaces are covered with an insulating film 112. The insulating film 112 may have a multilayer structure, for example, a two-layer structure in which a silicon nitride film is stacked on a silicon oxide film.

  The CNT 140 is disposed on the insulating film 112 of the semiconductor substrate 110. Further, the CNT 140 is electrically connected to the source electrode 120 and the drain electrode 130 and functions as a channel of the CNT-FET 200. As will be described later, the CNT 140 of the present embodiment is formed by chemical vapor deposition, and is in contact with the catalyst layer 210. In the present embodiment, the source electrode 120 and the drain electrode 130 may be connected by one CNT 140 as shown in FIG. 2, or may be connected by a plurality of CNTs.

  The protective film 150 is an insulating film that covers the CNT 140. In the present embodiment, protective film 150 covers not only CNT 140 but also the surface of semiconductor substrate 110 on the side where CNT 140 is disposed, and also covers catalyst layer 210 disposed on the same surface. In addition, in the protective film 150, a connection hole for electrically connecting the source electrode 120 and the drain electrode 130 and the CNT 140 is formed immediately below the source electrode 120 and the drain electrode 130 and in a region where the CNT 140 is disposed. Has been.

  The source electrode 120 and the drain electrode 130 are respectively disposed on the protective film 150, and are electrically connected to the CNT 140 through connection holes formed in the protective film 150. The source electrode 120 and the drain electrode 130 may be connected to the side surface of the CNT 140 as shown in FIG. 2 (side contact structure) or may be connected to the end face (end contact structure).

  The gate electrode 220 is disposed on the insulating film 112 on a surface (downward surface in FIG. 2) different from the surface (upward surface in FIG. 2) on which the CNT 140 of the semiconductor substrate 110 is disposed. By applying a voltage to the gate electrode 220, a current (source-drain current) flowing between the source electrode 120 and the drain electrode 130 can be controlled.

  As described above, since the CNT-FET 200 of the present embodiment protects the CNT 140 from the adsorption of water molecules and the like by the protective film 150, the hysteresis characteristics can be reduced.

  Next, a method for manufacturing the CNT-FET 200 of the present embodiment will be described with reference to the flowchart of FIG. 3 and the schematic diagram of FIG.

  First, in step S1100, a semiconductor substrate 110 such as a mirror-polished silicon substrate is prepared.

  Next, in step S1200, insulating films 112 are formed on both surfaces of the prepared semiconductor substrate 110. For example, a mirror-polished silicon substrate is heated in an air atmosphere to form a silicon oxide film (insulating film 112a) on both surfaces of the silicon substrate (semiconductor substrate 110), and then formed on the silicon oxide film by low-pressure CVD. A silicon nitride film (insulating film 112b) may be formed. FIG. 4A is a schematic diagram showing the semiconductor substrate (silicon substrate) 110 after the silicon oxide film 112a is formed on both surfaces. FIG. 4B is a schematic diagram showing the semiconductor substrate (silicon substrate) 110 after the silicon nitride film 112b is further formed on the silicon oxide film 112a. As described above, the insulating film 112 may have a two-layer structure in which the silicon nitride film 112b is stacked over the silicon oxide film 112a.

  Next, in step S1300, a catalyst layer 210 for growing CNTs 140 to be channels is formed on the insulating film 112 of the substrate 110. The position where the catalyst layer 210 is formed is not particularly limited as long as the CNT 140 can be grown so that the source electrode 120 and the drain electrode 130 can be finally connected. For example, in the region where the source electrode 120 is formed and It may be in the region where the drain electrode 130 is formed. For example, the catalyst layer 210 can be formed by forming a silicon thin film, an aluminum thin film, an iron thin film, and a molybdenum thin film in this order on the insulating film 112 by a sputtering method and then etching. FIG. 4C is a schematic diagram showing a state after two catalyst layers 210 are formed on the insulating film 112 (silicon nitride film 112b).

  Next, in step S1400, CNTs 140 are grown from the catalyst layer 210. The method for growing the CNT 140 is not particularly limited, and for example, a low pressure CVD method may be used. At this time, it is preferable to crosslink between the catalyst layers 210 with one or a plurality of CNTs 140. FIG. 4D is a schematic diagram illustrating a state after the CNT 140 is grown from the catalyst layer 210.

  Next, in step S1500, the protective film 150 is formed so as to cover the grown CNTs 140. For example, the protective film 150 made of silicon oxide may be formed on the semiconductor substrate 110 on which the CNTs 140 are grown by catalytic CVD. FIG. 4E is a schematic diagram showing a state after the protective film 150 is formed on the entire surface of the semiconductor substrate 110 on the side where the CNTs 140 are arranged.

  Next, in step S1600, the connection hole 152 is formed in the source electrode formation scheduled region and the drain electrode formation scheduled region of the protective film 150, and a part of the CNT 140 is exposed. For example, after a region other than the region where the connection hole 152 is to be formed on the surface of the protective film 150 made of silicon oxide is masked with a resist film, wet etching may be performed with an etchant containing hydrofluoric acid. At this time, if the insulating film 112 of the substrate has a two-layer structure in which the silicon nitride film 112b is stacked on the silicon oxide film 112a, the semiconductor substrate 110 is etched because the silicon nitride film 112b functions as a wet etching stopper. Can be prevented. By performing wet etching in this manner, the protective film 150 in the region not masked with the resist film (the region where the connection hole 152 is to be formed) is removed, and the side surface of the CNT 140 existing immediately below this region is exposed. FIG. 4F is a schematic diagram illustrating a state after the connection hole 152 is formed in the region where the source electrode 120 is to be formed and the region where the drain electrode 130 is to be formed in the protective film 150.

  Next, in step S1700, the source electrode 120 and the drain electrode 130 are formed on the protective film 150 so as to be electrically connected to the CNT 140 through the connection holes 152, respectively. For example, the source electrode 120 and the drain electrode 130 can be formed by forming an aluminum thin film on the protective film 150 by sputtering and then etching. FIG. 4G is a schematic diagram illustrating a state after the source electrode 120 and the drain electrode 130 are formed. In this example, since the source electrode 120 and the drain electrode 130 are formed in a state where the side surface of the CNT 140 is exposed (see FIG. 4F), the source electrode 120 and the drain electrode 130 are formed on the side surface of the CNT 140 serving as a channel. Will be connected only (side contact structure).

  Finally, in step S1800, the gate electrode 220 is formed on the insulating film 112 on the side of the semiconductor substrate 110 where the CNTs 140 are not disposed. For example, the gate electrode 220 can be formed by forming an aluminum thin film over the insulating film 112 (silicon nitride film 112b) by sputtering and then etching. FIG. 4H is a schematic diagram showing the CNT-FET 200 of the present embodiment after the gate electrode 220 is formed.

  As described above, the manufacturing method of the present embodiment forms the protective film 150 that covers the CNTs 140 to be the channel before moving to the step (S1700) for forming the source electrode 120 and the drain electrode 130. The CNT 140 can be physically and chemically protected in the step of forming the source electrode 120 and the drain electrode 130. As a result, the manufacturing method of the present embodiment can manufacture a CNT-FET having a clean CNT channel that makes the best use of the one-dimensional electrical conduction of CNTs.

(Embodiment 2)
The second embodiment shows an example of a back gate type CNT-FET having a second protective film.

  FIG. 5 is a cross-sectional view showing the configuration of the CNT-FET according to the second embodiment of the present invention. In FIG. 5, the CNT-FET 300 includes a semiconductor substrate 110, a source electrode 120, a drain electrode 130, a CNT 140, a protective film 150, a catalyst layer 210, a gate electrode 220, and a second protective film 310. The same components as those in the CNT-FET according to the first embodiment are denoted by the same reference numerals, and description of overlapping portions is omitted.

  The second protective film 310 covers the protective film 150 and part of the source electrode 120 and the drain electrode 130. The material of the second protective film 310 is not particularly limited as long as it has an insulating property. For example, inorganic compounds such as silicon oxide, silicon nitride, aluminum oxide, and titanium oxide, and organic compounds such as acrylic resin and polyimide are used. It is. A method for manufacturing the second protective film 310 is not particularly limited. For example, after the CNT-FET of Embodiment 1 is manufactured, the second protective film 310 is formed on the protective film 150 and the source electrode 120 and the drain electrode 130. The film 310 may be formed and etched so that part of the source electrode 120 and the drain electrode 130 is exposed.

  Since the CNT-FET of the present embodiment has the second protective film 310 that can also function as a sealing film, in addition to the effects of the first embodiment, the characteristics can be further stabilized.

(Embodiment 3)
In the first and second embodiments, an example of a back gate type CNT-FET having an insulating film on both surfaces of the semiconductor substrate has been shown, but in the third embodiment, a back gate type having an insulating film only on one surface of the semiconductor substrate. An example of the CNT-FET is shown.

  FIG. 6 is a cross-sectional view showing the configuration of the CNT-FET according to Embodiment 3 of the present invention. In FIG. 6, the CNT-FET 400 includes a semiconductor substrate 110, a source electrode 120, a drain electrode 130, a CNT 140, a protective film 150, and a catalyst layer 210. The same components as those in the CNT-FET according to the first embodiment are denoted by the same reference numerals, and description of overlapping portions is omitted.

  The semiconductor substrate 110 is a substrate made of a semiconductor in which only the surface on which the CNTs 140 are disposed (the upward surface in FIG. 6) is covered with the insulating film 112. The insulating film 112 may have a multilayer structure, for example, a two-layer structure in which a silicon nitride film is stacked on a silicon oxide film. Since the surface on which the CNT 140 is not disposed (the downward surface in FIG. 6) is not covered with an insulating film, in the CNT-FET 400 of the present embodiment, the semiconductor portion of the semiconductor substrate 110 acts as a gate electrode as it is. A method for covering only one surface of the semiconductor substrate 110 with the insulating film 112 is not particularly limited. For example, one of the insulating films formed on both surfaces of the semiconductor substrate 110 may be removed.

  As described above, the CNT-FET of the present embodiment can act as a gate electrode on the semiconductor substrate 110 as it is, so that in addition to the effect of the first embodiment, the gate voltage is effectively reduced. Can be applied.

(Embodiment 4)
In the first to third embodiments, an example of a back gate type CNT-FET is shown, but in the fourth embodiment, an example of a side gate type CNT-FET is shown.

  FIG. 7 is a cross-sectional view showing a configuration of a CNT-FET according to Embodiment 4 of the present invention. 7A and 7B, the CNT-FETs 500a and 500b include a semiconductor substrate 110, a source electrode 120, a drain electrode 130, a CNT 140, a protective film 154, a catalyst layer 210, and a gate electrode 510. The same components as those in the CNT-FET according to the first embodiment are denoted by the same reference numerals, and description of overlapping portions is omitted.

  The protective film 154 is an insulating film that covers the CNT 140 similarly to the protective film of the CNT-FETs of the first to third embodiments. However, the protective film 154 is used not only for the connection holes for the source electrode 120 and the drain electrode 130 but also for the gate electrode 510. The connection hole is also formed.

  The gate electrode 510 is disposed on the protective film 154 and is connected to the semiconductor substrate 110 through a connection hole formed in the protective film 154. The gate electrode 510 may be formed so as to be connected to the insulating film 112 of the semiconductor substrate 110 as shown in FIG. 7A, or is made of a semiconductor of the semiconductor substrate 110 as shown in FIG. You may form so that it may connect to a part. By applying a voltage to the gate electrode 510, the current flowing between the source electrode 120 and the drain electrode 130 can be controlled.

  The CNT-FETs 500a and 500b according to the present embodiment can be manufactured in substantially the same procedure as the CNT-FET 200 according to the first embodiment. That is, when the connection hole is formed in the protective film 154 (see step S1600 in FIG. 3), not only the connection hole for the source electrode and the drain electrode but also the connection hole for the gate electrode is formed to form the gate electrode 510. In this case (see step S1800 in FIG. 3), the gate electrode 510 may be formed above the connection hole for the gate electrode.

  As described above, since the CNT-FETs 500a and 500b of the present embodiment protect the CNT 140 from adsorption of water molecules and the like by the protective film 150, as in the CNT-FET of the first embodiment, the hysteresis characteristics are improved. Can be reduced.

  In addition, the CNT-FETs 500a and 500b of the present embodiment do not use the back surface of the semiconductor substrate as an electrode, and therefore can be manufactured without worrying about the state of the back surface of the semiconductor substrate. In the back gate type CNT-FET, the back surface of the semiconductor substrate is used as an electrode. Therefore, when the semiconductor substrate is processed on a stage or the like, the gate insulating film on the back surface (the surface in contact with the stage) of the semiconductor substrate is scratched or soiled. If it is attached, the yield may decrease. On the other hand, in the side-gate CNT-FET of this embodiment, the back surface of the semiconductor substrate functions only as a support substrate, so that the yield does not decrease even if the back surface of the semiconductor substrate is scratched or soiled.

(Embodiment 5)
In the fifth embodiment, an example of a side gate type CNT-FET having a diffusion layer in a semiconductor substrate is shown.

  FIG. 8 is a cross-sectional view showing the configuration of the CNT-FET according to the fifth embodiment of the present invention. In FIG. 8, the CNT-FET 600 includes a semiconductor substrate 610, a source electrode 120, a drain electrode 130, a CNT 140, a protective film 154, a catalyst layer 210, and a gate electrode 510. The same components as those of the CNT-FET according to the fourth embodiment are denoted by the same reference numerals, and description of overlapping portions is omitted.

  The CNT 140 exhibits n-type semiconductor characteristics and functions as an n-type channel of the CNT-FET 600. A method for manufacturing a channel exhibiting n-type semiconductor characteristics is not particularly limited. For example, the protective film 154 may be a silicon nitride film (see, for example, JP-A-2006-222279).

  The semiconductor substrate 610 is a substrate made of an n-type semiconductor and has an insulating film 112 on the surface thereof. Further, the semiconductor substrate 610 has a p-type diffusion layer 620 in a region where the CNT 140 is disposed. As a method for manufacturing a semiconductor substrate having a p-type diffusion layer, a conventionally known method such as an ion implantation method may be appropriately used.

  Note that although an example of a configuration including an n-type semiconductor substrate having a p-type diffusion layer and an n-type channel has been described in this embodiment, a p-type semiconductor substrate having an n-type diffusion layer, A similar effect can be obtained with a configuration having a p-type channel.

  Since the CNT-FET 600 of the present embodiment has a diffusion layer directly under the CNT, in addition to the effects of the fourth embodiment, the sensitivity of the CNT can be improved. For example, when the antibody is immobilized on the gate electrode and the CNT-FET is used as a biosensor, the CNT-FET of the present embodiment has a sensitivity of CNT (current change rate with respect to the antigen-antibody reaction generated on the gate electrode). ) Is high, the antigen (substance to be detected) can be detected with high sensitivity. Further, the CNT-FET 600 of this embodiment can also adjust the sensitivity characteristics of the CNTs by adjusting the impurity concentration of the diffusion layer.

  The present invention can produce a CNT-FET stably exhibiting excellent electrical conduction characteristics with good reproducibility, and is useful for the production of integrated devices and sensors including the CNT-FET.

The schematic diagram which shows an example of a structure of CNT-FET of this invention Sectional drawing which shows the structure of CNT-FET of Embodiment 1 Flowchart showing the method of manufacturing the CNT-FET of the first embodiment Schematic diagram showing a method of manufacturing the CNT-FET of the first embodiment Sectional drawing which shows the structure of CNT-FET of Embodiment 2. Sectional drawing which shows the structure of CNT-FET of Embodiment 3. Sectional drawing which shows the structure of CNT-FET of Embodiment 4. Sectional drawing which shows the structure of CNT-FET of Embodiment 5

Explanation of symbols

100, 200, 300, 400, 500a, 500b, 600 CNT-FET
110, 610 Semiconductor substrate 112 Insulating film 112a Silicon oxide film 112b Silicon nitride film 120 Source electrode 130 Drain electrode 140 CNT
150, 154 Protective film 152 Connection hole 210 Catalyst layer 220, 510 Gate electrode 310 Second protective film 620 Diffusion layer

Claims (11)

A semiconductor substrate having an insulating film;
Carbon nanotubes disposed on the insulating film;
A protective film covering the carbon nanotube;
A source electrode and a drain electrode that are respectively disposed on the protective film and electrically connected to the carbon nanotubes via connection holes formed in the protective film;
A field effect transistor having a carbon nanotube as a channel.   The field effect transistor according to claim 1, wherein the source electrode and the drain electrode are connected only to side surfaces of the carbon nanotube.   The field effect transistor according to claim 1, wherein the insulating film has a two-layer structure in which a silicon nitride film is stacked on a silicon oxide film.   The field effect transistor according to claim 1, wherein the protective film includes silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, or titanium oxide. Preparing a semiconductor substrate having an insulating film;
Disposing carbon nanotubes on the insulating film of the semiconductor substrate;
Forming a protective film on the carbon nanotube;
Forming a connection hole in each of a source electrode formation planned region and a drain electrode formation planned region of the protective film to expose a part of the carbon nanotube;
Forming a source electrode on the source electrode formation planned region of the protective film so that it can be electrically connected to the carbon nanotube through the connection hole;
Forming a drain electrode on the drain electrode formation planned region of the protective film so that it can be electrically connected to the carbon nanotube via the connection hole;
A method for manufacturing a field effect transistor using a carbon nanotube as a channel, comprising: The step of arranging the carbon nanotubes comprises:
Forming at least two catalyst layers on the insulating film of the semiconductor substrate;
Growing carbon nanotubes by chemical vapor deposition so as to connect the catalyst layers;
The manufacturing method of the field effect transistor of Claim 5 containing this.   6. The method of manufacturing a field effect transistor according to claim 5, wherein the insulating film has a two-layer structure in which a silicon nitride film is laminated on a silicon oxide film.   The field effect transistor manufacturing method according to claim 7, wherein the connection hole is formed by wet etching.   The method for manufacturing a field effect transistor according to claim 8, wherein the etching solution used for the wet etching includes hydrofluoric acid.   6. The method of manufacturing a field effect transistor according to claim 5, wherein the protective film includes silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, or titanium oxide. Providing a substantially circular semiconductor substrate having an orientation flat or notch and having an insulating film;
Partitioning the semiconductor substrate into a grid and forming a plurality of regions for forming one field effect transistor;
Forming at least two catalyst layers on the insulating film of the semiconductor substrate in each of the regions;
In each of the regions, growing carbon nanotubes from a catalyst layer by chemical vapor deposition and arranging the carbon nanotubes to connect the catalyst layers;
Forming a protective film on the carbon nanotubes in each of the regions;
In each of the regions, forming a connection hole in each of the source electrode formation planned region and the drain electrode formation planned region of the protective film, exposing a part of the carbon nanotubes;
In each of the regions, forming a source electrode on the source electrode formation planned region of the protective film so that it can be electrically connected to the carbon nanotube through the connection hole;
Forming a drain electrode on the drain electrode formation planned region of the protective film so as to be electrically connected to the carbon nanotube via the connection hole in each of the regions;
A method for manufacturing a field effect transistor using a carbon nanotube as a channel, comprising:

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