JP2009225516A - Capacitor charging/discharging monitoring control device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a capacitor charging/discharging monitoring control device which monitors two voltage of an initialization setting voltage and a full-charging detection setting voltage of a capacitor by using one comparator. <P>SOLUTION: In the capacitor charging/discharging monitoring control device used for a load which requires power in a periodical cycle time, the device includes: a bypass means Trn of a charging current of the capacitor; a first reference voltage setting means (Vref full) which sets a first reference voltage to the capacitor; a second reference voltage setting means (Vref ini) which sets a second reference voltage to the capacitor; a first latch circuit 53 which latches a bypass operation signal for operating the bypass means by output signals from these means, and outputs it as a first monitoring signal; and a second latch circuit 54 which latches a bypass operation signal at the time when the second reference voltage setting means is inputted into a comparator CMPn, and outputs it as a second monitoring signal. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention monitors a charge voltage of an electric double layer capacitor that supplies power to a load that requires power in a periodic cycle time, and controls charge / discharge of the capacitor based on the monitoring result It is about.

  In recent years, electric double layer capacitors capable of charging and discharging a large current have attracted attention. An electric double layer capacitor is a capacitor that uses an electric double layer formed by the polarization of ions at the interface between the electrode and the electrolyte. It can charge a large capacitance compared to conventional capacitors, and can be charged and discharged quickly. Is possible and its application is expected. Applications of the electric double layer capacitor include memory backup, electric vehicle power assist, and power storage battery replacement, and are widely studied from small capacity products to large capacity products. The present applicant, for example, connects a plurality of electric double layer capacitor cells in series, and a capacitor power storage device configured in combination with an electronic circuit that performs charging / discharging while monitoring each capacitor cell with a parallel monitor, as an ECS (Energy Capacitor). System) or ECaSS (Energy Capacitor Systems) (registered trademark). Here, the parallel monitor is connected between the terminals of each electric double layer capacitor of the capacitor bank in which a plurality of electric double layer capacitors are connected in series. When the charge voltage of the capacitor bank exceeds the set value of the parallel monitor, the charge current is It is a device that bypasses.

The capacitor bank with the parallel monitor described above bypasses the charging current so that the charging voltage of the capacitor bank does not rise above a set value when charging, so that all electric double layer capacitors in the capacitor bank are kept constant. The battery is evenly charged up to a set voltage, and the storage capacity of the electric double layer capacitor can be exhibited almost 100%. Therefore, the parallel monitor can be used up to the full withstand voltage by equalizing the maximum voltage, preventing backflow, detecting and controlling the end-of-charge voltage, etc., even when there are variations in capacitor characteristics and residual charge. As such, it has an extremely important role and is an indispensable device for effective use of energy density. Such a parallel monitor is disclosed in Patent Document 1 (Japanese Patent Laid-Open No. 2001-186681) and the like.
Japanese Patent No. 2001-186681

  The parallel monitor limits the charging voltage to a predetermined value (within a withstand voltage range) by bypassing the charging current with a predetermined reference voltage, and reduces variations in the charging voltage. The device described in Patent Document 1 has separate comparators 12 and 13 for initialization and full charge detection as shown in FIG. In FIG. 2, the initialization comparator 12 operates the transistor Tr connected in parallel to the capacitor C so as to bypass the charging current with the first set voltage Vref ini. The full-charge detection comparator 13 is used as voltage detection means for detecting a second set voltage Vref full that determines the arrival of full charge higher than the first set voltage Vref ini.

As described above, in the parallel monitor, it is necessary to monitor the capacitor by using two voltages of the setting voltage Vref ini for initialization and the setting voltage Vref full for detection of full charge, for example, the power charged in the capacitor May be used for instantaneous peak cut. That is, the capacitor is used to supplement instantaneous power to a load of a construction machine such as a crane or a transporter that requires electric power with a periodic cycle time, or a hybrid vehicle.

  In a system using a capacitor for the above-described applications, the capacitor voltage is monitored and maintained at an initial setting voltage Vref ini--for example, 2.3 V--that is usually a voltage lower than the rated voltage of the capacitor. To do. And it is set as the state which can discharge power running electric power with respect to load, or can charge regenerative electric power from load. On the other hand, when the capacitor voltage is monitored at the full charge detection setting voltage Vref full--for example, 2.7 V--, which is the rated voltage of the capacitor, and the capacitor voltage reaches the full charge detection setting voltage Vref full. Provides feedback to the controller of the main power supply that the capacitor voltage has reached the full charge voltage.

  By the way, in the parallel monitor in the case of using the capacitor to supplement the instantaneous power to the load as described above, in order to monitor two voltages, the setting voltage for initialization Vref ini and the setting voltage for full charge detection Vref full. Two comparators are required, and there is a problem that the circuit becomes complicated and the cost increases.

  In order to solve the above-described problem, an invention according to claim 1 is directed to a capacitor charge / discharge monitoring control apparatus for monitoring and controlling charge / discharge of a capacitor used for a load that requires power in a periodic cycle time. Bypass means for bypassing a charging current; first reference voltage setting means for setting a first reference voltage for the capacitor; second reference voltage setting means for setting a second reference voltage for the capacitor; and the first reference voltage Either the setting means or the second reference voltage setting means is input, the charge voltage of the capacitor is compared with the first reference voltage or the second reference voltage, and it is determined that these have been reached, and the bypass means is Comparison means for performing a bypass operation and outputting a bypass operation signal, and a bypass operation when the first reference voltage setting means is input to the comparison means The first latch circuit that latches the signal and outputs it as the first monitoring signal, and the bypass operation signal when the second reference voltage setting means is input to the comparison means are latched and output as the second monitoring signal And a second latch circuit.

  According to a second aspect of the present invention, in the capacitor charge / discharge monitoring and control device according to the first aspect, which of the first reference voltage setting means and the second reference voltage setting means is input to the comparison means? A timer circuit for time-sharing control is provided.

  According to a third aspect of the present invention, in the capacitor charge / discharge monitoring control apparatus according to the second aspect, the timer circuit also performs time-division control on the first latch circuit and the second latch circuit.

  According to the capacitor charge / discharge monitoring and control apparatus according to the embodiment of the present invention, one comparator (in order to monitor two voltages, the capacitor setting voltage Vref ini and the full charge detection setting voltage Vref full, is used. Since the comparison means is used in a time-sharing manner, it is not necessary to provide two comparators, cost can be suppressed, and the circuit can be simplified.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a schematic configuration of an electrical system in which a capacitor charge / discharge monitoring control apparatus according to an embodiment of the present invention is used. Such an electric system is an electric system such as a construction machine such as a crane or a transporter that requires electric power in a periodic cycle time, or a hybrid vehicle. In FIG.
Reference numeral 10 denotes a main control unit, 20 denotes a main power supply, 30 denotes a load, 40 denotes a capacitor charge / discharge monitoring control device, and C1, C2,... Cm denote electric double layer capacitors.

  The electric system is operated by a load 30 such as a motor, and the load 30 requires power in a periodic cycle time. The electric power for the load 30 is supplied with the electric power of the main power supply 20 and the electric power discharged from the electric double layer capacitors C1, C2,. Here, the electric double layer capacitors C1, C2,... Cm are used to supplement the instantaneous power of the load 30. Further, the electric double layer capacitors C1, C2,... Cm are controlled to be charged with power from the main power source 20 and also to be charged with regenerative power of the load 30.

  Capacitor charge / discharge monitoring and control device 40 for monitoring the charging voltage of each capacitor in each electric double layer capacitor C1, C2,... Cm and protecting the capacitor by bypassing the charging current to the capacitor as necessary. Is provided. The capacitor charge / discharge monitoring control device 40 is also configured to issue a signal for informing the main power source 20 of the bypass operation of the charging current. Further, the capacitor charge / discharge monitoring control device 40 receives a setting signal from the main control unit 10 in order to perform an operation according to the characteristics required by the load 30.

  The main control unit 10 is configured to perform main control of the electric system, and at least a load control signal for the load 30, a main power control signal for the main power supply 20, and a monitoring control device setting signal for the capacitor charge / discharge monitoring control device 40. Send to the configuration and control each one. The load control signal is a signal for controlling the output of the load 30 such as a motor, and the main power supply control signal is a signal for controlling the main power supply 20 according to the output of the load 30 and the like. The monitoring control device setting signal is a signal used to set the monitoring duty ratio in the capacitor charge / discharge monitoring control device 40.

  In this electric system, the electric power charged in the electric double layer capacitors C1, C2,... Cm is used for instantaneous peak cut. That is, the capacitor is used to supplement instantaneous power to a load of a construction machine such as a crane or a transporter that requires electric power with a periodic cycle time, or a hybrid vehicle.

  In the capacitor charge / discharge monitoring control device 40 of such an electric system, in a state where the load 30 does not require power, the initialization set voltage Vref ini − which is a voltage lower than the rated voltage of each capacitor, for example, 2 Monitor and maintain capacitor voltage at 3V-. And it is set as the state which can discharge power running electric power with respect to load, or can charge regenerative electric power from load.

  On the other hand, the capacitor charge / discharge monitoring control device 40 monitors the capacitor voltage at the full charge detection set voltage Vref full--for example, 2.7 V--that is the rated voltage of the capacitor, and uses this full charge detection set voltage Vref full. When the capacitor voltage has reached, the main power supply 20 is fed back that the capacitor voltage has reached the full charge voltage.

  Next, the capacitor charge / discharge monitoring control device 40 will be described in more detail. FIG. 2 is a diagram showing a capacitor charge / discharge monitoring control apparatus according to an embodiment of the present invention. The capacitor charge / discharge monitoring control device 40 shown in FIG. 2 shows the one connected to Cn among the electric double layer capacitors C1, C2,... Cm, but all the electric double layer capacitors C1, C2, .. The capacitor charge / discharge monitoring control device 40 connected to Cm has the same configuration.

In FIG. 2, 51 is a timer setting circuit, 52 is a timer circuit, 53 is a first latch circuit, 5
4 is a second latch circuit, SW1 and SW2 are switches, Vref full is a first reference voltage (full charge detection setting voltage), Vref ini is a second reference voltage (initialization setting voltage), CMPn is a comparator, and Trn is Transistors Cn represent electric double layer capacitors, respectively.

  The first reference voltage (full charge detection setting voltage) Vref full corresponds to the rated voltage of the electric double layer capacitor Cn, and the second reference voltage (initialization setting voltage) Vref ini corresponds to the initialization voltage of the electric double layer capacitor Cn. Each reference voltage is input to the comparator CMPn by the on / off operation of the switches SW1 and SW2. The switches SW1 and SW2 are turned on / off by an on / off signal from the timer circuit 52.

  The switch SW1 is turned on when the first on / off signal from the timer circuit 52 is High, and is turned off when it is Low. The switch SW2 is turned on when the second on / off signal from the timer circuit 52 is High, and is turned off when it is Low. As described above, in the capacitor charge / discharge monitoring control device 40 of the present embodiment, the first reference voltage Vref full and the second reference voltage Vref ini input by the timer circuit 52 are switched to control one comparator CMPn in a time division manner. Thus, it is not necessary to provide two comparators for monitoring two set voltages, and the cost can be suppressed and the circuit can be simplified.

  FIG. 3 is a diagram showing the timing of the first on / off signal and the second on / off signal generated by the timer circuit 52. In FIG.

  As shown in FIG. 3, when the first on / off signal is high for the time T1, the second on / off signal is low. Then, when the second on / off signal for the next T2 time is High, the second on / off signal is Low. The timer circuit 52 repeats this alternately and periodically.

  The timer setting circuit 51 can set a duty ratio between a time T1 when the first on / off signal in the timer circuit 52 is in a high state and a time T2 when the second on / off signal is in a high state. It has become. The setting of the duty ratio in the timer setting circuit 51 is determined by the main control unit 10 according to the power supply status of the main power supply 20 and the operation status of the load 30. The main control unit 10 transmits the determined duty ratio setting to the timer setting circuit 51 as a monitoring control device setting signal. Receiving this, the timer setting circuit 51 sets the duty ratio in the timer circuit 52.

  When the first reference voltage (full charge detection setting voltage) Vref full is input, the comparator CMPn compares the voltage of the electric double layer capacitor Cn with the first reference voltage Vref full, and compares the electric double layer capacitor Cn. When the voltage reaches the first reference voltage Vref full, the transistor Trn is operated to bypass the current flowing into the electric double layer capacitor Cn to the transistor Trn, and the bypass operation signal is sent to the first latch circuit 53 and the second latch. The data is transmitted to the circuit 54.

The comparator CMPn compares the voltage of the electric double layer capacitor Cn with the second reference voltage Vref ini when the second reference voltage (initialization setting voltage) Vref ini is input, and the electric double layer capacitor When the voltage of Cn reaches the second reference voltage Vref ini, the transistor Trn is operated to bypass the current flowing into the electric double layer capacitor Cn to the transistor Trn, and the bypass operation signal is sent to the first latch circuit 53, the second The data is transmitted to the latch circuit 54.

  The first latch circuit 53 latches the bypass operation signal when the first on / off signal from the timer circuit 52 is High, and outputs the latched bypass operation signal as a first monitoring signal. The second latch circuit 54 latches the bypass operation signal when the second on / off signal from the timer circuit 52 is High, and outputs the latched bypass operation signal as a second monitoring signal. The first monitoring signal is a signal for informing the main power supply 20 whether the electric double layer capacitor Cn is at the fully charged voltage (rated voltage), and the second monitoring signal is whether the electric double layer capacitor Cn is at the initialization voltage. It becomes. The first monitoring signal and the second monitoring signal as described above are input to the main power supply 20 and used for charging control of the electric double layer capacitors C1, C2,. In the present embodiment, since the main power supply 20 is controlled by such two types of monitoring signals, the electric double layer capacitors C1, C2,. Can be operated safely.

  As described above, according to the capacitor charge / discharge monitoring control apparatus of the present invention, one comparator (comparison means) is used to monitor two voltages, the capacitor initialization voltage Vref ini and the full charge detection setting voltage Vref full. Therefore, it is not necessary to provide two comparators, the cost can be suppressed, and the circuit can be simplified.

It is a figure which shows schematic structure of the electric system with which the capacitor charging / discharging monitoring control apparatus which concerns on embodiment of this invention is used. It is a figure which shows the capacitor charging / discharging monitoring control apparatus which concerns on embodiment of this invention. It is a figure which shows the timing of the on / off signal which the timer circuit of the capacitor charging / discharging monitoring control apparatus which concerns on embodiment of this invention generate | occur | produces.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Main control part, 20 ... Main power supply, 30 ... Load, 40 ... Capacitor charge / discharge monitoring control device, 51 ... Timer setting circuit, 52 ... Timer circuit, 53 ... .First latch circuit, 54... Second latch circuit

Claims (3)

In a capacitor charge / discharge monitoring and control device for monitoring and controlling charge / discharge of a capacitor used for a load that requires power in a periodic cycle time,
Bypass means for bypassing the charging current of the capacitor;
First reference voltage setting means for setting a first reference voltage for the capacitor;
Second reference voltage setting means for setting a second reference voltage for the capacitor;
Either the first reference voltage setting means or the second reference voltage setting means is input, the charge voltage of the capacitor is compared with the first reference voltage or the second reference voltage, and it is determined that these have been reached. A comparator for bypassing the bypass means and outputting a bypass operation signal; and a bypass operation signal when the first reference voltage setting means is input to the comparator means is latched and output as a first monitoring signal A first latch circuit that
A second latch circuit that latches a bypass operation signal when the second reference voltage setting means is input to the comparison means, and outputs it as a second monitoring signal;
A capacitor charge / discharge monitoring and control device comprising: 2. The capacitor charge / discharge monitoring according to claim 1, further comprising a timer circuit for time-division controlling whether the first reference voltage setting means or the second reference voltage setting means is input to the comparison means. Control device. 3. The capacitor charge / discharge monitoring control apparatus according to claim 2, wherein the timer circuit also performs time-sharing control of the first latch circuit and the second latch circuit.

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