JP2009116719A - Microcomputer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem wherein relatively great electric power is consumed because a CPU wakes up periodically to carry out an operation for monitoring an input and output circuit, in the prior art, although a microcomputer having a sleep operation mode to make the CPU sleep is known. <P>SOLUTION: This microcomputer includes the CPU for receiving a supply of a CPU clock to execute a command, the input and output circuit for receiving a CPU processing request from an external circuit, and a monitoring control circuit for carrying out a monitoring operation of accessing the input and output circuit, in a sleep period of the CPU, to detect the CPU processing request. The CPU stops the execution of the command in the sleep period. The monitoring control circuit is operated in the sleep period, and releases the sleep period, when detecting the CPU processing request. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a microcomputer.

  A microcomputer having a low power consumption mode such as a sleep mode and incorporating a nonvolatile memory is known. In recent years, various controls in automobiles have been computerized, and many microcomputers are used in vehicles because many processes are performed in a distributed manner. In particular, a microcomputer used in a vehicle and connected to an in-vehicle communication system is known as a body control microcomputer. The various control processes started by the body control microcomputer do not always function, but are processed when an event occurs, and the time zone between events is in a wait state (the microcomputer is in a sleep state) It has become. The microcomputer recognizes the occurrence of an event by referring to the state (status) of the external function block, and performs a processing operation.

  In recent years, microcomputers with built-in flash memory are often used to control various electronic devices in automobiles. In recent years, many semiconductor LSIs (Large Scale Integrations) have been applied to this application, and thus there is an increasing demand for low power consumption. Microcomputers for body control for automobiles rarely operate at all times, and constitute a control system for the purpose of performing distributed processing. Since the microcomputer for body control is mainly controlled to perform periodic processing, the low power consumption mode is often used while the processing is not performed. In addition, since it is used in an environment where the period during which processing is not performed is longer than the period during which normal operation (program processing operation) is performed, it would be very beneficial if power consumption during the period during which processing was not performed could be reduced. is there.

  Japanese Patent Laid-Open No. 11-288409 (see Patent Document 1) describes a microcomputer having a low power consumption mode for realizing low power consumption. In the transition from the low power consumption mode to the normal operation, the initial operation program is executed from the internal RAM (Random Access Memory) instead of the internal flash memory. In the low power consumption mode, there is an alternative means for performing program execution processing by flash EEPROM (Electronically Erasable and Programmable Read Only Memory) by program execution processing by built-in RAM.

  Japanese Patent Laying-Open No. 2002-63150 (see Patent Document 2) discloses a micro that cancels a sleep mode by measuring time with a timer that uses an input pulse as a low-frequency clock and periodically determining the level of an external terminal. Computer is listed. In sleep mode (when the CPU is stopped. Internally, only the low-frequency oscillator and some peripheral circuits are operating), the internal counter or timer operates with the clock supplied from the low-frequency oscillator 5 The sleep mode is periodically canceled using an internal interrupt signal or the like. At this time, a program (instruction) is read from a preset interrupt vector address (internal RAM area) and transferred to the CPU. The CPU executes the transferred program (instruction), reads the state of the peripheral IO (flag: status register), and requires CPU processing (peripheral IO operation request: operation mode change, or CPU processing request: calculation Processing, branching, data R / W processing, etc.). When the CPU recognizes that the CPU processing is necessary by reading the value of the peripheral IO register, the CPU performs branch control to branch to the address (address) storing the program necessary for the processing. If it is determined that the CPU processing is unnecessary, the timer or counter for setting the sleep mode state period is again initialized and restarted. At the same time, the operation of the CPU is stopped, and the mode is shifted to the sleep mode again.

  When there is no wakeup signal from an external circuit (external circuit is an external module such as keyless entry or lamp control), the CPU uses an internal wakeup signal from the oscillation means after a sleep period of several ms to several hundred ms. It is activated. Then, after waiting for the setup time of the flash memory, the state of the connected external circuit is monitored (analog / digital input value determination, etc.). If there is no processing request to the CPU, the process shifts again to a sleep period of several ms to several hundred ms, and if there is a processing request to the CPU, a processing program is executed. When there is a wake-up signal from the external circuit, the CPU is activated during the sleep period and performs processing such as communication with the external circuit. As the memory, a flash memory is used in consideration of a small variety of products and reprogramming after shipment. When only the mask ROM is used as the memory, the setup time can be shortened, but there is a demerit that it is not possible to develop a small variety of products and reprogram after shipping.

JP 11-288409 A JP 2002-63150 A

  The conventional microcomputer described in Patent Document 2 supplies a clock even during the sleep period, and measures the time for canceling the sleep period using a timer circuit or a counter circuit. During the sleep period, the clock operating current and the timer or counter circuit operating current are consumed. In addition, when the conventional microcomputers described in Patent Documents 1 and 2 wake up from the sleep state to the normal state, the built-in program memory is activated, and the external IO state is set by the CPU that executes the instruction. Check.

  In general, a CPU includes many functions. When a process for confirming an external IO state is performed, a large number of functional blocks (logic circuits operate: program counter circuit, memory control circuit, IR (Instruction) (Register) circuit, instruction decode circuit, timing generation circuit, instruction execution circuit, register access circuit, data bus circuit, arithmetic processing control circuit for register content check, arithmetic circuit, arithmetic result judgment processing control circuit, arithmetic result judgment processing control , Branch processing control circuit, etc.) operate. The power consumption at this time can be generally expressed in proportion to the size of [F (operating frequency) × C (operating load capacity (proportional to the number of gates)) × V (operating voltage)]. Therefore, the operation for confirming the external IO state also requires power consumption equivalent to the normal operation.

  For this reason, the conventional microcomputer wakes up from the sleep operation mode of the CPU and confirms the external IO state, and thus has the disadvantage of requiring the same power as when the CPU is in the normal operation mode. . In general, in body microcomputer control, control is performed in which an external IO state that rises intermittently from a sleep state is observed, and when the external IO does not change, the sleep state is restored again. The conventional microcomputer has a drawback that the starting power of the program memory when waking up from the sleep state and the power consumption necessary for executing the program by the CPU require the same power as in the normal operation. Further, the microcomputer disclosed in Patent Document 2 has a problem in that power necessary for clock generation and supply is consumed because the clock count is used to count the sleep period in the sleep state.

  [Means for Solving the Problems] will be described below using the numbers and symbols used in [Best Mode for Carrying Out the Invention]. These numbers and symbols are added in parentheses in order to clarify the correspondence between the description of [Claims] and [Best Mode for Carrying Out the Invention]. However, these numbers and symbols should not be used for the interpretation of the technical scope of the invention described in [Claims].

  In the microcomputer (11) according to the present invention, the CPU (40) receives a CPU clock and executes instructions. The input / output circuits (32 to 38) receive CPU processing requests from the external circuits (20 to 24). The monitoring control circuit (30) accesses the input / output circuits (32 to 38) during the sleep period of the CPU (40) and performs a monitoring operation for detecting a CPU processing request. The CPU (40) stops executing instructions during the sleep period. The supervisory control circuit (30) operates during the sleep period and cancels the sleep period when a CPU processing request is detected.

  The present invention includes a monitoring control circuit (30) that performs a monitoring operation for accessing the input / output circuits (32 to 38) and detecting a CPU processing request. Therefore, the CPU (40) does not need to wake up periodically during the sleep period, access the input / output circuits (32 to 38), and execute a program for detecting a CPU processing request. Therefore, the power consumption required for starting and operating the CPU (40) for executing the program and the flash memory for storing the program is not required, and the power consumption can be reduced.

  According to the present invention, the power consumption of the microcomputer can be reduced.

  Embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a vehicle. In FIG. 1, a vehicle 10 is equipped with a microcomputer 11. The microcomputer 11 and an external circuit arranged outside thereof constitute an in-vehicle communication system. The microcomputer 11 has a plurality of input / output terminals 12 to 18 and a vibrator terminal 19. The input / output terminals 12 to 18 are connected to the illustrated external circuits 20 to 24 or an external circuit (not shown). Connected to the input / output terminal 12 is a sensor interface circuit 20 that transmits a sensor signal such as a steering sensor to the microcomputer 11 as a digital signal. A pulse input interface circuit 21 for inputting a pulse to the microcomputer 11 is connected to the input / output terminal 13. Connected to the input / output terminal 14 is a switch input interface circuit 22 that notifies the microcomputer 11 that a switch has been input and that a failure diagnosis is to be performed. The input / output terminal 15 is connected to an analog input interface circuit 23 that transmits sensor signals such as a pressure sensor, a position sensor, and an acceleration sensor to the microcomputer 11 as analog values. An external interrupt signal notified from the in-vehicle communication system is input to the input / output terminal 16. A voltage monitor signal notified from the in-vehicle communication system is input to the input / output terminal 17. A transceiver 24 for transmitting and receiving data is connected to the input / output terminal 18 via an in-vehicle communication bus (CAN (Controller Area Network) or LIN (Local Interconnect Network)) of the in-vehicle communication system. The vibrator terminal 19 is schematically shown by one symbol, but in detail, has two terminals and is connected to a crystal vibrator (not shown). In addition, the microcomputer 11 has a power supply terminal (not shown) and is supplied with power.

  FIG. 2 shows a configuration diagram of main blocks of the microcomputer. In FIG. 2, the microcomputer 11 has a CPU 40 that executes program instructions. Input / output circuits 32 to 38 are connected to the input / output terminals 12 to 18. The input / output circuits 32 to 38 receive the input signal of the microcomputer 11 and hold the output signal. The input / output circuit 32 receives a digital sensor signal input from the input / output terminal 12. The input / output circuit 33 receives the pulse input from the input / output terminal 13 and transfers it to the timer / counter circuit 42. The input / output circuit 34 receives a switch input signal input from the input / output terminal 14. The input / output circuit 35 receives an analog signal input from the input / output terminal 15 and transfers the analog signal to the analog / digital conversion circuit 43. The input / output circuit 36 receives an external interrupt signal input from the input / output terminal 16. The input / output circuit 37 receives a voltage monitor signal input from the input / output terminal 17. The in-vehicle communication control circuit 38 which is one of the input / output circuits receives the output signal of the transceiver 24 input from the input / output terminal 18.

  In FIG. 2, the oscillator 46 oscillates by a vibrator connected to the vibrator terminal 19 to generate a main clock. The clock control circuit 48 generates a CPU clock and a peripheral clock based on the main clock and supplies them to each circuit block. The CPU clock is supplied to the CPU 40. The peripheral clock is supplied to circuit blocks arranged around the CPU 40.

  As shown in FIG. 2, the microcomputer 11 is provided with a monitoring control circuit 30. The monitoring control circuit 30 is connected to the input / output circuits 32 to 38. The monitoring control circuit 30 operates when the CPU 40 is sleeping. At this time, the monitoring control circuit 30 monitors the input / output circuits 32 to 38. The supervisory control circuit 30 sends a read control signal to the input / output circuits 32 to 38 and reads the status data via the bus DB1 to check whether there is a CPU processing request for the microcomputer 11. Note that sleep is one of the operation modes of the CPU and refers to a state in which the operation of the CPU is stopped by an instruction or an internal / external signal. In general, in this state (operation stop), the CPU clock stops.

  In addition, the microcomputer 11 has circuit blocks such as a flash memory for storing a program, a nonvolatile memory control circuit for controlling the flash memory, and a RAM used for a work area.

  In FIG. 2, when power is supplied to the microcomputer 11, the CPU 40 is activated. When the CPU 40 has finished executing the predetermined command, it sends a sleep transition signal. By sending the sleep transition signal, the operations of the oscillator 46 and the clock control circuit 48 are stopped, and the clock supply to each circuit block of the microcomputer 11 is stopped. The CPU 40 enters a sleep mode when the supply of the CPU clock is stopped. The sleep transition signal is also sent to the monitoring control circuit 30. When receiving the sleep transition signal, the monitoring control circuit 30 starts a monitoring operation. The monitoring control circuit 30 sends out a read control signal and reads status data from the bus DB1 to monitor the input / output circuits 32 to 38.

  When analyzing the status data and detecting a CPU processing request to the microcomputer 11, the monitoring control circuit 30 sends a sleep release signal and stops its operation. By sending the sleep release signal, the operations of the oscillator 46 and the clock control circuit 48 are resumed, and the clock supply to each circuit block of the microcomputer 11 is started. The CPU 40 wakes up by restarting the supply of the CPU clock. The CPU 40 accesses the input / output circuits 32 to 38 that have received the CPU processing request, confirms the content of the CPU processing request, and executes a predetermined program according to the content.

  For example, the analog input interface circuit 23 sends an analog / digital conversion start signal before sending a series of analog signals, and notifies the microcomputer 11 of a CPU processing request. In FIG. 2, an input / output circuit 35 receives an analog / digital conversion start signal. When the CPU 40 is sleeping, the supervisory control circuit 30 sends a read control signal to the input / output circuit 35. The analog / digital conversion start signal is transferred to the monitoring control circuit 30 via the input / output circuit 35, the analog / digital conversion circuit 43, and the bus DB1. When the analog / digital conversion start signal is detected, the supervisory control circuit 30 sends a sleep release signal to wake up the sleeping CPU 40.

  FIG. 3 shows a state transition diagram of the microcomputer. As shown in the figure, the microcomputer 11 has a normal operation mode 50 and a sleep operation mode 51. When the microcomputer 11 is in the normal operation mode 50, the CPU 40 receives a CPU clock and executes an instruction. The monitoring control circuit 30 desirably stops its operation in order to reduce power consumption. On the other hand, when the microcomputer 11 is in the sleep operation mode 51, the CPU 40 stops operating and the monitoring control circuit 30 operates. The monitoring control circuit 30 monitors the input / output circuits 32 to 38 and checks whether there is a CPU processing request. In FIG. 3, switching from the normal operation mode 50 to the sleep operation mode 51 is performed in response to the transmission of the sleep transition signal. In addition, switching from the sleep operation mode 51 to the normal operation mode 50 is performed in response to transmission of a sleep release signal. The sleep transition signal can be sent when the CPU 40 has finished executing a predetermined command. The sleep release signal can be sent when the monitoring control circuit 30 detects a CPU processing request.

  FIG. 4 shows a block configuration diagram of the monitoring control circuit. In FIG. 4, the monitoring control circuit 30 includes a time measurement circuit 61 and a sequencer 62. The supervisory control circuit 30 receives a sleep transition signal for notifying the transition to the sleep operation mode 51 and transmits a sleep cancellation signal for notifying the transition from the sleep operation mode 51 to the normal operation mode 50. In the monitoring control circuit 30, the sleep transition signal is input to the time measurement circuit 61. The time measuring circuit 61 outputs a monitoring activation signal after measuring a certain time. The sequencer 62 inputs the monitoring start signal, starts operation according to predetermined sequence control, and reads status data from the input / output circuits 32 to 38. The sequencer 62 outputs a sleep continuation signal when a CPU processing request is not detected. This sleep continuation signal is input to the time measurement circuit 61. On the other hand, when a CPU processing request is detected, a sleep release signal is output. The sleep release signal is input to the oscillator 46 and the clock control circuit 48.

  FIG. 5 shows a block configuration diagram of the sequencer. Here, in order to simplify the description, a configuration example of a sequencer 62 that monitors only four input / output circuits 32 to 35 is shown. With a simple design change, it is possible to create a sequencer that can monitor a large number of input / output circuits. The timer / counter circuit 42 and the analog / digital conversion circuit 43 are not shown. In FIG. 5, the sequencer 62 includes a sequencer (SQC) clock generation circuit 63, a timing generation circuit 64, a read control circuit 65, a register 66, and a determination circuit 67. In the figure, an SQC clock generation circuit 63 starts its operation upon receiving a monitor activation signal, and generates an SQC clock SQC_CLK used inside the sequencer 62. The timing generation circuit 64 generates timing signals T1 to T4 based on the SQC clock SQC_CLK. The read control circuit 65 outputs a read control signal, a monitoring end signal TE, and a port data check signal RWR based on the timing signals T1 to T4. The read control signal includes a port data read signal PRD and port selection signals CS1 to CS4. The register 66 fetches status data from the bus DB1 and stores it in synchronization with the port data check signal RWR being turned on. The determination circuit 67 reads the status data written in the register 66, and determines whether a change indicating a CPU processing request has occurred between the previous status data and the current status data. When there is no change, a sleep continuation signal is transmitted. When there is a change, in order to cope with the CPU processing request, a sleep release signal is sent to wake up the CPU.

  FIG. 6 is a timing chart for explaining the operation of the sequencer of FIG. In FIG. 6, the SQC clock SQC_CLK is generated by turning on the monitor activation signal. The timing signal T1 is generated at the first rising edge of the SQC clock SQC_CLK. The timing signal T2 is generated at the rising edge of the third SQC clock SQC_CLK. The timing signal T3 is generated at the rising edge of the fifth SQC clock SQC_CLK, and the timing signal T4 is generated at the rising edge of the seventh SQC clock SQC_CLK. The port data read signal PRD is turned on with a delay of one cycle from the timing signal T1. Thereafter, when the port selection signal CS1 is turned on, the status data of the input / output circuit 32 appears on the bus DB1, and when the port selection signal CS2 is turned on, the status data of the input / output circuit 33 appears on the bus DB1 to select the port. When the signal CS3 is turned on, the status data of the input / output circuit 34 appears on the bus DB1, and when the port selection signal CS4 is turned on, the status data of the input / output circuit 35 appears on the bus DB1. The port data check signal RWR is turned on after each port selection signal CS1 to CS4 is turned on, and writing to the register 66 is performed at this timing. Although it is possible to control the write timing to the register 66 without using the port data check signal RWR, it is easier to control using the port data check signal RWR as in this example. it is conceivable that. After the status data of the four input / output circuits 32 to 35 are sequentially written to the register 66, the monitoring end signal TE is turned on, and the generation of the SQC clock SQC_CLK is stopped. FIG. 6 shows an example in which a CPU processing request is not detected as a result of analyzing each status data DB. After the monitoring end signal TE is turned on, the sequencer 62 sends a sleep continuation signal. ing. The sleep release signal is not sent. As a result of analyzing each status data DB, when a CPU processing request is detected, after the monitoring end signal TE is turned on, the sequencer 62 sends a sleep release signal, and the sleep continuation signal is Not sent out.

  FIG. 7 shows a configuration diagram of the time measuring circuit. The time measuring circuit 61 in FIG. 7 measures time using a time constant of C (capacitance) × R (resistance) without counting a clock using a timer, a counter, or the like. More specifically, the time is measured using the charge-up time for the capacitor C1. In FIG. 7, the time measurement circuit 61 includes an RS flip-flop circuit 75 that is inverted by edge detection, a one-shot pulse generation circuit 76, and a transistor 77. The flip-flop circuit 75 sets a sleep operation mode. At the edge when the sleep transition signal or the sleep continuation signal is turned on, the signal is inverted to the set state, and the output signal A is turned on. The one-shot pulse generation circuit 76 outputs one intermittent operation setting pulse PS when the turned-on F / F output signal A is input. The transistor 77 is turned on when receiving the intermittent operation setting pulse PS. At this time, the source and drain of the transistor 77 become conductive, and the charge accumulated in the capacitor C1 is discharged. When the intermittent operation setting pulse PS becomes low, the transistor 77 is turned off, and the capacitor C1 is charged through the transistor TR1. After that, when the potential of the capacitor C1 exceeds a certain value, the output of the inverter INV1 becomes low, the output of the inverter INV2 having the same characteristics as the inverter INV1 becomes high, and the monitor activation signal is turned on. The monitoring activation signal is output to the sequencer 62 and resets the edge detection flip-flop circuit 75. Note that the capacitor C1 can be provided outside the time measuring circuit 61 and, in some cases, outside the microcomputer 11.

  FIG. 8 is an operation explanatory diagram of the time measuring circuit of FIG. In FIG. 8, when the rising edge of the sleep continuation signal is detected, the sleep operation mode setting FF 75 is inverted and set, and the FF output A is turned on. At this timing, the intermittent operation setting pulse PS is output. When the capacitor C1 starts discharging and the C1 potential falls below the INV1 threshold, the monitor activation signal goes low, and the time measurement period starts. In the time measurement period, the charge is recharged in the capacitor C1 once discharged. If the C1 potential exceeds the INV1 threshold value during the recharging process, the monitor activation signal is turned on, the edge detection sleep operation mode setting FF75 is inverted to be in a reset state, and the FF output A is turned off. Here, the time measurement period in the sleep period ends, and the sequencer operation period starts. In the sequencer operation period, the sequencer 62 performs a monitoring operation. If the CPU processing request is not detected as a result of the monitoring operation, the sequencer 62 sends a sleep continuation signal and stops the operation. Due to this sleep continuation signal, the capacitor C1 starts discharging again, the monitor activation signal becomes low, the time measurement period starts, and the intermittent operation of the monitor control circuit 30 is repeated.

  FIG. 9 shows a modification of the time measuring circuit. The time measuring circuit 78 in FIG. 9 can operate at the same timing as the time measuring circuit 61 in FIG. 7 and can be replaced. The time measuring circuit 78 in FIG. 9 measures time by using the charge leakage time due to the leakage current without counting the clock using a timer or a counter. In FIG. 9, the time measurement circuit 78 includes an RS flip-flop circuit 75 that is inverted by edge detection, a one-shot pulse generation circuit 76, and a transistor 79. The transistor 79 is turned on when receiving the intermittent operation setting pulse PS. At this time, the source and drain of the transistor 79 become conductive, and the capacitor C1 is charged. When the intermittent operation setting pulse PS becomes low, the transistor 79 is turned off, and charge leaks from the capacitor C1. Thereafter, when the potential of the capacitor C1 falls below a certain value, the output of the inverter INV1 is inverted and becomes high, and the monitor activation signal is turned on. The monitoring activation signal is output to the sequencer 62 and resets the edge detection flip-flop circuit 75. Note that the capacitor C1 can be provided outside the time measuring circuit 78, and in some cases, outside the microcomputer 11.

  FIG. 10 is an explanatory diagram of the operation of the time measuring circuit of FIG. In FIG. 10, when the rising edge of the sleep transition signal is detected, the sleep operation mode setting FF 75 is set, the FF output A is turned on, and the intermittent operation setting pulse PS is output. The capacitor C1 starts charging, and when the C1 potential exceeds the INV1 threshold, the monitor activation signal becomes low, and the time measurement period starts. In the time measurement period, the charged charge leaks from the capacitor C1. If the C1 potential falls below the INV1 threshold during this leakage process, the output of the inverter INV1 is inverted and becomes high, the monitor activation signal is turned on, and the sleep operation mode setting FF output A for edge detection is reset and turned off. become. Here, the time measurement period in the sleep period ends, and the sequencer operation period starts. After that, charge leakage continues, but when the sleep continuation signal is notified from the sequencer 62 that has finished the monitoring operation, the FF output A is turned on again, the intermittent operation setting pulse PS is output, and the capacitor C1 The charge is recharged.

  The time measuring circuits 61 and 78 described in FIGS. 7 to 10 do not use a clock and timer / counter circuit as means for counting time. Therefore, power consumption when the monitoring control circuit 30 is in the time measurement period can be reduced only to that due to leakage current or charge current. Generally, several hundreds of microamperes are required for the operating current when the clock circuit and the timer / counter circuit are operated. In the time measuring circuits 61 and 78 according to the present embodiment, current consumption (leakage current or charge current) of 1 microampere or less can be suppressed.

  FIG. 11 is a timing chart for explaining the operation of the microcomputer. FIG. 11 shows an example when a CPU processing request is not detected in the monitoring operation by the sequencer 62. In FIG. 11, when the CPU 40 has finished executing a predetermined command, it sends a sleep transition signal. The operation of the CPU 40 is stopped and the operation of the monitoring control circuit 30 is started. In the monitoring control circuit 30, first, the time measuring circuit 61 operates. When the time measuring circuit 61 measures a certain time, a monitoring start signal is sent and the operation of the sequencer 62 starts. When the sequencer 62 sends a read control signal to the input / output circuits 32 to 35 in accordance with the timing signal, the status data of the input / output circuits 32 to 35 sequentially appear on the bus DB1. Thereafter, a monitoring end signal is sent out, and a sleep continuation signal when no CPU processing request is detected is sent out to the time measuring circuit 61. No sleep release signal is sent. The CPU 40 remains stopped and the sleep operation mode 51 is continued.

  FIG. 12 shows another timing chart for explaining the operation of the microcomputer. FIG. 12 shows an example when a CPU processing request is detected in the monitoring operation by the sequencer 62. In FIG. 12, when the CPU 40 finishes executing a predetermined command, it sends a sleep transition signal. The operation of the CPU 40 is stopped and the operation of the monitoring control circuit 30 is started. In the monitoring control circuit 30, first, the time measuring circuit 61 operates. When the time measuring circuit 61 measures a certain time, a monitoring start signal is sent and the operation of the sequencer 62 starts. When the sequencer 62 sends a read control signal to the input / output circuits 32 to 35 in accordance with the timing signal, the status data of the input / output circuits 32 to 35 sequentially appear on the bus DB1. Thereafter, a monitoring end signal is sent out, and a sleep release signal is issued when a CPU processing request is detected. The sleep continuation signal is not sent. The microcomputer 11 transitions from the sleep operation mode 51 to the normal operation mode 50. After the oscillation stabilization period, when the CPU clock supplied by the clock control circuit 48 is stabilized, the CPU 40 resumes the operation and copes with the CPU processing request.

  FIG. 13 shows a modification of the sequencer. The sequencer 70 in FIG. 13 is obtained by changing the register 66 and the determination circuit 67 in the sequencer 62 in FIG. 5. The sequencer 62 in FIG. 5 includes an SQC clock generation circuit 63, a timing generation circuit 64, and a read circuit. It has the same circuit block as the control circuit 65. In FIG. 13, the reference value storage circuit 72 stores a predetermined reference value that is a condition for establishing a logic indicating a CPU processing request. As the reference value, a default value can be set in advance, and can be written from the CPU 40 in the normal operation mode. The comparison circuit 73 compares the value of the register 71 with the reference value of the reference value storage circuit 72. If the comparison circuit 73 indicates a mismatch, the determination circuit 74 determines that the logic indicating the CPU processing request is not established, and sends a sleep continuation signal. If they match, it is determined that a logic indicating a CPU processing request has been established, and a sleep release signal is transmitted. The sequencer 62 in FIG. 5 is an example in which the status data of the input / output circuits 32 to 35 is compared with the previous one and the current one, and the relative determination is performed. The sequencer 70 in FIG. In this example, absolute determination is performed in comparison with the reference value.

  In the monitoring control circuit 30 according to the present embodiment, power consumption is reduced because a CPU that reads, interprets, and executes instructions from the memory is not used as means for confirming the presence or absence of a CPU processing request. For example, the number of gates constituting the main functional block of the CPU needs tens of thousands of gates, but the sequencer 62 according to the present embodiment can be realized with several hundred gates, which is one hundredth or less. The power consumption of the CPU 40 and the sequencer 62 can be calculated by [F (operating frequency) × C (operating load capacity) × V (operating voltage)], where C (operating load capacity) is the number of gates. Since this is proportional, in this embodiment, a large reduction in power consumption of one digit or more can be expected. In terms of current consumption, generally, CPU current consumption is about several tens of milliamperes. On the other hand, since the current consumption of the sequencer 62 according to the present embodiment can be realized at about several hundred microamperes, it can be seen that the current consumption is significantly reduced in the in-vehicle microcomputer according to the present embodiment. .

FIG. 1 is a diagram illustrating a vehicle. FIG. 2 is a configuration diagram of main blocks of the microcomputer. FIG. 3 is a state transition diagram of the microcomputer. FIG. 4 is a block diagram of the monitoring control circuit. FIG. 5 is a block diagram of the sequencer. FIG. 6 is a timing chart for explaining the operation of the sequencer of FIG. FIG. 7 is a configuration diagram of the time measuring circuit. FIG. 8 is an explanatory diagram of the operation of the time measuring circuit of FIG. FIG. 9 is a diagram illustrating a modification of the time measurement circuit. FIG. 10 is an explanatory diagram of the operation of the time measuring circuit of FIG. FIG. 11 is a timing chart for explaining the operation of the microcomputer. FIG. 12 is a diagram showing another timing chart for explaining the operation of the microcomputer. FIG. 13 is a diagram illustrating a modification of the sequencer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Vehicle 11 Microcomputer 12-18 Input / output terminal 19 Vibrator terminals 20-24 External circuit 25 In-vehicle communication bus 30 Monitoring control circuit 32-38 Input / output circuit 40 CPU
42 Timer / Counter Circuit 43 Analog / Digital Conversion Circuit 46 Oscillator 48 Clock Control Circuit 50 Normal Operation Mode 51 Sleep Operation Mode 61, 78 Time Measurement Circuit 62, 70 Sequencer 63 Sequencer (SQC) Clock Generation Circuit 64 Timing Generation Circuit 65 Read Control Circuits 66 and 71 Registers 67 and 74 Determination circuit 72 Reference value storage circuit 73 Comparison circuit 75 Flip-flop circuit 76 One-shot pulse generation circuits 77 and 79 Transistors

Claims (9)

A CPU that receives a CPU clock and executes instructions;
An input / output circuit that receives a CPU processing request from an external circuit;
A monitoring control circuit that performs a monitoring operation of accessing the input / output circuit and detecting the CPU processing request during a sleep period of the CPU;
The CPU
During the sleep period, stop execution of instructions,
The monitoring control circuit includes:
A microcomputer that operates during the sleep period and releases the sleep period when the CPU processing request is detected. The monitoring control circuit includes:
Have a sequencer,
The microcomputer according to claim 1, wherein a monitoring operation for detecting the CPU processing request is performed by the sequencer. The sequencer is
A sequencer clock generation circuit for generating a sequencer clock;
The microcomputer according to claim 2, which operates based on the sequencer clock. The monitoring control circuit includes:
The microcomputer according to claim 2 or 3, wherein intermittent control is performed so that the sequencer operates intermittently. The monitoring control circuit includes:
It further has a time measuring circuit for measuring time,
The microcomputer according to claim 4, wherein the intermittent control is performed using a time measured by the time measuring circuit. The time measuring circuit is
6. The micro of claim 5, wherein the time measurement is performed based on a time using a time constant of C (capacitance) × R (resistance) without counting a clock or based on a charge leakage time using a leakage current. Computer. The monitoring control circuit includes:
The microcomputer according to claim 5 or 6, wherein the intermittent control is performed so that an operation in which the time measurement circuit measures time and an operation in which the sequencer performs a monitoring operation to detect the CPU processing request are alternately performed. . The time measuring circuit is
When a sleep transition signal for notifying transition to the sleep period or a sleep continuation signal for notifying that the sleep period continues is received, the operation is started, and after a predetermined time is measured, a monitor activation signal is transmitted,
The sequencer is
When the monitoring activation signal is received, the operation is started, the input / output circuit is monitored, and when the CPU processing request is not detected, the sleep continuation signal is transmitted, and the CPU processing request is detected The microcomputer according to claim 7, wherein a sleep cancel signal for canceling the sleep period is transmitted. The CPU
The microcomputer according to claim 1, wherein the CPU clock is not supplied during the sleep period.

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