JP2008312372A - Power conversion apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power conversion device capable of keeping output current in balance without having an effect due to integration of errors and use of dedicated voltage detection circuit. <P>SOLUTION: The power conversion device has: a three-phase inverter constituted to form each phase by output from at least one unit inverter 1 for obtaining a single-phase AC output from a DC power supply 11; control means 5 for controlling output voltage by giving gate pulse to each phase of the three-phase inverter; and current detection means 3 for directly or indirectly detecting each output current of the unit inverters 1. The control means 5 includes: a main control unit 6 for producing desired output voltage commands of three phases having desired frequency; current unbalance correction means 8 for correcting at least two phases out of the output voltage commands according to a deviation from the average values of output currents of three phases obtained by the current detection means 3; and PWM control means 7 for generating gate pulses based on a correction voltage command corrected by the current unbalance correction means 8. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a power conversion device, and more particularly to a three-phase output power conversion device that obtains an output voltage of each phase from mutually different DC power sources.

  Conventionally, as a multi-level power converter for the purpose of suppressing harmonics and obtaining a high-voltage output, a multi-level inverter in which the outputs of three single-phase inverters such as two or three levels are connected in a three-phase star, A multi-level inverter having a configuration in which the outputs of a single-phase inverter are connected in series and three-phase star connected is known.

  Usually, in a power conversion device in which single-phase inverters are star-connected, the DC power sources of the single-phase inverters have different configurations. For this reason, there is a problem that the instantaneous power and output voltage of each phase fluctuate due to variations in impedance and voltage of the DC power supply, resulting in imbalance in the current of each phase. Note that the above-mentioned imbalance does not basically occur in a three-phase inverter having a general configuration that generates an AC output from a common DC power supply.

The output voltage Vout (phase voltage peak value) of the power converter configured to obtain an output voltage for one phase by connecting n single-phase inverters in series is a modulation factor α, a DC voltage Vdc, and a single-phase inverter. If the number is n,
Vout = α × Vdc × n / √2 (1)
It becomes. Here, the modulation rate refers to the ratio between the voltage reference amplitude and the carrier amplitude in PWM control. It can be seen from equation (1) that when the DC voltage Vdc varies, or when Vdc varies depending on the load current of the power converter, the output voltage varies. In particular, in a power converter that outputs a high voltage, even if the voltage imbalance is about several percent, the current imbalance may reach several tens percent.

In order to avoid such adverse effects due to imbalance of output voltage and output current, the voltage of each DC power supply is detected, and the voltage reference of each phase is corrected according to the detected value to balance the line voltage. A method of maintaining has been proposed (see, for example, Patent Document 1).
JP 2006-271045 A (page 5-6, FIG. 1)

  However, according to the technique disclosed in Patent Document 1, a dedicated voltage detection circuit is required, which increases the size of the apparatus. In particular, in a high-voltage inverter, the apparatus becomes complicated and large in order to ensure insulation of the voltage detection circuit. In addition, since the current is obtained by integrating the voltage divided by the inductance, if the inductance of each phase varies, the error may be integrated in the voltage detection method and the correction may be insufficient.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a power conversion device that does not have a dedicated voltage detection circuit and can balance output current without the influence of error integration. There is.

  In order to achieve the above object, the power conversion device according to the first aspect of the present invention forms each phase with the output of at least one unit inverter that obtains a single-phase AC output from a DC power source through a smoothing capacitor. A three-phase inverter configured as described above, a control means for applying a gate pulse to each phase of the three-phase inverter to control the output voltage, and a current detection means for directly or indirectly detecting each output current of the unit inverter; The control means includes a deviation between a main control unit for generating a desired output voltage command for three phases having a desired frequency and an average value of the output currents for three phases obtained by the current detection means. And a current unbalance correction unit that corrects at least two phases of the output voltage command, and the gate based on the correction voltage command corrected by the current unbalance correction unit. It is characterized by having a PWM control unit for generating a pulse.

  The power conversion device according to the second aspect of the present invention is a three-phase configuration in which each phase is formed by the output of at least one unit inverter that obtains a single-phase AC output from a DC power source via a smoothing capacitor. An inverter; control means for controlling the output voltage by applying a gate pulse to each phase of the three-phase inverter; and current detection means for directly or indirectly detecting each output current of the unit inverter, The control means is obtained by a main control unit that generates a desired output voltage command of three phases having a desired frequency, a PWM control unit that generates the gate pulse in response to the output voltage command, and the current detection unit. Current imbalance correction means for correcting a modulation factor for at least two phases of the PWM control means in accordance with a deviation from the average value of the three-phase output currents. To have.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to provide the power converter device which does not have a dedicated voltage detection circuit and can balance an output current without the influence of error integration.

  Embodiments of the present invention will be described below with reference to the drawings.

  Hereinafter, the power converter concerning Example 1 of the present invention is explained with reference to Drawing 1 thru / or Drawing 4. FIG. 1 is a circuit configuration diagram of a power conversion apparatus according to Embodiment 1 of the present invention.

  The unit inverters 1U, 1V, and 1W are single-phase output inverters. The outputs of the unit inverters 1U, 1V, and 1W constitute a three-phase inverter by star connection, and supply three-phase AC power to the AC motor 2. The unit inverters 1U, 1V and 1W are controlled so as to output a voltage having a desired frequency component by a gate pulse from the control circuit 5 which will be described in detail later.

  The output currents Iu and Iw of the unit inverters 1U and 1W are detected by current detectors 3U and 3W, respectively, and are given to the control circuit 5. The rotational speed ωm of the AC motor 2 is detected by the speed detector 4 and given to the control circuit 5.

  Hereinafter, the internal configuration of the control circuit 5 will be described.

  According to this embodiment, the main control unit 6, which will be described in detail later, outputs the output voltage commands Vu * of the unit inverters 1U, 1V, and 1W so that the deviation between the given speed command ωr and the rotational speed ωm is minimized. , Vv * and Vw * are adjusted. The current unbalance correction circuit 8 having the output currents Iu and Iw as inputs outputs correction output signals Vuc and Vcw corresponding to the degree of unbalance, respectively, in order to correct the unbalance of the output currents Iu and Iw. The above-described output voltage commands Vu * and Vw * are added and corrected. The corrected voltage commands Vu1 * and Vw1 * after the U-phase and W-phase correction obtained by the addition correction are applied to the PWM controllers 7U and 7W, respectively. The PWM controllers 7U and 7W output gate control pulses Gu and Gw, respectively, according to a predetermined modulation procedure, and turn on / off the switching elements of the unit inverters 1U and 1W. In this embodiment, the output voltage command Vv * is supplied to the PWM controller 7V without being corrected. Then, the PWM controller 7V outputs a gate control pulse Gv according to a predetermined modulation procedure, and performs on / off control of the switching element of the unit inverter 1V.

  The internal circuit configuration of the unit inverter 1 is shown in FIG. The output of the DC power supply 11 is supplied through a smoothing capacitor 12 to a single-phase inverter circuit composed of switching elements 13AP, 13AN, 13BP, and 13BN. A flywheel diode is connected to each switching element 13 in antiparallel. An AC output is obtained from the output terminals A and B of the single-phase inverter circuit. The DC power source 11 may be a battery as shown in FIG. 2, but may be obtained by rectifying from an AC power source using a converter.

  Next, a detailed configuration of the main control unit 6 will be described with reference to FIG.

  The difference between the speed command ωr and the rotational speed ωm is given to the speed controller 61. The speed controller 61 adjusts the output torque reference T * so that the difference becomes zero. This torque reference T * is divided by the excitation command Φ * set by the magnetic flux setter 62 and converted into a torque current reference Iq *. Further, the excitation command Φ * is converted into an excitation current reference Id * by calculation.

  On the other hand, the three-phase two-phase converter 64 obtains a three-phase current from the two-phase current of the AC motor 2 detected by the current detectors 3U and 3W, and orthogonally transforms it to obtain a feedback torque current Iq and a feedback excitation. A current Id is obtained. These feedback currents Iq and Id are compared with the above-described torque current reference Iq * and excitation current reference Id *, respectively, and q-axis which is the output of each of the current controllers 63A and 63B so that the respective deviations become zero. And d-axis voltage references Vq * and Vd *, respectively. The q-axis and d-axis voltage references Vq * and Vd * obtained here are converted into three-phase output voltage references Vu *, Vv * and Vw * by the two-phase / three-phase converter 65.

  Further, the slip frequency ωs is obtained by calculation from the torque reference T * and the excitation command Φ *, and the output frequency ω1 of the power converter is determined by adding the rotational speed ωm thereto. The output phase reference θ1 obtained by integrating the output frequency ω1 is used as the phase reference of the three-phase two-phase converter 64 described above, and the three-phase output voltage references Vu * and Vv from the two-phase three-phase converter 65. * And Vw * are used as phase references.

  The main control unit 6 described above has a so-called vector control function, but may be sensorless vector control for calculating the rotational speed ωm, or directly generates a voltage command from the speed command by so-called V / F control. Such a control system may be used. In the case of sensorless vector control, the speed detector 4 is not required, and in the case of V / F control, a configuration in which no current feedback is provided may be used.

  Next, details of the current imbalance correction circuit 8 will be described. FIG. 4 shows a block diagram of the current imbalance correction circuit 8. The output current Iv of the unit inverter 1V is obtained by adding the output current values Iu and Iw of the unit inverters 1U and 1W, and the absolute value of each output current is obtained by inputting this three-phase output current to the absolute value circuit 82. Get. The absolute value of each output current is given to the processing circuit 83. The output of the processing circuit 83 is given to the average value calculation circuit 84. The processing circuit 83 performs signal processing so that the average value calculation circuit 84 can perform an accurate average value calculation.

  One specific example of the processing circuit 83 is a one-cycle integration circuit. In this case, integration is performed by the processing circuit 83 for one cycle of the fundamental wave of the output current values Iu, Iv, and Iw, and the result is held for a predetermined sampling period and given to the average value calculation circuit 84.

  Another specific example of the processing circuit 83 is a low-pass filter circuit. In this case, the filter constant is appropriately selected so that the output of the processing circuit 83 is substantially only a direct current component in relation to the control time constant.

  The average value calculation circuit 84 calculates the current average value by calculating each phase output of the processing circuit 83 to one third. Then, the comparison circuit 85 compares the U-phase and W-phase outputs of the processing circuit 83 with the current average value, and outputs each deviation. Each deviation of the U phase and the W phase is normalized to a value proportional to the output voltage reference by the voltage weighting circuit 86. The voltage weighting circuit 86 has a function of preventing the full scale of the control from becoming excessive when the current deviation is large at a low voltage, but it is not always necessary to provide this.

  The deviation output of the voltage weighting circuit 86 for each of the U phase and the W phase is input to the correction controller 87. The correction controller 87 is a controller using PI control, for example, and adjusts its output so that the deviation between these inputs becomes zero.

  In this way, the output of the correction controller 87 is added to the original voltage commands Vu * and Vw *, respectively, as the correction amount of the voltage command. The correction voltage commands Vu1 * and Vw1 * obtained in this way are converted into gate pulses Gu and Gw by the PWM control circuits 7U and 7W, respectively, as described above, and supplied to the switching element 13 of each unit inverter 1. The

  As described above, according to the present invention, since the voltage command is corrected so that the output currents of the unit inverters constituting each phase are balanced, there is no dedicated voltage detection circuit, and error integration is performed. It is possible to provide a power conversion device that can balance the output current without any influence.

  In the first embodiment, an example in which a three-phase inverter is configured using three unit inverters 1 is shown. However, a plurality of unit inverters 1 may be connected in series to configure a three-phase inverter. .

  In the present embodiment, the V-phase current is obtained from the U-phase and W-phase currents by calculation, but the V-phase current may also be directly detected.

  Furthermore, in the present embodiment, the correction output of the current imbalance correction circuit 8 is two phases of the U phase and the W phase, but all three phases including the V phase may be corrected.

  FIG. 5 is a circuit configuration diagram of a control circuit used in the power conversion apparatus according to the second embodiment of the present invention.

The same parts of the control circuit 5A of the second embodiment as those of the circuit configuration diagram of the control circuit 5 of the power conversion device according to the first embodiment of the present invention shown in FIG. . The second embodiment is different from the first embodiment in that the correction voltage commands Vu1 * and Vw1 * are supplied to the PWM controllers 7U and 7W via the limit circuits 9U and 9W, respectively.

  By providing the limit circuits 9U and 9W, it is possible to protect from excessive voltage correction. Since the amount of correction due to normal unbalance is at most several percent, it is possible to detect a control abnormality or device failure by detecting the limit of this limit circuit. In this case, an alarm is output as shown.

  The limit circuits 9U and 9W in FIG. 5 are provided on the output side of the correction voltage commands Vu1 * and Vw1 *. However, this limit circuit may be provided on the output side of the current imbalance correction circuit 8. In this case, it is possible to quickly detect an abnormality even when the operating voltage of the apparatus is low.

  FIG. 6 is a circuit configuration diagram of a control circuit used in the power conversion apparatus according to Embodiment 3 of the present invention.

The same parts of the control circuit 5B of the third embodiment as those in the circuit configuration diagram of the control circuit 5 of the power conversion device according to the first embodiment of the present invention shown in FIG. . The third embodiment is different from the first embodiment in that the correction output signal of the current imbalance correction circuit 8 is supplied to the PWM controllers 7U and 7W, and the modulation rates of the PWM controllers 7U and 7W are corrected. is there. Therefore, the correction output signal of the current imbalance correction circuit 8 in the third embodiment acts as a modulation rate correction signal.

  Here, the internal configuration of the PWM controller 7U will be described as an example. As shown in FIG. 6, the carrier signal from the carrier generator 71 and the voltage command Vu * are compared by the comparator 72, and the comparison result is given to the pulse output circuit 73 so that the pulse output circuit 73 generates the gate pulse Gu. It is configured to output.

  Therefore, as shown in the equation (1), if the modulation rate, that is, the amplitude of the carrier generator 71 is corrected and controlled by the correction output signal of the current imbalance correction circuit 8, the current imbalance can be corrected. It is clear that

  Note that it is obvious that the effect described in the second embodiment can be obtained by limiting the output of the correction output signal of the current unbalance correction circuit 8 or the corrected modulation factor in the third embodiment as well. .

  In each of the embodiments described above, the load of the three-phase inverter is the AC motor 2. However, the load is not necessarily an AC motor and may be a normal load. In this case, the main controller 6 may be configured to give a desired output voltage command having a desired frequency.

The circuit block diagram of the power converter device which concerns on Example 1 of this invention. The circuit block diagram of the unit inverter used for this invention. The block block diagram which shows an example of the main control part used for this invention. The block block diagram which shows an example of the current imbalance correction circuit used for this invention. The circuit block diagram of the control circuit used for the power converter device which concerns on Example 2 of this invention. The circuit block diagram of the control circuit used for the power converter device which concerns on Example 3 of this invention.

Explanation of symbols

1, 1U, 1V, 1W Unit inverter 2 AC motor 3U, 3W Current detector 4 Speed detector 5 Control circuit 6 Main controller 7U, 7V, 7W PWM control circuit 8 Current imbalance correction circuit 9U, 9W Limit circuit

11 DC power supply 12 Smoothing capacitor 13, 13AP, 13AN, 13BP, 13BN Switching element

61 Speed controller 62 Magnetic flux setter 63A, 63B Current controller 64 3-phase-2 axis converter 65 2-axis-3 phase converter

71 Carrier generator 72 Comparator 73 Pulse output circuit

81 Adder 82 Absolute value circuit 83 Processing circuit 84 Average value calculation circuit 85 Comparison circuit 86 Voltage weighting circuit 87 Correction controller

Claims (9)

A three-phase inverter configured to form each phase with the output of at least one unit inverter that obtains a single-phase AC output from a DC power source via a smoothing capacitor;
Control means for controlling the output voltage by applying a gate pulse to each phase of the three-phase inverter;
A current detecting means for directly or indirectly detecting each output current of the unit inverter;
The control means includes
A main control unit for generating a desired output voltage command of three phases having a desired frequency;
Current imbalance correction means for correcting at least two phases of the output voltage command according to a deviation from an average value of the three-phase output currents obtained by the current detection means;
And a PWM control unit that generates the gate pulse based on a correction voltage command corrected by the current imbalance correction unit. A three-phase inverter configured to form each phase with the output of at least one unit inverter that obtains a single-phase AC output from a DC power source via a smoothing capacitor;
Control means for controlling the output voltage by applying a gate pulse to each phase of the three-phase inverter;
A current detecting means for directly or indirectly detecting each output current of the unit inverter;
The control means includes
A main control unit for generating a desired output voltage command of three phases having a desired frequency;
PWM control means for generating the gate pulse in response to the output voltage command;
Current imbalance correction means for correcting a modulation factor for at least two phases of the PWM control means according to a deviation from an average value of three-phase output currents obtained by the current detection means, Power converter. The current imbalance correction means includes
The absolute values of the three-phase output currents obtained by the current detection means are each integrated for one cycle, and the deviation between the one-cycle integrated current value and the average value for the three phases of the one-cycle integrated current value is obtained. The power conversion device according to claim 1, wherein the power conversion device is configured as described above. The current imbalance correction means includes
The smoothing current value is obtained by inputting the absolute value of the three-phase output current obtained by the current detecting means to the low-pass filter, and the deviation between the smoothing current value and the average value of the three smoothing current values is calculated. The power conversion device according to claim 1, wherein the power conversion device is obtained.   2. The power converter according to claim 1, further comprising a limit unit configured to limit at least one of the output of the current imbalance correction unit and the output of the corrected correction voltage command so as not to exceed a predetermined range. .   The power converter according to claim 2, further comprising a limit unit configured to limit at least one of the output of the current imbalance correction unit and the corrected modulation factor so as not to exceed a predetermined range.   The power converter according to claim 5 or 6, wherein an alarm is issued when the limit means performs an operation related to a limit. The load of the three-phase inverter is an AC motor,
The power converter according to any one of claims 1 to 7, wherein the main control unit is configured to perform vector control, sensorless vector control, or V / F control. The three-phase inverter is
The power converter according to any one of claims 1 to 8, wherein outputs of the plurality of unit inverters are connected in series.

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