JP2008289211A - System-cooperative inverter - Google Patents

System-cooperative inverter Download PDF

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JP2008289211A
JP2008289211A JP2007128953A JP2007128953A JP2008289211A JP 2008289211 A JP2008289211 A JP 2008289211A JP 2007128953 A JP2007128953 A JP 2007128953A JP 2007128953 A JP2007128953 A JP 2007128953A JP 2008289211 A JP2008289211 A JP 2008289211A
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JP5110960B2 (en
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Zhongwei Guo
中為 郭
Tatsu Shudo
龍 周藤
Mitsuhiro Furuya
充宏 古谷
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Shindengen Electric Manufacturing Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a system-cooperative inverter suppressing variations in switching and DC components of AC output current. <P>SOLUTION: The system-cooperative inverter has a voltage detecting means 8 for detecting a voltage between a midpoint of two capacitors C1, C2 and positive and negative busbars 201, 202 and a voltage between the positive and negative busbars; and an inverter output current control means 12 for controlling the DC components of an output current command of an inverter so that the voltage between the midpoint of the two capacitors and the positive and negative busbars may be 1/2 of the voltage between the positive and negative busbars. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、系統連系インバータ装置に関し、特に、トランスを介さずに、直流電源、発電機等の電力供給源を連系する商用交流電力系統に接続するトランスレス方式の系統連系インバータ装置に関するものである。   The present invention relates to a grid-connected inverter device, and more particularly to a transformer-less grid-connected inverter device that connects a power supply source such as a DC power source and a generator to a commercial AC power system that is linked without using a transformer. Is.

系統連系単相三線式インバータでは、中性点を作るために正母線と負母線間に直列に接続している二つのコンデンサの中点から中性線を取り出して利用する回路方式がある。PWMインバータのスイッチングぱらつき及び出力電流検出オフセット誤差によって、出力電流に直流成分が生じる問題がある。具体的には、二つのコンデンサの中点の初期電圧をVn0、二つのコンデンサの合計容量をC、U相の電流直流成分をIdu、V相の電流直流成分をIdvとして、交流電圧成分を無視して、中性線コンデンサ電圧Vnを求めると、   In a grid-connected single-phase three-wire inverter, there is a circuit system in which a neutral wire is taken out from the middle point of two capacitors connected in series between a positive bus and a negative bus in order to create a neutral point. There is a problem that a direct current component is generated in the output current due to the switching fluctuation of the PWM inverter and the output current detection offset error. Specifically, the initial voltage at the middle point of the two capacitors is Vn0, the total capacity of the two capacitors is C, the U-phase current DC component is Idu, the V-phase current DC component is Idv, and the AC voltage component is ignored. Then, when obtaining the neutral line capacitor voltage Vn,

Figure 2008289211
Figure 2008289211

となる。この結果、前記直流成分によって前記直列に接続している二つのコンデンサに直流成分の電流が流れ、コンデンサの中点電位が正母線と負母線間電圧まで偏ることになり、コンデンサの耐圧を超えてしまう問題もある。 It becomes. As a result, the DC component current flows through the two capacitors connected in series by the DC component, and the middle point potential of the capacitor is biased to the voltage between the positive bus and the negative bus, exceeding the breakdown voltage of the capacitor. There is also a problem.

前記問題の対策として、前記直列に接続する二つのコンデンサにそれぞれ抵抗を前記コンデンサに並列接続し、それぞれのコンデンサの電圧をバランスさせる方法がある(特許文献1参照)。
特開2007−97355公報
As a countermeasure against the above problem, there is a method in which resistors are connected in parallel to the two capacitors connected in series to balance the voltages of the capacitors (see Patent Document 1).
JP 2007-97355 A

しかし、抵抗でバランスさせる方法は抵抗に高圧を印加するため、損失が多い問題と、スイッチングのばらつき及び交流出力電流検出オフセットによる交流出力電流の直流成分の制御ができない問題がある。   However, the method of balancing with the resistance has a problem that there is a lot of loss because a high voltage is applied to the resistance, and there is a problem that the DC component of the AC output current cannot be controlled by the variation in switching and the AC output current detection offset.

本発明は、上記問題に鑑みてなされたものであり、スイッチングのばらつき及び交流出力電流の直流成分を抑制した系統連系インバータ装置を提供する。   The present invention has been made in view of the above problems, and provides a grid-connected inverter device that suppresses switching variations and a DC component of an AC output current.

上記課題を解決するために、本発明に係る系統連系インバータ装置は、直流電源とこれに接続する正母線と負母線を有し、前記正母線と前記負母線間に第一及び第二のスイッチ素子、並びに第三及び第四のスイッチ素子を直列接続し、それぞれの中間点がリアクトルを介して、単相三線式電力系統のU相電圧出力端子並びに前記単相三線式電力系統のV相電圧出力端子に接続すると共に、前記正母線と負母線間に直列に接続された二つのコンデンサの中点から前記単相三線式電力系統の中性線に接続して交流電力に変換する系統連系インバータにおいて、前記二つのコンデンサの中点と前記母線との間の電圧と前記正母線と負母線間の電圧を検出する電圧検出手段と、前記二つのコンデンサの中点と前記母線との間の電圧が前記正母線と負母線間の電圧の1/2になるようにインバータの出力電流指令の直流成分を制御するインバータ出力電流制御手段とを有することを特徴とする。   In order to solve the above problems, a grid-connected inverter device according to the present invention includes a DC power source, a positive bus connected to the DC power source, and a negative bus. The first and second buses are connected between the positive bus and the negative bus. The switch element and the third and fourth switch elements are connected in series, and each intermediate point is connected to the U-phase voltage output terminal of the single-phase three-wire power system and the V-phase of the single-phase three-wire power system via a reactor. Connected to the voltage output terminal and connected to the neutral line of the single-phase three-wire power system from the middle point of the two capacitors connected in series between the positive bus and the negative bus to convert to AC power In the system inverter, voltage detecting means for detecting a voltage between a midpoint of the two capacitors and the bus and a voltage between the positive bus and the negative bus, and between the midpoint of the two capacitors and the bus Is the positive bus and negative bus And having an inverter output current control means for controlling the DC component of the output current command of the inverter so that the half of the voltage between.

また、本発明に係る系統連系インバータ装置は、直流電源とこれに接続する正母線と負母線を有し、前記正母線と単相二線式電力系統の相電圧出力間並びに前記負母線と前記単相二線式電力系統の相電圧出力端子間にリアクトルを介して、それぞれ第一及び第二のスイッチ素子を直列接続すると共に、前記正母線と負母線間に直列に接続された二つのコンデンサの中点から前記単相二線式電力系統の相電圧出力端子に接続して交流電力に変換する系統連系インバータにおいて、前記二つのコンデンサの中点と前記母線との間の電圧と前記正母線と負母線間の電圧を検出する電圧検出手段と、前記二つのコンデンサの中点と前記母線との間の電圧が前記正母線と負母線間の電圧の1/2になるようにインバータの出力電流指令の直流成分を制御するインバータ出力電流制御手段とを有することを特徴とする系統連系インバータ装置。   Further, the grid-connected inverter device according to the present invention has a DC power source, a positive bus connected to the DC power source and a negative bus, and between the positive bus and the phase voltage output of the single-phase two-wire power system, and the negative bus The first and second switch elements are connected in series via a reactor between the phase voltage output terminals of the single-phase two-wire power system, and two connected in series between the positive bus and the negative bus In a grid-connected inverter that is connected to the phase voltage output terminal of the single-phase two-wire power system from the midpoint of the capacitor and converts it to AC power, the voltage between the midpoint of the two capacitors and the bus A voltage detecting means for detecting a voltage between the positive bus and the negative bus; and an inverter so that a voltage between a midpoint of the two capacitors and the bus is ½ of a voltage between the positive bus and the negative bus Controls the DC component of the output current command System interconnection inverter apparatus characterized by having an inverter output current control means that.

前記リアクトルと前記U相電圧出力端子間、及び前記リアクトルと前記負母線と前記単相三線式電力系統V相電圧出力端子間、又は前記リアクトルと前記相電圧出力端子間の交流電流値を検出する交流電流検出手段を備えてあることを特徴とする。   An AC current value is detected between the reactor and the U-phase voltage output terminal, between the reactor and the negative bus and the single-phase three-wire power system V-phase voltage output terminal, or between the reactor and the phase voltage output terminal. An AC current detecting means is provided.

また、前記電圧検出手段で検出した前記二つのコンデンサの中点と前記母線との間の電圧と前記正母線と負母線間の電圧とを比較して、この比較値を直流入力電圧の1/2の値から減算し、この値を前記交流出力の直流成分とみなすように制御することを特徴とする。   Further, the voltage between the midpoint of the two capacitors detected by the voltage detecting means and the bus and the voltage between the positive bus and the negative bus are compared, and this comparison value is 1 / DC input voltage. Subtract from the value of 2 and control to consider this value as a DC component of the AC output.

さらに、前記交流出力のみなし直流成分と予め生成した正弦波電流波形とを加算し、この加算して得た加算値から前記交流電流検出手段で検出された交流電流値を減算して前記直流成分を除去することを特徴とする。   Further, only the AC output non-direct current component and a sine wave current waveform generated in advance are added, and the direct current component detected by the alternating current detection means is subtracted from the added value obtained by the addition. It is characterized by removing.

本発明によれば、二つのコンデンサの中点と正負母線との間の電圧が正母線と負母線間の電圧の1/2になるようにインバータの出力電流指令の直流成分を制御することにより、スイッチングのばらつき及び出力電流検出オフセット誤差によって生じた出力電流の直流成分を抑制することができる。また、二つのコンデンサに電圧バランス回路を接続する必要がないので、回路の簡素化及び低コスト化を図ることができる。   According to the present invention, by controlling the DC component of the output current command of the inverter so that the voltage between the midpoint of the two capacitors and the positive / negative bus is ½ of the voltage between the positive bus and the negative bus. The DC component of the output current caused by the switching variation and the output current detection offset error can be suppressed. Further, since it is not necessary to connect a voltage balance circuit to the two capacitors, the circuit can be simplified and the cost can be reduced.

発明を実施するための最良の形態の回路図を図1に示す。先ず、図1図示の系統連系インバータの主回路について説明する。先ず、本実施例に係る系統連系インバータは、単相三線式の系統連系インバータであり、直流電源1とこれに接続する正母線201と負母線202を有する。この正母線201と負母線202との間に二つのコンデンサC1,C2とを直列に接続してある。また、正母線201と負母線202との間に第一のスイッチ素子Q1と第二のスイッチ素子Q2とを直列に接続して第一のアーム3を構成してあるとともに、これらと並列に、第三のスイッチ素子Q3と第四のスイッチ素子Q4とを直列に接続して第二のアーム4を構成してある。   A circuit diagram of the best mode for carrying out the invention is shown in FIG. First, the main circuit of the grid interconnection inverter shown in FIG. 1 will be described. First, the grid interconnection inverter according to the present embodiment is a single-phase three-wire grid interconnection inverter, and includes a DC power source 1, a positive bus 201 and a negative bus 202 connected thereto. Two capacitors C1 and C2 are connected in series between the positive bus 201 and the negative bus 202. Further, the first switch element Q1 and the second switch element Q2 are connected in series between the positive bus 201 and the negative bus 202 to constitute the first arm 3, and in parallel with these, A second arm 4 is configured by connecting a third switch element Q3 and a fourth switch element Q4 in series.

第一のアーム3の中点から単相三線式電力系統のU相電圧出力端子101を接続し、第二のアーム4の中点から単相三線式電力系統のV相電圧出力端子102を接続してある。二つのコンデンサC1,C2の直列回路2の中点から単相三線式電力系統の中性線103を接続してある。   The U-phase voltage output terminal 101 of the single-phase three-wire power system is connected from the middle point of the first arm 3, and the V-phase voltage output terminal 102 of the single-phase three-wire power system is connected from the middle point of the second arm 4. It is. A neutral line 103 of a single-phase three-wire power system is connected from the midpoint of the series circuit 2 of two capacitors C1 and C2.

第一のアーム3の中点と、単相三線式電力系統のU相電圧出力端子101との間にリアクトルL1を接続してあるとともに、第二のアーム4の中点と、単相三線式電力系統のV相電圧出力端子102との間にリアクトルL2を接続してある。   A reactor L1 is connected between the midpoint of the first arm 3 and the U-phase voltage output terminal 101 of the single-phase three-wire power system, and the midpoint of the second arm 4 and the single-phase three-wire type A reactor L2 is connected between the V-phase voltage output terminal 102 of the power system.

続いて、本実施例に係る系統連系インバータの制御回路について説明する。先ず、二つのコンデンサC1,C2の直列回路2の中点と母線201,202との間の電圧と、正母線201と負母線202との間の電圧を検出する電圧検出手段、本実施例においては、直流出力電圧検出器8を備えてある。この電圧検出器8は、二つのコンデンサC1,C2の直列回路2の中点と母線201,202との間の電圧と、正母線201と負母線202との間の電圧とを比較する。   Then, the control circuit of the grid connection inverter which concerns on a present Example is demonstrated. First, in the present embodiment, voltage detection means for detecting the voltage between the midpoint of the series circuit 2 of the two capacitors C1 and C2 and the buses 201 and 202 and the voltage between the positive bus 201 and the negative bus 202, Is provided with a DC output voltage detector 8. The voltage detector 8 compares the voltage between the midpoint of the series circuit 2 of the two capacitors C1 and C2 and the buses 201 and 202 with the voltage between the positive bus 201 and the negative bus 202.

電圧検出器8より出力された比較値を、直流電源1の直流入力電圧Edの1/2の電圧から減算する減算器11を備え、この減算器11より出力された直流電圧信号はゲイン14に入力される。ゲイン14では、減算器11より出力された直流電圧信号を本実施例に係る系統連系インバータ装置における交流電流のうちの直流成分とみなす。   A subtractor 11 is provided for subtracting the comparison value output from the voltage detector 8 from a voltage that is ½ of the DC input voltage Ed of the DC power supply 1. The DC voltage signal output from the subtractor 11 is supplied to the gain 14. Entered. In the gain 14, the DC voltage signal output from the subtractor 11 is regarded as a DC component of the AC current in the grid-connected inverter device according to the present embodiment.

本実施例に係る系統連系インバータの制御回路は加算器15,16を備えてある。一方の加算器15はゲイン14より出力される交流出力のみなし直流成分と、U相で出力すべき正弦波電力波形21とを加算するように構成してある。他方の加算器16はゲイン14より出力される交流出力のみなし直流成分と、V相で出力すべき正弦波電力波形22とを加算するように構成してある。   The control circuit for the grid-connected inverter according to this embodiment includes adders 15 and 16. One adder 15 is configured to add not only the AC output output from the gain 14 but also the sine wave power waveform 21 to be output in the U phase. The other adder 16 is configured to add not only the AC output output from the gain 14 but also the sine wave power waveform 22 to be output in the V phase.

これに対して、交流電力側には、一方のリアクトルL1とU相電圧出力端子101との間にU相の交流電流を検出するU相電流検出器27を備えてある。また、他方のリアクトルL2とV相電圧出力端子102との間にV相の交流電流を検出するV相電流検出器28を備えてある。   On the other hand, a U-phase current detector 27 for detecting a U-phase AC current is provided between one reactor L1 and the U-phase voltage output terminal 101 on the AC power side. Further, a V-phase current detector 28 for detecting a V-phase AC current is provided between the other reactor L2 and the V-phase voltage output terminal 102.

本実施例に係る系統連系インバータの制御回路は減算器17,18を備えてある。一方の減算器17で、交流出力のみなし直流補正成分が含まれるU相電流指令正弦波からU相電流検出器27で検出されたU相電流を減算する。他方の減算器18で、交流出力のみなし直流補正成分が含まれるV相電流指令正弦波からV相電流検出器28で検出されたV相電流を減算する。   The control circuit for the grid-connected inverter according to the present embodiment includes subtractors 17 and 18. One subtracter 17 subtracts the U-phase current detected by the U-phase current detector 27 from the U-phase current command sine wave including only the AC output and the DC correction component. The other subtracter 18 subtracts the V-phase current detected by the V-phase current detector 28 from the V-phase current command sine wave including only the AC output and the DC correction component.

本実施例に係る系統連系インバータの制御回路は電流制御器12,13を備えてある。減算器17,18で出力された電流誤差信号は各電流制御器12,13で制御演算して誤差制御信号として出力する。具体的には本実施例では、比例制御(P制御)と積分制御(I制御)とを組み合わせたPI制御により、誤差制御信号を出力する。   The control circuit for the grid-connected inverter according to this embodiment includes current controllers 12 and 13. The current error signals output from the subtractors 17 and 18 are calculated by the current controllers 12 and 13 and output as error control signals. Specifically, in this embodiment, the error control signal is output by PI control that combines proportional control (P control) and integral control (I control).

本実施例に係る系統連系インバータの制御回路はそれぞれU相及びV相のPWM変調器9,10を備えてある。U相のPWM変調器9はU相の電流制御器12から出力された誤差制御信号をPWM変調信号に変換して、第一のアーム3の各スイッチ素子Q1,Q2に出力する。一方、V相のPWM変調器10はV相の電流制御器13から出力された誤差制御信号をPWM変調信号に変換して、第二のアーム4の各スイッチ素子Q3,Q4に出力する。   The control circuit for the grid-connected inverter according to the present embodiment includes U-phase and V-phase PWM modulators 9 and 10, respectively. The U-phase PWM modulator 9 converts the error control signal output from the U-phase current controller 12 into a PWM modulation signal, and outputs the PWM control signal to the switch elements Q 1 and Q 2 of the first arm 3. On the other hand, the V-phase PWM modulator 10 converts the error control signal output from the V-phase current controller 13 into a PWM modulation signal and outputs the PWM modulation signal to the switch elements Q3 and Q4 of the second arm 4.

以上のように構成してある系統連系インバータ装置は以下のように作用する。先ず、二つのコンデンサC1,C2の直列回路2の中点と母線201,202との間の電圧と、正母線201と負母線202との間の電圧を直流出力電圧検出器8で検出して、二つのコンデンサC1,C2の直列回路2のと母線201,202との間の電圧と、正母線201と負母線202との間の電圧とを比較する。   The grid-connected inverter device configured as described above operates as follows. First, the DC output voltage detector 8 detects the voltage between the midpoint of the series circuit 2 of the two capacitors C1 and C2 and the buses 201 and 202, and the voltage between the positive bus 201 and the negative bus 202. The voltage between the series circuit 2 of the two capacitors C1 and C2 and the buses 201 and 202 is compared with the voltage between the positive bus 201 and the negative bus 202.

電圧検出器8より出力された比較値を、減算器11で直流電源1の直流入力電圧Edの1/2の電圧から減算する。減算器11より出力された直流電圧信号をゲイン14に入力する。ゲイン14では、減算器11より出力された直流電圧信号を本実施例に係る系統連系インバータ装置における交流電流のうちの直流成分とみなす。ゲイン14より出力される交流出力のみなし直流成分と、U相で出力すべき正弦波電力波形21とを加算器15で加算するとともに、ゲイン14より出力される交流出力のみなし直流成分と、V相で出力すべき正弦波電力波形22とを加算器16で加算する。   The subtractor 11 subtracts the comparison value output from the voltage detector 8 from a voltage that is 1/2 of the DC input voltage Ed of the DC power supply 1. The DC voltage signal output from the subtractor 11 is input to the gain 14. In the gain 14, the DC voltage signal output from the subtractor 11 is regarded as a DC component of the AC current in the grid-connected inverter device according to the present embodiment. The adder 15 adds the alternating current output non-direct current component output from the gain 14 and the sine wave power waveform 21 to be output in the U phase. The adder 16 adds the sine wave power waveform 22 to be output in phase.

これに対して、交流電力側では、一方のリアクトルL1とU相電圧出力端子101との間に備えたU相電流検出器27によりU相の交流電流を検出する。また、他方のリアクトルL2とV相電圧出力端子102との間に備えたV相電流検出器28によりV相の交流入力電流を検出する。   On the other hand, on the AC power side, a U-phase AC current is detected by a U-phase current detector 27 provided between one reactor L1 and the U-phase voltage output terminal 101. A V-phase AC input current is detected by a V-phase current detector 28 provided between the other reactor L2 and the V-phase voltage output terminal 102.

一方の減算器17で、交流出力のみなし直流成分が含まれるU相正弦波電力波形からU相電流検出器27で検出されたU相電流を減算する。他方の減算器18で、交流出力のみなし直流成分が含まれるV相正弦波電力波形からV相電流検出器28で検出されたV相電流を減算する。この減算処理により、交流出力の直流成分を除去することができる。減算器17,18で交流出力の直流成分を除去した信号は各電流制御器12,13でPI制御演算して誤差制御信号として出力される。   One subtractor 17 subtracts the U-phase current detected by the U-phase current detector 27 from the U-phase sine wave power waveform including only the AC output and the DC component. The other subtracter 18 subtracts the V-phase current detected by the V-phase current detector 28 from the V-phase sine wave power waveform including only the AC output and the DC component. With this subtraction process, the DC component of the AC output can be removed. The signals from which the DC components of the AC output are removed by the subtractors 17 and 18 are subjected to PI control calculation by the current controllers 12 and 13 and are output as error control signals.

U相の電流制御器12から出力された誤差制御信号をU相のPWM変調器9でPWM変調信号に変換して、第一のアーム3の各スイッチ素子Q1,Q2に出力する。一方、V相の電流制御器13から出力された誤差制御信号をV相のPWM変調器10でPWM変調信号に変換して、第二のアーム4の各スイッチ素子Q3,Q4に出力する。   The error control signal output from the U-phase current controller 12 is converted into a PWM modulation signal by the U-phase PWM modulator 9 and output to the switch elements Q1 and Q2 of the first arm 3. On the other hand, the error control signal output from the V-phase current controller 13 is converted into a PWM modulation signal by the V-phase PWM modulator 10 and output to the switching elements Q3 and Q4 of the second arm 4.

以上より、二つのコンデンサの中点と正負母線との間の電圧が正母線と負母線間の電圧の1/2になるようにインバータの出力電流指令の直流成分を制御することにより、スイッチングのばらつき及び出力電流検出オフセット誤差によって生じた出力電流の直流成分を抑制することができる。また、二つのコンデンサに電圧バランス回路を接続する必要がないので、回路の簡素化及び低コスト化を図ることができる。   From the above, by controlling the DC component of the output current command of the inverter so that the voltage between the midpoint of the two capacitors and the positive / negative bus is half of the voltage between the positive bus and the negative bus, The direct current component of the output current caused by the variation and the output current detection offset error can be suppressed. Further, since it is not necessary to connect a voltage balance circuit to the two capacitors, the circuit can be simplified and the cost can be reduced.

続いて、第二の実施例について説明する。第二の実施例に係る系統連系インバータは、単相二線式の系統連系インバータであり、直流電源1とこれに接続する正母線201と負母線202を有する。この正母線201と負母線202との間に二つのコンデンサC1,C2とを直列に接続してある。また、正母線201と負母線202との間に第一のスイッチ素子Q1と第二のスイッチ素子Q2とを直列に接続してアーム3を構成してある。   Subsequently, a second embodiment will be described. The grid interconnection inverter according to the second embodiment is a single-phase two-wire grid interconnection inverter, and includes a DC power source 1, a positive bus 201 and a negative bus 202 connected thereto. Two capacitors C1 and C2 are connected in series between the positive bus 201 and the negative bus 202. Further, the arm 3 is configured by connecting the first switch element Q1 and the second switch element Q2 in series between the positive bus 201 and the negative bus 202.

アーム3の中点から単相二線式電力系統の交流電圧出力端子101を接続ししてある。二つのコンデンサC1,C2の直列回路2の中点から単相二線式電力系統の中性線103を接続してある。アーム3の中点と交流電圧出力端子101との間にリアクトルL1を接続してあるとともに、二つのコンデンサC1,C2の直列回路2の中点と交流電源7との間にリアクトルL2を接続してある。   The AC voltage output terminal 101 of the single-phase two-wire power system is connected from the middle point of the arm 3. A neutral line 103 of a single-phase two-wire power system is connected from the middle point of the series circuit 2 of two capacitors C1 and C2. A reactor L1 is connected between the midpoint of the arm 3 and the AC voltage output terminal 101, and a reactor L2 is connected between the midpoint of the series circuit 2 of the two capacitors C1 and C2 and the AC power supply 7. It is.

続いて、本実施例に係る系統連系インバータの制御回路について説明する。先ず、二つのコンデンサC1,C2の直列回路2の中点と母線201,202との間の電圧と、正母線201と負母線202との間の電圧を検出する電圧検出手段、本実施例においては、直流出力電圧検出器8を備えてある。この電圧検出器8は、二つのコンデンサC1,C2の直列回路2の中点と母線201,202との間の電圧と、正母線201と負母線202との間の電圧とを比較する。   Then, the control circuit of the grid connection inverter which concerns on a present Example is demonstrated. First, in the present embodiment, voltage detection means for detecting the voltage between the midpoint of the series circuit 2 of the two capacitors C1 and C2 and the buses 201 and 202 and the voltage between the positive bus 201 and the negative bus 202, Is provided with a DC output voltage detector 8. The voltage detector 8 compares the voltage between the midpoint of the series circuit 2 of the two capacitors C1 and C2 and the buses 201 and 202 with the voltage between the positive bus 201 and the negative bus 202.

電圧検出器8より出力された比較値を、直流電源1の直流入力電圧Edの1/2の電圧から減算する減算器11を備え、この減算器11より出力された直流電圧信号はゲイン14に入力される。ゲイン14では、減算器11より出力された直流電圧信号を本実施例に係る系統連系インバータ装置における交流電流のうちの直流成分とみなす。   A subtractor 11 is provided for subtracting the comparison value output from the voltage detector 8 from a voltage that is ½ of the DC input voltage Ed of the DC power supply 1. The DC voltage signal output from the subtractor 11 is supplied to the gain 14. Entered. In the gain 14, the DC voltage signal output from the subtractor 11 is regarded as a DC component of the AC current in the grid-connected inverter device according to the present embodiment.

本実施例に係る制御回路は加算器15を備えてある。この加算器15はゲイン14より出力される交流出力のみなし直流成分と、交流部分で出力すべき正弦波電力波形21とを加算するように構成してある。これに対して、交流電力側には、一方のリアクトルL1と交流電圧出力端子101との間に交流電流を検出する電流検出器27を備えてある。   The control circuit according to this embodiment includes an adder 15. The adder 15 is configured to add not only the AC output output from the gain 14 but also the sine wave power waveform 21 to be output in the AC portion. On the other hand, on the AC power side, a current detector 27 that detects an AC current is provided between one reactor L1 and the AC voltage output terminal 101.

本実施例に係る制御回路は減算器17を備えてある。減算器17で、交流出力のみなし直流成分が含まれる正弦波電力波形から交流電流検出器27で検出された交流電流を減算する。この減算処理により、交流出力の直流成分を除去することができる。   The control circuit according to this embodiment includes a subtracter 17. The subtracter 17 subtracts the AC current detected by the AC current detector 27 from a sine wave power waveform including only an AC output and a DC component. With this subtraction process, the DC component of the AC output can be removed.

本実施例に係る制御回路は電流制御器12を備えてある。減算器17で交流出力の直流成分を除去した信号は電流制御器12でPI制御演算して誤差制御信号として出力する。本実施例に係る制御回路はPWM変調器9を備えてある。PWM変調器9は電流制御器12から出力された誤差制御信号をPWM変調信号に変換して、アーム3の各スイッチ素子Q1,Q2に出力する。   The control circuit according to this embodiment includes a current controller 12. The signal from which the DC component of the AC output is removed by the subtractor 17 is subjected to PI control calculation by the current controller 12 and output as an error control signal. The control circuit according to this embodiment includes a PWM modulator 9. The PWM modulator 9 converts the error control signal output from the current controller 12 into a PWM modulation signal and outputs the PWM modulation signal to the switch elements Q1 and Q2 of the arm 3.

以上のように構成してある系統連系インバータ装置は以下のように作用する。先ず、二つのコンデンサC1,C2の直列回路2の中点と母線201,202との間の電圧と、正母線201と負母線202との間の電圧を直流出力電圧検出器8で検出して、二つのコンデンサC1,C2の直列回路2の中点の電圧と、正母線201と負母線202との間の電圧とを比較する。   The grid-connected inverter device configured as described above operates as follows. First, the DC output voltage detector 8 detects the voltage between the midpoint of the series circuit 2 of the two capacitors C1 and C2 and the buses 201 and 202, and the voltage between the positive bus 201 and the negative bus 202. The voltage at the midpoint of the series circuit 2 of the two capacitors C1 and C2 is compared with the voltage between the positive bus 201 and the negative bus 202.

電圧検出器8より出力された比較値を、減算器11で直流電源1の直流入力電圧Edの1/2の電圧から減算する。減算器11より出力された直流電圧信号をゲイン14に入力する。ゲイン14では、減算器11より出力された直流電圧信号を本実施例に係る系統連系インバータ装置における交流電流のうちの直流成分とみなす。ゲイン14より出力される交流出力のみなし直流成分と、交流部分で出力すべき正弦波電力波形21とを加算器15で加算する。これに対して、交流電力側では、一方のリアクトルL1と交流電圧出力端子101との間に備えた交流電流検出器27により交流電流を検出する。   The subtractor 11 subtracts the comparison value output from the voltage detector 8 from a voltage that is 1/2 of the DC input voltage Ed of the DC power supply 1. The DC voltage signal output from the subtractor 11 is input to the gain 14. In the gain 14, the DC voltage signal output from the subtractor 11 is regarded as a DC component of the AC current in the grid-connected inverter device according to the present embodiment. The adder 15 adds only the AC component output from the gain 14 and the sine wave power waveform 21 to be output in the AC part. On the other hand, on the AC power side, an AC current is detected by an AC current detector 27 provided between one reactor L1 and the AC voltage output terminal 101.

減算器17で、交流出力のみなし直流成分が含まれる正弦波電力波形から電流検出器27で検出された交流電流を減算する。この減算処理により、交流出力の直流成分を除去することができる。減算器17で交流出力の直流成分を除去した信号は各電流制御器12でPI制御演算して誤差制御信号として出力される。電流制御器12から出力された誤差制御信号をPWM変調器9でPWM変調信号に変換して、第一のアーム3の各スイッチ素子Q1,Q2に出力する。   The subtracter 17 subtracts the AC current detected by the current detector 27 from the sine wave power waveform including only the AC output and the DC component. With this subtraction process, the DC component of the AC output can be removed. The signal from which the DC component of the AC output is removed by the subtractor 17 is subjected to PI control calculation by each current controller 12 and output as an error control signal. The error control signal output from the current controller 12 is converted into a PWM modulation signal by the PWM modulator 9 and output to the switch elements Q1 and Q2 of the first arm 3.

以上より、二つのコンデンサの中点と正負母線との間の電圧が正母線と負母線間の電圧の1/2になるようにインバータの出力電流指令の直流成分を制御することにより、スイッチングのばらつき及び出力電流検出オフセット誤差によって生じた出力電流の直流成分を抑制することができる。また、二つのコンデンサに電圧バランス回路を接続する必要がないので、回路の簡素化及び低コスト化を図ることができる。   From the above, by controlling the DC component of the output current command of the inverter so that the voltage between the midpoint of the two capacitors and the positive / negative bus is half of the voltage between the positive bus and the negative bus, The direct current component of the output current caused by the variation and the output current detection offset error can be suppressed. Further, since it is not necessary to connect a voltage balance circuit to the two capacitors, the circuit can be simplified and the cost can be reduced.

本発明によれば、二つのコンデンサの中点と正負母線との間の電圧が正母線と負母線間の電圧の1/2になるようにインバータの出力電流指令の直流成分を制御することにより、スイッチングのばらつき及び出力電流検出オフセット誤差によって生じた出力電流の直流成分を抑制することができる。また、二つのコンデンサに電圧バランス回路を接続する必要がないので、回路の簡素化及び低コスト化を図ることができ、産業上利用可能である。   According to the present invention, by controlling the DC component of the output current command of the inverter so that the voltage between the midpoint of the two capacitors and the positive / negative bus is ½ of the voltage between the positive bus and the negative bus. The DC component of the output current caused by the switching variation and the output current detection offset error can be suppressed. Further, since it is not necessary to connect a voltage balance circuit to the two capacitors, the circuit can be simplified and the cost can be reduced, and the invention can be used industrially.

本発明に係る系統連系インバータ装置における発明を実施するための最良の形態の回路図である。1 is a circuit diagram of the best mode for carrying out the invention in a grid-connected inverter device according to the present invention. 図1とは別の系統連系インバータ装置における実施例の回路図である。It is a circuit diagram of the Example in the grid connection inverter apparatus different from FIG.

符号の説明Explanation of symbols

1 直流電源
C1,C2 コンデンサ
2 コンデンサC1,C2との直列回路
Q1,Q2,Q3,Q4 スイッチ素子
3,4 アーム
7 交流電源
8 直流出力電圧検出器
9,10 PWM変調器
11 減算器
12,13 電流制御器
14 ゲイン
15,16 加算器
17,18 減算器
21,22 正弦波電力波形
27,28 交流電流検出器
101、102 交流電圧出力端子
103 中性線
201 正母線
202 負母線
L1 リアクトル
DESCRIPTION OF SYMBOLS 1 DC power supply C1, C2 Capacitor 2 Series circuit Q1, Q2, Q3, Q4 with capacitor C1, C2 Switch element 3, 4 Arm 7 AC power supply 8 DC output voltage detector 9, 10 PWM modulator 11 Subtractor 12, 13 Current controller 14 Gain 15, 16 Adder 17, 18 Subtractor 21, 22 Sine wave power waveform 27, 28 AC current detector 101, 102 AC voltage output terminal 103 Neutral wire 201 Positive bus 202 Negative bus L1 Reactor

Claims (5)

直流電源とこれに接続する正母線と負母線を有し、前記正母線と前記負母線間に第一及び第二のスイッチ素子、並びに第三及び第四のスイッチ素子を直列接続し、それぞれの中間点がリアクトルを介して、単相三線式電力系統のU相電圧出力端子並びに前記単相三線式電力系統のV相電圧出力端子に接続すると共に、前記正母線と負母線間に直列に接続された二つのコンデンサの中点から前記単相三線式電力系統の中性線に接続して交流電力に変換する系統連系インバータにおいて、
前記二つのコンデンサの中点と前記母線との間の電圧と前記正母線と負母線間の電圧を検出する電圧検出手段と、前記二つのコンデンサの中点と前記母線との間の電圧が前記正母線と負母線間の電圧の1/2になるようにインバータの出力電流指令の直流成分を制御するインバータ出力電流制御手段とを有することを特徴とする系統連系インバータ装置。
A DC power source and a positive bus and a negative bus connected thereto, and the first and second switch elements, and the third and fourth switch elements are connected in series between the positive bus and the negative bus, The intermediate point is connected to the U-phase voltage output terminal of the single-phase three-wire power system and the V-phase voltage output terminal of the single-phase three-wire power system via a reactor, and connected in series between the positive bus and the negative bus In the grid-connected inverter that is connected to the neutral line of the single-phase three-wire power system from the midpoint of the two capacitors that are converted into AC power,
Voltage detecting means for detecting a voltage between a midpoint of the two capacitors and the bus and a voltage between the positive bus and the negative bus; and a voltage between the midpoint of the two capacitors and the bus. An inverter output current control means for controlling a direct current component of an output current command of the inverter so that the voltage between the positive bus and the negative bus is ½.
直流電源とこれに接続する正母線と負母線を有し、前記正母線と単相二線式電力系統の相電圧出力間並びに前記負母線と前記単相二線式電力系統の相電圧出力端子間にリアクトルを介して、それぞれ第一及び第二のスイッチ素子を直列接続すると共に、前記正母線と負母線間に直列に接続された二つのコンデンサの中点から前記単相二線式電力系統の相電圧出力端子に接続して交流電力に変換する系統連系インバータにおいて、
前記二つのコンデンサの中点と前記母線との間の電圧と前記正母線と負母線間の電圧を検出する電圧検出手段と、前記二つのコンデンサの中点と前記母線との間の電圧が前記正母線と負母線間の電圧の1/2になるようにインバータの出力電流指令の直流成分を制御するインバータ出力電流制御手段とを有することを特徴とする系統連系インバータ装置。
DC power source and positive and negative buses connected to it, phase voltage output terminals between the positive bus and the single-phase two-wire power system, and between the negative bus and the single-phase two-wire power system The first and second switch elements are respectively connected in series via a reactor in between, and the single-phase two-wire power system from the midpoint of two capacitors connected in series between the positive bus and the negative bus In the grid-connected inverter that is connected to the phase voltage output terminal and converts to AC power,
Voltage detecting means for detecting a voltage between a midpoint of the two capacitors and the bus and a voltage between the positive bus and the negative bus; and a voltage between the midpoint of the two capacitors and the bus. An inverter output current control means for controlling a direct current component of an output current command of the inverter so that the voltage between the positive bus and the negative bus is ½.
前記リアクトルと前記U相電圧出力端子間、及び前記リアクトルと前記負母線と前記単相三線式電力系統V相電圧出力端子間、又は前記リアクトルと前記相電圧出力端子間の交流電流値を検出する交流電流検出手段を備えてあることを特徴とする請求項1又は2記載の系統連系インバータ装置。 An AC current value is detected between the reactor and the U-phase voltage output terminal, between the reactor and the negative bus and the single-phase three-wire power system V-phase voltage output terminal, or between the reactor and the phase voltage output terminal. 3. The grid-connected inverter device according to claim 1, further comprising AC current detecting means. 前記電圧検出手段で検出した前記二つのコンデンサの中点と前記母線との間の電圧と前記正母線と負母線間の電圧とを比較して、この比較値を直流入力電圧の1/2の値から減算し、この値を前記交流出力の直流成分とみなすように制御することを特徴とする請求項1乃至3のいずれかに記載の系統連系インバータ装置。 The voltage between the midpoint of the two capacitors detected by the voltage detection means and the bus is compared with the voltage between the positive bus and the negative bus, and this comparison value is ½ of the DC input voltage. 4. The grid-connected inverter device according to claim 1, wherein control is performed so that the value is subtracted from the value and the value is regarded as a direct current component of the alternating current output. 前記交流出力のみなし直流成分と予め生成した正弦波電流波形とを加算し、この加算して得た加算値から前記交流電流検出手段で検出された交流電流値を減算して前記直流成分を除去することを特徴とする請求項4記載の系統連系インバータ装置。 Adds only the AC output DC component and the sine wave current waveform generated in advance, and subtracts the AC current value detected by the AC current detection means from the added value to remove the DC component The system interconnection inverter apparatus according to claim 4, wherein
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WO2010055652A1 (en) 2008-11-11 2010-05-20 東ソー・ファインケム株式会社 Solid polymethylaluminoxane composition and process for producing same
WO2012108267A1 (en) * 2011-02-10 2012-08-16 シャープ株式会社 Power conversion apparatus and method of controlling thereof
CN102780414A (en) * 2012-01-13 2012-11-14 广东志成冠军集团有限公司 Device and method for inhibiting inrush starting current for large-power grid-connected inverter
CN104348375A (en) * 2013-07-26 2015-02-11 株式会社日立信息通信工程 Power supply device and method of operating device
JP2018011420A (en) * 2016-07-13 2018-01-18 オムロン株式会社 Electric power converter
JP2018011413A (en) * 2016-07-13 2018-01-18 オムロン株式会社 Electric power converter
CN110943642A (en) * 2019-12-12 2020-03-31 厦门市爱维达电子有限公司 Power frequency UPS full-bridge inversion primary direct current bias self-adaptive control system
CN115603601A (en) * 2022-12-13 2023-01-13 麦田能源有限公司(Cn) Method and device for controlling inverter, inverter system and electronic equipment
CN115622435A (en) * 2022-12-13 2023-01-17 麦田能源有限公司 Control method and device of inverter based on scene observation and inverter system

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0775345A (en) * 1993-09-01 1995-03-17 Hitachi Ltd Power converter device
JP2001197757A (en) * 2000-01-11 2001-07-19 Mitsubishi Electric Corp Power converter
JP2002112448A (en) * 2000-09-29 2002-04-12 Canon Inc System linking apparatus and method for linking
JP2004104973A (en) * 2002-09-12 2004-04-02 Toshiba Corp Inverter control device
JP2004180467A (en) * 2002-11-29 2004-06-24 Hitachi Home & Life Solutions Inc Systematically interconnecting power supply system
JP2005137070A (en) * 2003-10-29 2005-05-26 Hitachi Home & Life Solutions Inc System linkage inverter and power source system

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0775345A (en) * 1993-09-01 1995-03-17 Hitachi Ltd Power converter device
JP2001197757A (en) * 2000-01-11 2001-07-19 Mitsubishi Electric Corp Power converter
JP2002112448A (en) * 2000-09-29 2002-04-12 Canon Inc System linking apparatus and method for linking
JP2004104973A (en) * 2002-09-12 2004-04-02 Toshiba Corp Inverter control device
JP2004180467A (en) * 2002-11-29 2004-06-24 Hitachi Home & Life Solutions Inc Systematically interconnecting power supply system
JP2005137070A (en) * 2003-10-29 2005-05-26 Hitachi Home & Life Solutions Inc System linkage inverter and power source system

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010055652A1 (en) 2008-11-11 2010-05-20 東ソー・ファインケム株式会社 Solid polymethylaluminoxane composition and process for producing same
WO2012108267A1 (en) * 2011-02-10 2012-08-16 シャープ株式会社 Power conversion apparatus and method of controlling thereof
JP2012170189A (en) * 2011-02-10 2012-09-06 Sharp Corp Power conversion device and control method thereof
CN102780414A (en) * 2012-01-13 2012-11-14 广东志成冠军集团有限公司 Device and method for inhibiting inrush starting current for large-power grid-connected inverter
CN104348375A (en) * 2013-07-26 2015-02-11 株式会社日立信息通信工程 Power supply device and method of operating device
US9306472B2 (en) 2013-07-26 2016-04-05 Hitachi Information & Telecommunication Engineering, Ltd. Power supply device operating switching elements of first and second switching legs to charge first and second capacitors to a voltage higher than a voltage crest value of an AC power supply and method of operating the power supply device
CN104348375B (en) * 2013-07-26 2017-04-12 株式会社日立信息通信工程 Power supply device and method of operating device
JP2018011420A (en) * 2016-07-13 2018-01-18 オムロン株式会社 Electric power converter
JP2018011413A (en) * 2016-07-13 2018-01-18 オムロン株式会社 Electric power converter
CN110943642A (en) * 2019-12-12 2020-03-31 厦门市爱维达电子有限公司 Power frequency UPS full-bridge inversion primary direct current bias self-adaptive control system
CN115603601A (en) * 2022-12-13 2023-01-13 麦田能源有限公司(Cn) Method and device for controlling inverter, inverter system and electronic equipment
CN115622435A (en) * 2022-12-13 2023-01-17 麦田能源有限公司 Control method and device of inverter based on scene observation and inverter system
CN115603601B (en) * 2022-12-13 2023-04-07 麦田能源有限公司 Method and device for controlling inverter, inverter system and electronic equipment
CN115622435B (en) * 2022-12-13 2023-04-28 麦田能源有限公司 Inverter control method and device based on scene observation and inverter system

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