JP2008072856A - Dc/dc power conversion system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To connect an LC serial object where a capacitor and an inductor are connected in series between adjacent circuits, to improve conversion efficiency by utilizing a resonance phenomenon, and to miniaturize a device structure in a DC/DC power conversion device, having three or more circuits of an inverter circuit and a rectifier circuit and using charging/discharging of the capacitor. <P>SOLUTION: Three or more circuits of the drive inverter circuits and the rectifier circuits are connected in series, and the LC serial objects LC12 to LC34 of the capacitors and the inductors are arranged in between the adjacent circuits. The LC serial objects LC12 to LC34 are constituted so that more capacitor elements and the inductor elements of the same specification are arranged in parallel, the closer they are to low voltage-side voltage terminals VL and Vcom for input/output. Thus, capacitor capacitance is set the larger, the smaller the inductance the closer the elements to VL and Vcom, moreover, the resonance periods are each set equal, the resonance phenomenon is used effectively, and the sizes of the capacitors and inductance of the LC serial objects LC12 to LC34 are optimized. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a DC / DC power converter that converts a DC voltage into a DC voltage that is stepped up or down.

  A DC / DC converter as a conventional DC / DC power converter includes an inverter circuit including at least two semiconductor switches including a semiconductor switch connected to a positive potential and a semiconductor switch connected to a negative potential. It is composed of a multiple voltage rectifier circuit with a plurality of rectifiers connected in series and a plurality of capacitors connected in series, creates an AC voltage with an inverter circuit, and further generates a high voltage DC voltage with a multiple voltage rectifier circuit Is supplied to the load (see, for example, Patent Document 1).

  A switched capacitor converter as a DC / DC power converter according to another conventional example is composed of an inverter circuit and a double voltage rectifier circuit. An inductor is connected in series with the capacitor, and an LC resonance phenomenon is used to convert the capacitor. Thus, power conversion is realized with little reduction in efficiency even when large power is transferred (see Non-Patent Document 1, for example).

JP-A-9-191638 Futoshi Itoba et al .: "Control characteristics of resonant switched capacitor converter", IEICE Technical Report, IEICE Technical Report, EE2005-62, pp7-12, 2006

  These conventional DC / DC power converters are provided with an inverter circuit and a rectifier circuit, and perform DC / DC power conversion using charging / discharging of a capacitor. In addition, an inductor is connected in series with the capacitor. If the LC resonance phenomenon is used, high power can be transferred with high efficiency. In this case, if a multiple voltage rectifier circuit in which a plurality of rectifier circuits are connected to each other, a plurality of LC series bodies of capacitors and inductors are also required. However, if a plurality of LC series bodies having the same specifications are used, Therefore, there is a problem that the allowable current value is increased in accordance with the maximum current value, resulting in an increase in the size of the apparatus configuration.

  The present invention has been made in order to solve the above-described problems, and is provided with three or more circuits including an inverter circuit and a rectifier circuit, and DC / DC power conversion using charging / discharging of a capacitor. An object of the present invention is to provide an LC series body of a capacitor and an inductor between circuits to improve conversion efficiency by utilizing a resonance phenomenon and to reduce the size of the device.

  According to a first DC / DC power converter of the present invention, three or more circuits including a plurality of semiconductor switching elements and smoothing capacitors whose ON / OFF operations are controlled by a control electrode are connected in series between a capacitor and an inductor between adjacent circuits. A low voltage side voltage terminal and a high voltage side voltage terminal, which are input / output voltage terminals, are respectively connected to the terminals of the predetermined smoothing capacitor. In the plurality of series bodies, the closer to the low voltage side voltage terminal, the larger the capacitor capacity and the smaller the inductance, and the resonance periods determined by the capacitor capacity and the inductance are set to be equal. Then, among the plurality of circuits, a predetermined circuit is used as a drive inverter circuit, and another circuit is used as a rectifier circuit, and DC / DC conversion is performed by charging and discharging the capacitors in the series bodies.

  A second DC / DC power converter according to the present invention comprises a circuit in which two semiconductor switching elements whose on / off operations are controlled by a control electrode are connected in series between the positive and negative terminals of a smoothing capacitor, and two diode elements in series. Connect three or more circuits, which are connected between the positive and negative terminals of a smoothing capacitor, in a row with a series of capacitors and inductors between adjacent circuits, and serve as input / output voltage terminals on the low voltage side A voltage terminal and a high voltage side voltage terminal are respectively connected to terminals of the predetermined smoothing capacitor. In the plurality of series bodies, the closer to the low voltage side voltage terminal, the larger the capacitor capacity and the smaller the inductance, and the resonance periods determined by the capacitor capacity and the inductance are set to be equal. Then, DC / DC conversion is performed by charging / discharging the capacitors in the series bodies.

  In the first and second DC / DC power converters according to the present invention, a plurality of series bodies in which a capacitor and an inductor are connected in series are arranged such that the closer to the low voltage side voltage terminal, the larger the capacitor capacity and the smaller the inductance. Resonance periods determined by inductance were set equal. For this reason, it is possible to improve the conversion efficiency by effectively using the resonance phenomenon, and the series body closer to the low voltage side voltage terminal can increase the allowable current value to optimize the size of each series body, thereby reducing the device configuration. Can be

Embodiment 1 FIG.
Hereinafter, a DC / DC power converter according to Embodiment 1 of the present invention will be described with reference to the drawings. 1 and 2 show a circuit configuration of a DC / DC power converter according to Embodiment 1 of the present invention. FIG. 1 shows a main circuit and FIG. 2 shows a control circuit.
In the first embodiment, the voltage V1 between the low voltage side voltage terminal VL and Vcom and the voltage raising and lowering having a function of performing bidirectional energy transfer between the voltage V2 between the high voltage side voltage terminal VH and Vcom. A pressure type DC / DC power converter will be described. The voltage V2 is about four times the voltage V1, where V1 is 50V and V2 is about 200V.

  As shown in FIG. 1, the main circuit unit of the DC / DC power converter smoothes input / output voltages V1 and V2, and also functions as a voltage source for energy transfer, smoothing capacitors Cs1, Cs2, Cs3, and Cs4. And two MOSFETs (Mos1L, Mos1H) (Mos2L, Mos2H) (Mos3L, Mos3H) (Mos4L, Mos4H) as low-voltage side switches and high-voltage side switches, connected in series to each smoothing capacitor Cs1 , Cs2, Cs3, and Cs4 are connected in series between circuits A1, A2, A3, and A4. Then, with the connection point of the two MOSFETs in each circuit A1, A2, A3, A4 as an intermediate terminal, a capacitor Cr12 (Cr12A, Cr12B, Cr12C) is connected between the intermediate terminals of the adjacent circuits A1, A2, A3, A4. ), Cr23 (Cr23A, Cr23B), Cr34 (Cr34A) and inductor Lr12 (Lr12A, Lr12B, Lr12C), Lr23 (Lr23A, Lr23B), Lr34 (Lr34A) are connected in series and LC series functions as an energy transfer element Connect the body LC12, LC23, LC34. Each MOSFET is a power MOSFET in which a parasitic diode is formed between the source and drain.

Details of connection of the main circuit section will be described. Both terminals of the smoothing capacitor Cs1 are connected to voltage terminals VL and Vcom, respectively, and the voltage terminal Vcom is grounded. The VL side voltage terminal of the smoothing capacitor Cs1 is connected to one terminal of the smoothing capacitor Cs2, the other terminal of the smoothing capacitor Cs2 is connected to one terminal of the smoothing capacitor Cs3, and the other terminal of the smoothing capacitor Cs3 is connected to the smoothing capacitor Cs4. One terminal and the other terminal of the smoothing capacitor Cs4 are connected to the voltage terminal VH.
The source terminal of Mos1L is connected to the voltage terminal Vcom, the drain terminal is connected to the source terminal of Mos1H, and the drain terminal of Mos1H is connected to the voltage terminal VL. The source terminal of Mos2L is connected to the low voltage side terminal of the smoothing capacitor Cs2, the drain terminal of Mos2L is connected to the source terminal of Mos2H, and the drain terminal of Mos2H is connected to the high voltage side terminal of the smoothing capacitor Cs2. The source terminal of Mos3L is connected to the low voltage side terminal of the smoothing capacitor Cs3, the drain terminal of Mos3L is connected to the source terminal of Mos3H, and the drain terminal of Mos3H is connected to the high voltage side terminal of the smoothing capacitor Cs3. The source terminal of Mos4L is connected to the low voltage side terminal of the smoothing capacitor Cs4, the drain terminal of Mos4L is connected to the source terminal of Mos4H, and the drain terminal of Mos4H is connected to the high voltage side terminal of the smoothing capacitor Cs4.

  One end of the LC series LC12 is connected to a connection point between Mos1L and Mos1H, and the other end is connected to a connection point between Mos2L and Mos2H. One end of the LC series LC23 is connected to a connection point between Mos2L and Mos2H, and the other end is connected to a connection point between Mos3L and Mos3H. One end of the LC series LC34 is connected to a connection point between Mos3L and Mos3H, and the other end is connected to a connection point between Mos4L and Mos4H.

  The gate terminals of Mos1L and Mos1H are connected to the output terminal of the gate drive circuit 111, and the gate drive signals based on the voltage of the source terminal of Mos1L are input to the input terminal of the gate drive circuit 111. The gate drive circuit is a general bootstrap drive circuit, and includes a driver IC for driving a half-bridge inverter circuit, a capacitor for driving a MOSFET on the high voltage side, and the like. The gate terminals of Mos2L and Mos2H are connected to the output terminal of the gate drive circuit 112, and the gate drive signals based on the voltage of the source terminal of Mos2L are input to the input terminal of the gate drive circuit 112. The gate terminals of Mos3L and Mos3H are connected to the output terminal of the gate drive circuit 113, and the gate drive signal is input to the input terminal of the gate drive circuit 113 based on the voltage of the source terminal of the Mos3L. The gate terminals of Mos4L and Mos4H are connected to the output terminal of the gate drive circuit 114, and the gate drive signals based on the voltage at the source terminal of the Mos4L are input to the input terminal of the gate drive circuit 114.

  The gate drive signal for driving Mos1L is output from the photocoupler 121L, and the gate drive signal for driving Mos1H is output from the photocoupler 121H. Gate signals Gate1L and Gate1H are input to the photocouplers 121L and 121H. The photocoupler has a function of electrically isolating a signal on the control circuit side and a signal on the gate driving side and transmitting the signal by light, and converts the reference voltage of the signal. The gate drive signal for driving Mos2L is output from the photocoupler 122L, and the gate drive signal for driving Mos2H is output from the photocoupler 122H. Gate signals Gate2L and Gate2H are input to the photocouplers 122L and 122H. The gate drive signal for driving Mos3L is output from the photocoupler 123L, and the gate drive signal for driving Mos3H is output from the photocoupler 123H. Gate signals Gate3L and Gate3H are input to the photocouplers 123L and 123H. The gate drive signal for driving Mos4L is output from the photocoupler 124L, and the gate drive signal for driving Mos4H is output from the photocoupler 124H. Gate signals Gate4L and Gate4H are input to the photocouplers 124L and 124H.

The power supplies Vs1, Vs2, Vs3, and Vs4 are power supplies provided for driving the MOSFET, the gate drive circuit, and the photocoupler with reference to the source terminals of Mos1L, Mos2L, Mos3L, and Mos4L, respectively.
Further, as shown in FIG. 2, the gate signals Gate1L, Gate1H, Gate2L, Gate2H, Gate3L, Gate3H, Gate4L, and Gate4H are generated by the control circuit 13. In this case, a gate signal is generated in a signal processing circuit such as a microcomputer.

Next, the configuration of the LC serial bodies LC12, LC23, and LC34 will be described in detail. The capacitor elements Cr12A, Cr12B, Cr12C, Cr23A, Cr23B, and Cr34A have the same specifications, for example, an allowable current of 20 Arms and a capacitance value of 2.5 μF. The capacitor Cr12 of the LC series LC12 is configured by arranging three capacitor elements Cr12A, Cr12B, Cr12C in parallel, and the capacitor Cr23 of the LC series LC23 is configured by arranging two capacitor elements Cr23A, Cr23B in parallel. The capacitor Cr34 of the LC series LC34 is composed of one capacitor element Cr34A.
The inductor elements Lr12A, Lr12B, Lr12C, Lr23A, Lr23B, and Lr34A have the same specifications, for example, an allowable current of 20 Arms and an inductance value of 1.2 μH. The inductor Lr12 of the LC series LC12 is configured by arranging three inductor elements Lr12A, Lr12B, and Lr12C in parallel, and the inductor Lr23 of the LC series LC23 is configured by arranging two inductor elements Lr23A and Lr23B in parallel. The inductor Lr34 of the LC series body LC34 is configured by one inductor element Lr34A.

Thereby, the LC series body LC12 has a capacitance value of Cr12 of 7.5 μF (3 × 2.5 μF), an inductance value of Lr12 of 0.4 μH (1.2 μH / 3), and a total allowable current of 60 Arms. The LC series LC23 has a capacitance value of Cr23 of 5.0 μF (2 × 2.5 μF), an inductance value of Lr23 of 0.6 μH (1.2 μH / 2), and a total allowable current of 40 Arms. The capacitance value of Cr34 is 2.5 μF, the inductance value of Lr34 is 1.2 μH, and the total allowable current is 20 Arms.
The resonance period determined by the inductance value and the capacitance value of the LC series bodies LC12, LC23, and LC34 at each stage is approximately 10.9 μs and the resonance frequency is approximately 92 kHz at each stage.
As described above, the LC series bodies LC12, LC23, and LC34 are set such that the closer to the low voltage side, that is, the closer to the low voltage side voltage terminals VL and Vcom, the larger the capacitor capacity and the smaller the inductance, and the equal resonance period. is there.
In this case, the LC series bodies LC12 and LC23 are shown in which inductance elements and capacitor elements connected in series are connected in parallel, but the inductance elements and capacitor elements connected in parallel to each other are shown in FIG. A capacitor connected in parallel may be connected in series.

Next, the energy transfer operation (voltage boost operation) from voltage V1 to V2 will be described.
The capacitance values of the smoothing capacitors Cs1, Cs2, Cs3, and Cs4 are set to a sufficiently large value as compared with the capacitance value of the capacitor Cr of the LC series bodies LC12, LC23, and LC34. Since the voltage V1 input between the voltage terminals VL and Vcom is changed to a voltage V2 boosted about four times and output between the voltage terminals VH and Vcom, a load is connected between the voltage terminals VH and Vcom, and the voltage V2 Is lower than 4 × V1. In the steady state, the smoothing capacitor Cs1 is charged with the voltage V1, and the smoothing capacitors Cs2, Cs3, and Cs4 are charged with an average voltage of (V2-V1) / 3.
The circuit A1 is used in a driving inverter circuit that sends energy input between the voltage terminals VL-Vcom to the high voltage side by the on / off operation of MOSFETs (Mos1L, Mos1H). The circuits A2, A3, and A4 are used as rectifier circuits that rectify the current driven by the driving inverter circuit A1 and shift the energy to the high voltage side.

Gate signals Gate1H, Gate2H, Gate3H, Gate4H to the high-voltage side MOSFET, gate signals Gate1L, Gate2L, Gate3L, Gate4L to the low-voltage side MOSFET, and currents I12, I23, I34 flowing through the LC series bodies LC12, LC23, LC34 Is shown in FIG. Currents I12, I23, and I34 indicate total currents flowing through the inductance element Lr and the capacitor element Cr arranged in parallel in the LC series bodies LC12, LC23, and LC34. The currents I12, I23, and I34 are displayed with the current direction shown in FIG. 1 as positive. The MOSFET is turned on when the gate signal is at a high voltage.
As shown in FIG. 3, the gate signal is an on / off signal having a duty T of about 50% with a period T slightly larger than the resonance period determined by the LC serial bodies LC12, LC23, LC34. Note that t indicates a period of 1/2 of the resonance period, and 1a and 1b are on-pulses of the gate signal (hereinafter referred to as gate pulses). In this case, the period substantially coincides with the period t of 1/2 of the resonance period. Is generated.

When Mos1L, Mos2L, Mos3L, and Mos4L, which are the low-voltage side MOSFETs of the circuits A1 to A4, are turned on by the gate pulse 1b to the low-voltage side MOSFET, they are stored in the smoothing capacitors Cs1, Cs2, and Cs3 because there is a voltage difference. Some energy is transferred to the capacitors Cr12, Cr23, and Cr34 through the following path.
Cs1⇒Mos2L⇒Lr12⇒Cr12⇒Mos1L
Cs1⇒Cs2⇒Mos3L⇒Lr23⇒Cr23⇒Lr12⇒Cr12⇒Mos1L
Cs1⇒Cs2⇒Cs3⇒Mos4L⇒Lr34⇒Cr34⇒Lr23⇒Cr23⇒Lr12⇒Cr12⇒Mos1L

Next, when Mos1H, Mos2H, Mos3H, and Mos4H, which are the high-voltage side MOSFETs of the circuits A1 to A4, are turned on by the gate pulse 1a to the high-voltage side MOSFET, the capacitors Cr12, Cr23, and Cr34 are charged because there is a voltage difference. The energy transferred to the smoothing capacitors Cs2, Cs3, and Cs4 through the following path.
Mos1H⇒Cr12⇒Lr12⇒Mos2H⇒Cs2
Mos1H⇒Cr12⇒Lr12⇒Cr23⇒Lr23⇒Mos3H⇒Cs3⇒Cs2
Mos1H⇒Cr12⇒Lr12⇒Cr23⇒Lr23⇒Cr34⇒Lr34⇒Mos4H⇒Cs4⇒Cs3⇒Cs2

  As described above, in the boosting operation, energy is transferred from the smoothing capacitor Cs1 to the smoothing capacitors Cs2, Cs3, and Cs4 by charging and discharging the capacitors Cr12, Cr23, and Cr24. Then, the voltage V1 input between the voltage terminals VL and Vcom is changed to a voltage V2 boosted about four times and output between the voltage terminals VH and Vcom.

Next, the energy transition operation (voltage step-down operation) from voltage V2 to V1 will be described.
Since the voltage V2 input between the voltage terminals VH and Vcom is output to the voltage terminal VL-Vcom as a voltage V1 stepped down by about 1/4, a load is connected between the voltage terminals VL-Vcom, The voltage V2 is higher than 4 × V1.
In this case, the circuit A4 is used as a drive inverter circuit, and the circuits A1 to A3 are used as rectifier circuits.
In step-down operation, the gate signals Gate1H, Gate2H, Gate3H, Gate4H to the high-voltage side MOSFET, the gate signals Gate1L, Gate2L, Gate3L, Gate4L to the low-voltage side MOSFET, and the current I12 flowing through each LC series LC12, LC23, LC34, I23 and I34 are shown in FIG.
As shown in FIG. 4, the gate signal at the time of the step-down operation is the same as that at the time of the step-up operation, and is an on / off signal with a duty of about 50% with a period T slightly larger than the resonance period determined by the LC serial bodies LC12, LC23, LC34. . Reference numerals 1c and 1d denote gate pulses, which are generated in a period substantially coincident with a period t which is a half of the resonance period.

When Mos1H, Mos2H, Mos3H, and Mos4H, which are the high-voltage side MOSFETs of the circuits A1 to A4, are turned on by the gate pulse 1c to the high-voltage side MOSFET, there is a voltage difference, so that they are stored in the smoothing capacitors Cs2, Cs3, Cs4 Some energy is transferred to the capacitors Cr12, Cr23, and Cr34 through the following path.
Cs2⇒Cs3⇒Cs4⇒Mos4H⇒Lr34⇒Cr34⇒Lr23⇒Cr23⇒Lr12⇒Cr12⇒Mos1H
Cs2⇒Cs3⇒Mos3H⇒Lr23⇒Cr23⇒Lr12⇒Cr12⇒Mos1H
Cs2⇒Mos2H⇒Lr12⇒Cr12⇒Mos1H

Next, when Mos1L, Mos2L, Mos3L, and Mos4L, which are the low-voltage side MOSFETs of the circuits A1 to A4, are turned on by the gate pulse 1d to the low-voltage side MOSFET, the capacitors Cr12, Cr23, and Cr34 are charged because there is a voltage difference. The energy transferred to the smoothing capacitors Cs1, Cs2, and Cs3 through the following path.
Cr12⇒Lr12⇒Cr23⇒Lr23⇒Cr34⇒Lr34⇒Mos4L⇒Cs3⇒Cs2⇒Cs1⇒Mos1L
Cr12⇒Lr12⇒Cr23⇒Lr23⇒Mos3L⇒Cs2⇒Cs1⇒Mos1L
Cr12⇒Lr12⇒Mos2L⇒Cs1⇒Mos1L

  As described above, in the step-down operation, energy is transferred from the smoothing capacitors Cs2, Cs3, and Cs4 to the smoothing capacitor Cs1 by charging and discharging the capacitors Cr12, Cr23, and Cr34. Then, the voltage V2 input between the voltage terminals VH and Vcom is converted to a voltage V1 that is stepped down by about 1/4 and output between the voltage terminals VL and Vcom.

As shown in FIGS. 3 and 4, the directions of the currents I12, I23, and I34 flowing through the LC series bodies LC12, LC23, and LC34 of the respective voltage stages are reversed between the boost operation and the buck operation. In either case, I12: I23: I34 = 3: 2: 1. In this case, the maximum current value is an effective value of 60 Arms for I12, an effective value of 40 Arms for I23, and an effective value of 20 Arms for I34.
As described above, the LC series body LC12 has three capacitor elements and three inductor elements arranged in parallel, the LC series body LC23 has two capacitor elements and two inductor elements arranged in parallel, and the LC series body LC34 has Each of the capacitor element and the inductor element is composed of one piece. That is, the LC series bodies LC12, LC23, and LC34 of each voltage stage have a minimum required number of capacitor elements and inductor elements arranged in parallel according to the maximum current values of the flowing currents I12, I23, and I34. The closer to the voltage side, that is, the low voltage side voltage terminals VL and Vcom, the larger the capacitor capacity and the smaller the inductance, and the equal resonance periods are set.
For this reason, it is possible to easily optimize the size of the capacitors and inductors constituting the LC series bodies LC12, LC23, and LC34, and to realize a small and inexpensive device configuration. Moreover, since each LC serial body LC12, LC23, and LC34 is configured using the capacitor element and the inductor element having the same specifications, the component cost can be further reduced.

In this embodiment, the gate signal of the drive inverter circuit and the gate signal of the rectifier circuit are the same, but the gate pulse of the drive inverter circuit A1 is used during the boost operation, and the drive inverter circuit is used during the step-down operation. The A4 gate pulse may be longer than the gate pulse of the rectifier circuit. In the rectifier circuits A2 to A4 during the step-up operation and the rectifier circuit A1 during the step-down operation, a current flows through the parasitic diode of the MOSFET even when the gate signal is a low voltage. . In these rectifier circuits including the rectifier circuits A2 and A3 at the time of the step-down operation, the current flows backward if the voltage is high even if the gate signal has passed the period t which is a half of the resonance period. The reverse current is prevented by the parasitic diode of the MOSFET so as not to exceed the period t which is ½ of the period.
In this embodiment, since the resonance period of each LC series LC12, LC23, LC34 is equal, it is not necessary to change the gate signal of each rectifier circuit according to each resonance period, and the resonance phenomenon can be easily and effectively used. A highly efficient DC / DC power converter can be realized. Furthermore, the use of MOSFETs in the rectifier circuit can reduce conduction loss compared to diodes, further improving conversion efficiency.

  Further, the circuits A1 to A3 are used for the rectifier circuit during the step-down operation of the above embodiment. Although the circuit A1 is substantially used for rectification, the circuits A2 and A3 are also driving circuits that control the amount of energy transferred by the on / off operation of the MOSFET. In this case, as described above, since the high voltage period of the gate signal does not exceed the period t which is a half of the resonance period, the parasitic diode of the MOSFET prevents the backflow. I consider it.

  Further, in the above embodiment, in order to prevent the ON state of the high-voltage side MOSFET and the low-voltage side MOSFET from overlapping, a time margin of, for example, about 1 μs is provided when the switch between the high-voltage side MOSFET and the low-voltage side MOSFET is switched. . This time margin depends on the rise and fall times and response delay time of the semiconductor switch element to be used, but is set between 10 ns and 10 μs.

  In the above embodiment, a power MOSFET in which a parasitic diode is formed between the source and drain is used as the switching element in the drive inverter circuit and rectifier circuit. However, the on / off operation is controlled by a control electrode such as an IGBT. Other semiconductor switching elements that can be used may be used, in which case a diode connected in antiparallel is used, and this diode functions as a parasitic diode of the power MOSFET. Thereby, the same effect is acquired by the control similar to the said embodiment.

Embodiment 2. FIG.
In the first embodiment, the inductance values of the inductors of the LC series bodies LC12, LC23, and LC34 are inversely proportional to the maximum current value, and the capacitance value of the capacitor is proportional to the maximum current value. It is not a thing. For example, the maximum current value flowing through the LC series bodies LC12, LC23, and LC34 of each voltage stage is 80 Arms for Ir12, 53.3 Arms for Ir23, and 26.7 Arms for Ir34, and the capacitor element (2 .5μF / 20Arms) and inductor element (1.2μH / 20Arms) are used as follows. LC series body LC12 Lr12, Cr12 is a capacitor element, 4 inductor elements each in parallel, LC series body LC23 Lr23, Cr23 is a capacitor element, 3 inductor elements each in parallel, LC series body LC34 Lr34, Cr34 is a capacitor element, Two inductor elements are arranged in parallel.

Also in this embodiment, the LC series bodies LC12, LC23, LC34 of each voltage stage have a minimum necessary number of capacitor elements and inductor elements arranged in parallel according to the maximum current values of the flowing currents I12, I23, I34. The lower the voltage side, the larger the capacitor capacity and the smaller the inductance, and the resonance periods are set to be equal.
For this reason, the size of the capacitors and inductors constituting each LC serial body LC12, LC23, LC34 can be easily optimized using the predetermined capacitor elements and inductor elements, and a small and inexpensive apparatus configuration can be realized. Moreover, since each LC serial body LC12, LC23, and LC34 is configured using the capacitor element and the inductor element having the same specifications, the component cost can be further reduced.

Embodiment 3 FIG.
In the first embodiment, the LC series bodies LC12, LC23, and LC34 use the same specification capacitor elements and inductor elements, and the number of parallel arrangements is determined according to the maximum current values of the flowing currents I12, I23, and I34. .
In this embodiment, each LC series body LC12, LC23, LC34 is configured by connecting one capacitor element and one inductor element in series. As in the first embodiment, the LC series LC12 has a Cr12 capacitance value of 7.5 μF, an Lr12 inductance value of 0.4 μH, and an allowable current of 60 Arms. The LC series body LC23 has a Cr23 capacitance value of 5.0 μF, an Lr23 inductance value of 0.6 μH, and an allowable current of 40 Arms, and the LC series body LC34 has a Cr34 capacitance value of 2.5 μF and an Lr34 inductance value of 1. 2μH, allowable current 20Arms.

  In this case, based on the inductor Lr34 and capacitor Cr34 of the LC series LC34, the inductor Lr12 of the LC series LC12 reduces the number of windings of the inductor Lr34 to 1/3, and the capacitor Cr12 triples the electrode area of the capacitor Cr34. To. As a result, the inductor Lr12 can reduce the direct current resistance value to 1/3 and the magnetic flux density that determines magnetic saturation to 1/3, so that the allowable current value can be easily tripled. The capacitor Cr12 can easily triple the allowable current value by simply triple the electrode area of the capacitor Cr34. Similarly, the inductor Lr23 of the LC series LC23 halves the number of windings of the inductor Lr34, and the capacitor Cr23 doubles the electrode area of the capacitor Cr34. As a result, the inductor Lr23 can halve the direct current resistance value and halve the magnetic flux density that determines magnetic saturation, so that the allowable current value can be easily doubled. The capacitor Cr23 can easily double the allowable current value simply by doubling the electrode area of the capacitor Cr34.

Also in this embodiment, the LC series bodies LC12, LC23, and LC34 of each voltage stage have their capacitor capacity and inductance determined according to the maximum current values of the flowing currents I12, I23, and I34, and the capacitor capacity increases as the voltage becomes lower. The inductance is large and the resonance period is set to be equal.
For this reason, the size of the capacitors and inductors constituting each LC serial body LC12, LC23, LC34 can be easily optimized using the predetermined capacitor elements and inductor elements, and a small and inexpensive apparatus configuration can be realized.

Embodiment 4 FIG.
Next, a DC / DC power conversion apparatus according to Embodiment 4 of the present invention will be described with reference to the drawings. FIG. 5 shows a circuit configuration of a DC / DC power converter according to Embodiment 4 of the present invention.
In the fourth embodiment, a step-up DC / DC power converter that transfers energy from a voltage V1 between voltage terminals VL and Vcom to a voltage V2 between voltage terminals VH and Vcom is shown. Similar to the first embodiment, the voltage V2 is about four times the voltage V1, V1 is 50V, and V2 is about 200V.

  In this embodiment, as shown in FIG. 5, circuits A1a to A4a are used instead of the circuits A1 to A4 in the DC / DC power converter according to the first embodiment shown in FIG. 1, and the circuit A1a is a circuit A1. In the same configuration, circuits A2a to A4a replace two MOSFETs (Mos2L, Mos2H) (Mos3L, Mos3H) (Mos4L, Mos4H) with diodes (Di2L, Di2H) (Di3L, Dis3H) (Di4L, Di4H), respectively. Yes. That is, the drive inverter circuit A1a is configured by connecting two MOSFETs (Mos1L, Mos1H) as a low-voltage side switch and a high-voltage side switch in series and connecting between both terminals of the smoothing capacitor Cs1. The rectifier circuits A2a to A4a are configured by connecting two diodes (Di2L, Di2H) (Di3L, Di3H) (Di4L, Di4H) in series and connecting them between both terminals of the smoothing capacitors Cs2, Cs3, Cs4. The Accordingly, the gate drive circuit 111, the photocouplers 121H and 121L, the power supply Vs1 and the gate signals Gate1H and Gate1L for driving the MOSFET are deleted except for those for the MOSFETs (Mos1L and Mos1H). In this case, the control circuit 13a Outputs only gate signals Gate1H and Gate1L. Other configurations are the same as those of the first embodiment shown in FIG.

Next, the operation will be described.
The capacitance values of the smoothing capacitors Cs1, Cs2, Cs3, and Cs4 are set to a sufficiently large value as compared with the capacitance value of the capacitor Cr of the LC series bodies LC12, LC23, and LC34. Since the voltage V1 input between the voltage terminals VL and Vcom is changed to a voltage V2 boosted about four times and output between the voltage terminals VH and Vcom, a load is connected between the voltage terminals VH and Vcom, and the voltage V2 Is lower than 4 × V1. In the steady state, the smoothing capacitor Cs1 is charged with the voltage V1, and the smoothing capacitors Cs2, Cs3, and Cs4 are charged with an average voltage of (V2-V1) / 3.
The drive inverter circuit A1a sends the energy input between the voltage terminals VL and Vcom to the high voltage side by turning on and off the MOSFETs (Mos1L, Mos1H), and the rectifier circuits A2a to A4a are driven by the drive inverter circuit A1a The rectified current is rectified, and energy is transferred to the high voltage side.

FIG. 6 shows a gate signal Gate1H to the high-voltage side MOSFET, a gate signal Gate1L to the low-voltage side MOSFET, and currents I12, I23, and I34 flowing through the LC series bodies LC12, LC23, and LC34.
As shown in FIG. 6, the gate signal is an on / off signal having a duty T of about 50% with a period T slightly larger than the resonance period determined by the LC serial bodies LC12, LC23, LC34. Note that t indicates a period of 1/2 of the resonance period, and 1e and 1f are on-pulses (hereinafter referred to as gate pulses) of the gate signal, and in this case, periods substantially coincide with the period t of 1/2 of the resonance period. Is generated.
During the step-up operation of the first embodiment, the current flowing through the MOSFET in the rectifier circuit flows through the diode in this embodiment, and thus conduction loss occurs. However, the current is the same as in the first embodiment. The currents I12, I23, and I34 flowing through the LC series bodies LC12, LC23, and LC34 by the boosting operation are substantially the same as those in the first embodiment.

As described above, the LC series body LC12 has three capacitor elements and three inductor elements arranged in parallel, the LC series body LC23 has two capacitor elements and two inductor elements arranged in parallel, and the LC series body LC34 has Each of the capacitor element and the inductor element is composed of one piece. Further, the currents I12, I23, and I34 flowing through the LC series bodies LC12, LC23, and LC34 are I12: I23: I34 = 3: 2: 1. That is, as in the first embodiment, the LC series bodies LC12, LC23, LC34 of each voltage stage are the minimum necessary to arrange capacitor elements and inductor elements in parallel according to the maximum current values of the flowing currents I12, I23, I34. A limited number is determined, and the lower the voltage side, the larger the capacitor capacity and the smaller the inductance, and the equal resonance period is set.
For this reason, it is possible to easily optimize the size of the capacitors and inductors constituting the LC series bodies LC12, LC23, and LC34, and to realize a small and inexpensive device configuration. Moreover, since each LC serial body LC12, LC23, and LC34 is configured using the capacitor element and the inductor element having the same specifications, the component cost can be further reduced.

Embodiment 5. FIG.
Next, a DC / DC power conversion apparatus according to Embodiment 5 of the present invention will be described with reference to the drawings. FIG. 7 shows a circuit configuration of a DC / DC power conversion apparatus according to Embodiment 5 of the present invention.
In the fifth embodiment, a step-down DC / DC power converter that transfers energy from a voltage V2 between voltage terminals VH and Vcom to a voltage V1 between voltage terminals VL and Vcom is shown. Similar to the first embodiment, the voltage V2 is about four times the voltage V1, V1 is 50V, and V2 is about 200V.
In this embodiment, as shown in FIG. 7, instead of the circuits A1 to A4 in the DC / DC power converter according to the first embodiment shown in FIG. 1, circuits A1b to A4b are used, and the circuits A2b to A4b are A circuit A1b having the same configuration as the circuits A2 to A4 has two MOSFETs (Mos1L and Mos1H) replaced with diodes (Di1L and Di1H), respectively. That is, the drive inverter circuit A4b and the rectifier circuits A2b and A3b are configured by connecting two MOSFETs in series as a low-voltage side switch and a high-voltage side switch and connecting them between both terminals of the smoothing capacitors Cs4, Cs2, and Cs3. Is done. The rectifier circuit A1b is configured by connecting two diodes (Di1L, Di1H) in series and connecting between both terminals of the smoothing capacitor Cs1. Accordingly, the gate drive circuit 111, the photocouplers 121H and 121L, the power supply Vs1, and the gate signals Gate1H and Gate1L for driving the MOSFET in the circuit A1 in the first embodiment are deleted. In this case, the gate signal is output from the control circuit. Only Gate2H to Gate4H and Gate2L to Gate4L are output. Other configurations are the same as those of the first embodiment shown in FIG.

During the step-down operation of the first embodiment, the current flowing through the MOSFET in the rectifier circuit A1 flows through the diode in the rectifier circuit A1b in this embodiment, so that conduction loss occurs. By the step-down operation similar to that of the first embodiment, the currents I12, I23, I34 flowing through the LC series bodies LC12, LC23, LC34 are substantially the same as in the first embodiment, and I12: I23: I34 = 3: 2: 1
That is, as in the first embodiment, the LC series bodies LC12, LC23, LC34 of each voltage stage are the minimum necessary to arrange capacitor elements and inductor elements in parallel according to the maximum current values of the flowing currents I12, I23, I34. A limited number is determined, and the lower the voltage side, the larger the capacitor capacity, the smaller the inductance, and the equal resonance period.
For this reason, it is possible to easily optimize the sizes of capacitors and inductors constituting each LC series body LC12, LC23, and LC34, and to realize a small and inexpensive device configuration. Moreover, since each LC serial body LC12, LC23, and LC34 is configured using the capacitor element and the inductor element having the same specifications, the component cost can be further reduced.

  In the fourth and fifth embodiments, the LC serial bodies LC12, LC23, and LC34 may be configured as shown in the second and third embodiments, and each has the same effect.

Embodiment 6 FIG.
So far, the input / output voltages (V1, V2) have been described for non-insulated type embodiments. Here, a DC / DC power conversion device including a transformer and having isolated input / output voltages is shown.
8 and 9 show a circuit configuration of a DC / DC power converter according to Embodiment 6 of the present invention, FIG. 8 shows a main circuit, and FIG. 9 shows a control circuit.
In the sixth embodiment, energy transfer is bidirectional between the voltage V1 between the low voltage side voltage terminals VL and Vcom and the voltage V2 between the high voltage side voltage terminals VH and Vcom having different reference voltage levels. A step-up / step-down DC / DC power converter having a function to be performed is described. The voltage V2 is about 8 times the voltage V1.
As shown in FIG. 8, a circuit B0 as a first circuit and circuits B1 to B4 as second circuits are provided. The circuit B0 and the circuit B1 are connected via a transformer Tr having a winding ratio of 1: 1. Connected.

The circuit B0 includes a smoothing capacitor Cs0 that smoothes the voltage V1 and also functions as a voltage source for energy transfer, and a plurality of MOSFETs (Mos0AH, Mos0AL, Mos0BH, Mos0BL).
One end of the primary winding of the transformer Tr is coupled to a connection point between the source terminal of Mos0AH and the drain terminal of Mos0AL, and the other end is coupled to a connection point between the source terminal of Mos0BH and the drain terminal of Mos0BL. The drain terminals of Mos0AH and Mos0BH are connected to the voltage terminal VL, and the source terminals of Mos0AL and Mos0BL are connected to the voltage terminal Vcom0. A smoothing capacitor Cs0 is disposed between the voltage terminals VL and Vcom0.

  The circuits B1 to B4 are similar in configuration to the circuits A1 to A4 of the first embodiment, and capacitors Cr12 (Cr12A, Cr12B, Cr12C), Cr23 (Cr23A, Cr23B) are provided between the intermediate terminals of the adjacent circuits B1 to B4. , Cr34 (Cr34A) and inductor Lr12 (Lr12A, Lr12B, Lr12C), Lr23 (Lr23A, Lr23B), Lr34 (Lr34A) are connected in series, and LC series bodies LC12, LC23, LC34 that function as energy transfer elements are connected Is done. In addition, an LC series body LC01 in which a capacitor Cr01 (Cr01A, Cr01B, Cr01C, Cr01D) and an inductor Lr01 (Lr01A, Lr01B, Lr01C, Lr01D) are connected in series to an intermediate terminal (a connection point between Mos1H and Mos1L) of the circuit B1. The other end of the LC series body LC01 is connected to one end of the secondary winding of the transformer Tr. Thereby, each LC serial body LC01, LC12, LC23, LC34 and the secondary winding of the transformer Tr are connected in series. The other end of the secondary winding of the transformer Tr is connected to the voltage terminal Vcom.

As shown in FIG. 9, the gate signals Gate0AL, Gate0AH, Gate0BL, Gate0BH, Gate1L, Gate1H, Gate2L, Gate2H, Gate3L, Gate3H, Gate4L, and Gate4H are generated by the control circuit 13b. In this case, a gate signal is generated in a signal processing circuit such as a microcomputer.
Gate signals Gate0AH and Gate0AL for controlling on / off of Mos0AH and Mos0AL are supplied from the control circuit 13b to the gate drive circuit 110A via the photocouplers 120AH and 120AL, and Mos0AH and Mos0AL are driven by the gate drive circuit 110A. Gate signals Gate0BH and Gate0BL for controlling on / off of Mos0BH and Mos0BL are supplied from the control circuit 13b to the gate drive circuit 110B via the photocouplers 120BH and 120BL, and Mos0BH and Mos0BL are driven by the gate drive circuit 110B. The gate drive circuit and the photocoupler are driven by the power supply Vs0.

Next, the configuration of the LC serial bodies LC01, LC12, LC23, and LC34 will be described in detail. Each capacitor element Cr01A, Cr01B, Cr01C, Cr01D, Cr12A, Cr12B, Cr12C, Cr23A, Cr23B, and Cr34A have the same specifications, for example, an allowable current of 20 Arms and a capacitance value of 2.5 μF.
The capacitor Cr01 of the LC series LC01 is configured by arranging four capacitor elements Cr01A, Cr01B, Cr01C, Cr01D in parallel, and the capacitor Cr12 of the LC series LC12 is configured by arranging three capacitor elements Cr12A, Cr12B, Cr12C in parallel. The capacitor Cr23 of the LC series body LC23 is configured by arranging two capacitor elements Cr23A and Cr23B in parallel, and the capacitor Cr34 of the LC series body LC34 is configured by one capacitor element Cr34A.
The inductor elements Lr01A, Lr01B, Lr01C, Lr01D, Lr12A, Lr12B, Lr12C, Lr23A, Lr23B, and Lr34A have the same specifications, for example, an allowable current of 20 Arms and an inductance value of 1.2 μH. The inductor Lr01 of the LC series LC01 is configured by arranging four inductor elements Lr01A, Lr01B, Lr01C, and Lr01D in parallel. The inductor Lr12 of the LC series LC12 is configured by three inductor elements Lr12A, Lr12B, and Lr12C. The inductor Lr23 of the LC series body LC23 is configured by arranging two inductor elements Lr23A and Lr23B in parallel, and the inductor Lr34 of the LC series body LC34 is configured by one inductor element Lr34A.

As a result, the LC series body LC01 has a capacitance value of Cr01 of 10.0 μF (4 × 2.5 μF), an inductance value of Lr01 of 0.3 μH (1.2 μH / 4), and a total allowable current of 80 Arms. The LC series LC12 has a Cr12 capacitance value of 7.5 μF (3 × 2.5 μF), an Lr12 inductance value of 0.4 μH (1.2 μH / 3), and a total allowable current of 60 Arms. The LC series LC23 has a capacitance value of Cr23 of 5.0 μF (2 × 2.5 μF), an inductance value of Lr23 of 0.6 μH (1.2 μH / 2), and a total allowable current of 40 Arms. The capacitance value of Cr34 is 2.5 μF, the inductance value of Lr34 is 1.2 μH, and the total allowable current is 20 Arms.
The resonance period determined by the inductance value and the capacitance value of the LC series bodies LC01, LC12, LC23, and LC34 at each stage is approximately equal to about 10.9 μs and the resonance frequency is approximately 92 kHz at each stage.

As described above, the LC series bodies LC01, LC12, LC23, and LC34 are configured such that the closer to the low voltage side, that is, the closer to the low voltage side voltage terminal, the larger the capacitor capacity, the smaller the inductance, and the equal resonance period.
In this case, although the LC series bodies LC01, LC12, and LC23 are illustrated by connecting in parallel an inductance element and a capacitor element, the inductance element and the capacitor element are connected in parallel. Alternatively, capacitors connected in parallel to each other may be connected in series.

Next, the energy transfer operation (voltage boost operation) from voltage V1 to V2 will be described.
The capacitance values of the smoothing capacitors Cs0 to Cs4 are set to a sufficiently large value as compared with the capacitance values of the capacitors Cr of the LC series bodies LC01, LC12, LC23, and LC34.
As described above, since the voltage V1 input between the voltage terminals VL and Vcom0 is converted to the voltage V2 boosted about 8 times and output between the voltage terminals VH and Vcom, the voltage V2 is lower than 8 × V1. It is a value.
The circuit B0 is used in a drive inverter circuit that sends energy input between the voltage terminals VL and Vcom to the high voltage side by on / off operation of MOSFETs (Mos1L, Mos1H). The circuits B1 to B4 are used as a rectifier circuit that rectifies the current driven by the driving inverter circuit B0 and shifts the energy to the high voltage side.

Gate signals Gate0AH, Gate0BL, Gate1H, Gate2H, Gate3H, Gate4H and gate signals Gate0AL, Gate0BH, Gate1L, Gate2L, Gate3L, Gate4L, and currents I01, I12, I23 flowing through the LC serial bodies LC01, LC12, LC23, LC34, FIG. 10 shows I34. The currents I01, I12, I23, and I34 indicate all currents flowing through the inductance element Lr and the capacitor element Cr that are arranged in parallel in the LC serial bodies LC01, LC12, LC23, and LC34. The currents I01, I12, I23, and I34 are displayed with the current direction shown in FIG. 8 as positive. The MOSFET is turned on when the gate signal is at a high voltage.
As shown in FIG. 10, the gate signal is an on / off signal having a duty T of about 50% with a period T slightly larger than the resonance period determined by the LC serial bodies LC01, LC12, LC23, and LC34. Note that t indicates a period of 1/2 of the resonance period, and 1g and 1h are gate pulses, and in this case, they are generated in a period substantially coincident with the period t of 1/2 of the resonance period.

When the gate pulse 1h turns on Mos0AL and Mos0BH of the drive inverter circuit B0 and the low-voltage side MOSFETs Mos1L, Mos2L, Mos3L, and Mos4L of the rectifier circuits B1 to B4, the negative voltage direction of the primary winding of the transformer Tr At the same time, the voltage V1 is generated in the negative voltage direction of the secondary winding, and a part of the energy stored in the smoothing capacitors Cs0, Cs1, Cs2, and Cs3 is transferred to Cr01 through the path shown below. , Transition to Cr12, Cr23, Cr34.
Vcom⇒Mos1L⇒Lr01⇒Cr01⇒Tr
Cs1⇒Mos2L⇒Lr12⇒Cr12⇒Lr01⇒Cr01⇒Tr
Cs1⇒Cs2⇒Mos3L⇒Lr23⇒Cr23⇒Lr12⇒Cr12⇒Lr01⇒Cr01⇒Tr
Cs1⇒Cs2⇒Cs3⇒Mos4L⇒Lr34⇒Cr34⇒Lr23⇒Cr23⇒Lr12⇒Cr12⇒Lr01⇒Cr01⇒Tr

Next, when the Mos0AH and Mos0BL of the driving inverter circuit B0 and the high-voltage side MOSFETs Mos1H, Mos2H, Mos3H, and Mos4H of the rectifier circuits B1 to B4 are turned on by the gate pulse 1g, the positive voltage of the primary winding of the transformer Tr At the same time as the voltage V1 is applied in the direction, the voltage V1 is generated in the positive voltage direction of the secondary winding, and the energy charged in the capacitors Cr01, Cr12, Cr23, Cr34 is the smoothing capacitor Cs1, Move to Cs2, Cs3, Cs4.
Tr⇒Cr01⇒Lr01⇒Mos1H⇒Cs1
Tr⇒Cr01⇒Lr01⇒Cr12⇒Lr12⇒Mos2H⇒Cs2⇒Cs1
Tr⇒Cr01⇒Lr01⇒Cr12⇒Lr12⇒Cr23⇒Lr23⇒Mos3H⇒Cs3⇒Cs2⇒Cs1
Tr⇒Cr01⇒Lr01⇒Cr12⇒Lr12⇒Cr23⇒Lr23⇒Cr34⇒Lr34⇒Mos4H⇒Cs4⇒Cs3⇒Cs2⇒Cs1

  As described above, in the boosting operation, energy is transferred from the smoothing capacitors Cs0, Cs1, Cs2, and Cs3 to the smoothing capacitors Cs1, Cs2, Cs3, and Cs4 by charging and discharging the capacitors Cr01, Cr12, Cr23, and Cr34. Then, the voltage V1 inputted between the voltage terminals VL and Vcom0 is changed to a voltage V2 boosted by about 8 times and outputted between the voltage terminals VH and Vcom.

Next, the energy transition operation (voltage step-down operation) from voltage V2 to V1 will be described.
Since the voltage V2 input between the voltage terminals VH and Vcom is converted to the voltage V1 that is stepped down by about 1/8, and output between the voltage terminals VL and Vcom, a load is connected between the voltage terminals VL and Vcom. The voltage V2 is higher than 8 × V1.
In this case, the circuit B4 is used as a drive inverter circuit, and the circuits B0 to B3 are used as rectifier circuits.
In the step-down operation, the gate signal and the currents I01, I12, I23, and I34 flowing through the LC serial bodies LC01, LC12, LC23, and LC34 are not shown, but the gate signal is the same as in the step-up operation, and the currents I01, I12 , I23 and I34 are opposite in direction to the step-up operation.

When the gate pulse causes Mos4H of the drive inverter circuit B4 and Mos0AH, Mos0BL, Mos1H, Mos2H, and Mos3H of the rectifier circuits B0 to B3 to be turned on, a part of energy stored in the smoothing capacitors Cs4, Cs3, Cs2, and Cs1 Moves to capacitors Cr34, Cr23, Cr12, and Cr01 through the following path.
Cs1⇒Cs2⇒Cs3⇒Cs4⇒Mos4H⇒Lr34⇒Cr34⇒Lr23⇒Cr23⇒Lr12⇒Cr12⇒Lr01⇒Cr01⇒Tr
Cs1⇒Cs2⇒Cs3⇒Mos3H⇒Lr23⇒Cr23⇒Lr12⇒Cr12⇒Lr01⇒Cr01⇒Tr
Cs1⇒Cs2⇒Mos2H⇒Lr12⇒Cr12⇒Lr01⇒Cr01⇒Tr
Cs1⇒Mos1H⇒Lr01⇒Cr01⇒Tr
Due to the current flowing in this way, a voltage is generated in the positive voltage direction of the primary winding of the transformer Tr, and energy is transferred to the smoothing capacitor Cs0 through the following path.
Tr⇒Mos0AH⇒Cs0⇒Mos0BL

Next, when Mos4L of the driving inverter circuit B4 and Mos0AL, Mos0BH, Mos1L, Mos2L, and Mos3L of the rectifier circuits B0 to B3 are turned on by the gate pulse, the energy stored in the capacitors Cr34, Cr23, Cr12, and Cr01 is as follows. It moves to smoothing capacitors Cs3, Cs2, and Cs1 by the path.
Cr01⇒Lr01⇒Cr12⇒Lr12⇒Cr23⇒Lr23⇒Cr34⇒Lr34⇒Mos4L⇒Cs3⇒Cs2⇒Cs1⇒Tr
Cr01⇒Lr01⇒Cr12⇒Lr12⇒Cr23⇒Lr23⇒Mos3L⇒Cs2⇒Cs1⇒Tr
Cr01⇒Lr01⇒Cr12⇒Lr12⇒Mos2L⇒Cs1⇒Tr
Cr01⇒Lr01⇒Mos1L⇒Tr
The current flowing in this way generates a voltage in the negative voltage direction of the primary winding of the transformer Tr, and energy is transferred to the smoothing capacitor Cs0 through the following path.
Tr⇒Mos0BH⇒Cs0⇒Mos0AL

  In this way, energy is transferred from the smoothing capacitors Cs1, Cs2, Cs3, and Cs4 to the smoothing capacitors Cs0, Cs1, Cs2, and Cs3 by charging and discharging the capacitors Cr01, Cr12, Cr23, and Cr34. Then, the voltage V2 input between the voltage terminals VH and Vcom is changed to a voltage V1 that is stepped down by about 1/8 and output between the voltage terminals VL and Vcom0.

The directions of the currents I01, I12, I23, and I34 flowing through the LC serial bodies LC01, LC12, LC23, and LC34 of the respective voltage stages are reversed between the step-up operation and the step-down operation, but their ratios are all I01: I12: I23: I34 = 4: 3: 2: 1. In this case, the maximum current value is an effective value of 80 Arms for I01, an effective value of 60 Arms for I12, an effective value of 40 Arms for I23, and an effective value of 20 Arms for I34.
As described above, the LC series body LC01 has four capacitor elements and four inductor elements arranged in parallel, the LC series body LC12 has three capacitor elements and three inductor elements arranged in parallel, and the LC series body LC23 has Two capacitor elements and two inductor elements are arranged in parallel, and the LC series LC34 is composed of one capacitor element and one inductor element. That is, for the LC series bodies LC01, LC12, LC23, and LC34 of each voltage stage, the minimum necessary number of capacitor elements and inductor elements arranged in parallel is determined according to the maximum current value of the flowing currents I01, I12, I23, and I34. Thus, the closer to the low voltage side, that is, the closer to the low voltage side voltage terminal, the larger the capacitor capacity and the smaller the inductance, and the resonance periods are set to be equal.
Therefore, the size of the capacitors and inductors constituting each LC serial body LC01, LC12, LC23, LC34 can be easily optimized, and a small and inexpensive device configuration can be realized. In addition, since each LC serial body LC01, LC12, LC23, and LC34 is configured using the capacitor element and the inductor element having the same specifications, the component cost can be further reduced.

Also in this embodiment, similarly to the first embodiment, the gate pulse of the drive inverter circuit may be made longer than the gate pulse of the rectifier circuit. In the rectifier circuit, even when the gate signal is at a low voltage, current flows through the parasitic diode of the MOSFET, so that energy can be transferred in a period t that is half the resonance period. At this time, in the rectifier circuit, even if the gate signal passes the period t that is half the resonance period, the current flows backward if the voltage is high, so the period of the high voltage does not exceed the period t that is 1/2 the resonance period. In this way, the reverse current is prevented by the parasitic diode of the MOSFET.
In addition, since the resonance cycle of each LC series LC01, LC12, LC23, LC34 is equal, there is no need to change the gate signal of each rectifier circuit according to each resonance cycle, and the resonance phenomenon can be used effectively and efficiently. The DC / DC power converter can be realized. Furthermore, the use of MOSFETs in the rectifier circuit can reduce conduction loss compared to diodes, further improving conversion efficiency.

  In the step-down operation, the circuit B0 is substantially used for rectification, but the circuits B1 to B3 are also driving circuits that control the amount of energy transferred by the on / off operation of the MOSFET. In this case, as described above, since the high voltage period of the gate signal does not exceed the period t which is a half of the resonance period, the circuit B1 to B3 is also regarded as a rectifier circuit.

Embodiment 7 FIG.
In this embodiment, a DC / DC power conversion apparatus having a circuit configuration different from that of the above-described Embodiment 6 and including a transformer and having isolated input / output voltages will be described.
FIG. 11 shows a part of the circuit configuration of the DC / DC power converter according to Embodiment 7 of the present invention, and shows a transformer Tr and a circuit B0a on the primary winding side of the transformer Tr. Other portions, that is, the secondary winding side of the transformer Tr are the same as those shown in FIG. 8 of the sixth embodiment.
As shown in FIG. 11, on the primary side of the transformer Tr, two windings of a first winding and a second winding are wound, a first terminal at the beginning of winding of the first winding, It has a second terminal to which the winding end of the first winding and the winding start of the second winding are connected, and a third terminal at the winding end of the second winding. The number of turns of each of the three windings including the secondary winding is the same. The circuit B0a includes a smoothing capacitor Cs0 and two MOSFETs (Mos0AL, Mos0BL).

The second terminal on the primary side of the transformer Tr is connected to the voltage terminal VL, the first terminal is connected to the drain terminal of Mos0AL, and the third terminal is connected to the drain terminal of Mos0BL. The source terminals of Mos0AL and Mos0BL are connected to the reference voltage Vcom0. A smoothing capacitor Cs0 is disposed between the voltage terminals VL and Vcom0. On / off of Mos0AL and Mos0BL is controlled by the gate signals Gate0AL and Gate0BL via the photocouplers 120A and 120B and the gate drive circuit 110.
The operation will be described below.
When boosting using this DC / DC power converter, the circuit B0a is used as a drive inverter circuit, the circuits B1 to B4 are used as rectifier circuits, and the circuit B4 is used as a drive inverter circuit during voltage reduction, and the circuits B0a and B1 are used. ~ B3 are used in the rectifier circuit.
During the boosting operation, the voltage V1 is generated in the positive voltage direction on the secondary side of the transformer Tr by turning on Mos0BL, and the voltage V1 is generated in the negative voltage direction on the secondary side by turning on Mos0AL. Other operations are the same as those in the sixth embodiment. During step-down operation, when negative voltage occurs on the secondary side, Cs0 is charged via the route Tr → Cs0 → Mos0BL. When positive voltage occurs on the secondary side, Cs0 is charged via the route Tr → Cs0 → Mos0AL. . Other operations are the same as those in the sixth embodiment.

In this embodiment, the configuration of the LC serial bodies LC01, LC12, LC23, and LC34 of each voltage stage and the behavior of the flowing currents I01, I12, I23, and I34 are the same as those in the sixth embodiment. That is, the LC series bodies LC01, LC12, LC23, and LC34 have a minimum required number of capacitor elements and inductor elements arranged in parallel according to the maximum current values of the currents I01, I12, I23, and I34. The capacitor capacity is larger and the inductance is smaller toward the side, and the resonance periods are set to be equal.
For this reason, the same effect as the sixth embodiment can be obtained, and the size of capacitors and inductors constituting each LC series LC01, LC12, LC23, LC34 can be easily optimized, and a small and inexpensive device configuration can be realized. it can. In addition, since each LC serial body LC01, LC12, LC23, and LC34 is configured using the capacitor element and the inductor element having the same specifications, the component cost can be further reduced.

In the sixth and seventh embodiments, the LC serial bodies LC01, LC12, LC23, and LC34 may be configured as shown in the second and third embodiments, and each has the same effect.
Further, similarly to the fourth and fifth embodiments, the MOSFET of the predetermined rectifier circuit can be replaced with a diode, so that only a step-up operation or a step-down operation can be performed.

  In the sixth and seventh embodiments, one circuit B0 (B0a) is arranged on the primary side of the transformer Tr, and a plurality of circuits B1 to B4 are arranged on the secondary side. Although the secondary winding of the transformer Tr is connected in series, the number of circuits arranged on the primary side and the secondary side is not limited to this, and each LC series circuit arranged between adjacent circuits May be connected to the primary or secondary winding of the transformer Tr in series.

Embodiment 8 FIG.
Next, a DC / DC power converter according to an eighth embodiment of the present invention will be described. FIG. 12 shows a circuit configuration of a DC / DC power conversion apparatus according to Embodiment 8 of the present invention. The configuration of the control circuit is the same as that shown in FIG. 2 of the first embodiment.
In the eighth embodiment, the voltage V1 between the low voltage side voltage terminal VL and Vcom and the voltage raising / lowering function having a function of bidirectionally transferring energy between the voltage V2 between the high voltage side voltage terminals VHh and VHl. A pressure type DC / DC power converter will be described. The voltage V2 is about four times the voltage V1, where V1 is 50V and V2 is about 200V.
As shown in FIG. 12, the circuits A1c to A4c having different configurations of the circuits A1 to A4 and the LC serial body LC12 in the first embodiment shown in FIG. 1 are used, and the connection configuration of the voltage terminals is different. That is, the positive voltage terminal VL on the low voltage side is connected to the connection point between the smoothing capacitors Cs3 and Cs4, and the negative electrode terminal Vcom on the low voltage side grounded is connected to the connection point between the smoothing capacitors Cs2 and Cs3. The positive voltage terminal VHh on the high voltage side is connected to the high voltage side terminal of the smoothing capacitor Cs4, and the negative voltage terminal VHl on the high voltage side is connected to the low voltage side terminal of the smoothing capacitor Cs1.

In the LC series body LC12 connected between the circuit A1c and the circuit A2c, the capacitor Cr12 is composed of one capacitor element Cr12A, and the inductor Lr12 is composed of one inductor element Lr12A. In the LC series body LC23 connected between the circuit A2c and the circuit A3c, the capacitor Cr23 is composed of two capacitor elements Cr23A and Cr23B, and the inductor Lr23 is composed of two inductor elements Lr23A and Lr23B. Yes. In the LC series body LC34 connected between the circuit A3c and the circuit A4c, the capacitor Cr34 is composed of one capacitor element Cr34A, and the inductor Lr34 is composed of one inductor element Lr34A.
As in the first embodiment, the capacitor elements Cr12A, Cr23A, Cr23B, and Cr34A have the same specifications, for example, an allowable current of 20 Arms and a capacitance value of 2.5 μF, and the inductor elements Lr12A, Lr23A, Lr23B, and Lr34A have the same specifications. For example, the allowable current is 20 Arms and the inductance value is 1.2 μH.
As a result, the LC series LC12 has a Cr12 capacitance value of 2.5 μF, an Lr12 inductance value of 1.2 μH, and a total allowable current of 20 Arms. The LC series LC23 has a capacitance value of Cr23 of 5.0 μF (2 × 2.5 μF), an inductance value of Lr23 of 0.6 μH (1.2 μH / 2), and a total allowable current of 40 Arms. The capacitance value of Cr34 is 2.5 μF, the inductance value of Lr34 is 1.2 μH, and the total allowable current is 20 Arms. The resonance period determined by the inductance value and the capacitance value of the LC series bodies LC12, LC23, and LC34 at each stage is approximately 10.9 μs and the resonance frequency is approximately 92 kHz at each stage.

As described above, the LC series bodies LC12, LC23, and LC34 have a larger number of capacitor elements and inductor elements arranged in parallel as they are closer to the low voltage side voltage terminals VL and Vcom, and have a large capacitor capacity, a small inductance, and resonance. The periods are set to be equal.
In this case as well, although the LC series body LC23 is configured by connecting in parallel an inductance element and a capacitor element in parallel, the inductance in which the inductance element is connected in parallel and the capacitor element are parallel to each other. A connected capacitor may be connected in series.

Next, the energy transfer operation (voltage boost operation) from voltage V1 to V2 will be described.
The capacitance values of the smoothing capacitors Cs1, Cs2, Cs3, and Cs4 are set to a sufficiently large value as compared with the capacitance value of the capacitor Cr of the LC series bodies LC12, LC23, and LC34. Since the voltage V1 input between the voltage terminals VL and Vcom is changed to a voltage V2 boosted about four times and output between the voltage terminals VHh and VHl, a load is connected between the voltage terminals VHh and VHl, and the voltage V2 Is lower than 4 × V1. In the steady state, the smoothing capacitor Cs3 is charged with the voltage V1, and the smoothing capacitors Cs1, Cs2, and Cs4 are charged with an average voltage of (V2-V1) / 3.
The circuit A3c is used in a drive inverter circuit that sends energy input between the voltage terminals VL and Vcom on the low voltage side between the voltage terminals VHh and VHl on the high voltage side by turning on and off the MOSFETs (Mos3L and Mos3H). . The circuits A1c, A2c, and A4c are used as rectifier circuits that rectify the current driven by the driving inverter circuit A3c and shift the energy to the high voltage side.

Gate signals Gate1H, Gate2H, Gate3H, Gate4H to the high-voltage side MOSFET, gate signals Gate1L, Gate2L, Gate3L, Gate4L to the low-voltage side MOSFET, and currents I12, I23, I34 flowing through the LC series bodies LC12, LC23, LC34 Is shown in FIG. Currents I12, I23, and I34 indicate total currents flowing through the inductance element Lr and the capacitor element Cr arranged in parallel in the LC series bodies LC12, LC23, and LC34. The currents I12, I23, and I34 are displayed with the current direction shown in FIG. 12 as positive. The MOSFET is turned on when the gate signal is at a high voltage.
As shown in FIG. 13, the gate signal is an on / off signal having a duty T of about 50% with a period T slightly larger than the resonance period determined by the LC series bodies LC12, LC23, LC34. Note that t indicates a period of 1/2 of the resonance period, 1i and 1j are on-pulses of the gate signal (hereinafter referred to as gate pulses), and in this case, a period that substantially coincides with the period t of 1/2 of the resonance period. Is generated.

When Mos1L, Mos2L, Mos3L, and Mos4L, which are the low-voltage side MOSFETs of the circuits A1c to A4c, are turned on by the gate pulse 1j to the low-voltage side MOSFET, there is a voltage difference, so some energy stored in the smoothing capacitor Cs3 Is transferred to the capacitor Cr34, and the energy charged in the capacitors Cr23 and Cr12 is transferred to the smoothing capacitors Cs2 and Cs1 through the following path.
Cs3⇒Mos4L⇒Lr34⇒Cr34⇒Mos3L
Cr23⇒Lr23⇒Mos3L⇒Cs2⇒Mos2L
Cr12⇒Lr12⇒Cr23⇒Lr23⇒Mos3L⇒Cs2⇒Cs1⇒Mos1L

Next, when Mos1H, Mos2H, Mos3H, and Mos4H, which are the high-voltage side MOSFETs of the circuits A1c to A4c, are turned on by the gate pulse 1i to the high-voltage side MOSFET, there is a voltage difference, so the energy charged in the capacitor Cr34 is smoothed. A part of energy stored in the smoothing capacitors Cs2 and Cs3 is transferred to the capacitors Cs4 and Crs23 through the following path.
Cr34⇒Lr34⇒Mos4H⇒Cs4⇒Mos3H
Cs3⇒Mos3H⇒Lr23⇒Cr23⇒Mos2H
Cs2⇒Cs3⇒Mos3H⇒Lr23⇒Cr23⇒Lr12⇒Cr12⇒Mos1H

  As described above, energy is transferred from the smoothing capacitor Cs3 to the smoothing capacitors Cs1, Cs2, and Cs4 by charging and discharging the capacitors Cr12, Cr23, and Cr34. Then, the voltage V1 input between the voltage terminals VL and Vcom is changed to a voltage V2 boosted about four times and output between the voltage terminals VHh and VHl.

Next, the energy transition operation (voltage step-down operation) from voltage V2 to V1 will be described.
Since the voltage V2 input between the voltage terminals VHh and VHl on the high voltage side is output to the voltage V1 that has been stepped down by about 1/4, the voltage V1 is output between the voltage terminals VL and Vcom. Are connected, and the voltage V2 is higher than 4 × V1.
In this case, the circuit A4c is used as a drive inverter circuit, and the circuits A1c to A3c are used as rectifier circuits.
In step-down operation, the gate signals Gate1H, Gate2H, Gate3H, Gate4H to the high-voltage side MOSFET, the gate signals Gate1L, Gate2L, Gate3L, Gate4L to the low-voltage side MOSFET, and the current I12 flowing through each LC series LC12, LC23, LC34, I23 and I34 are shown in FIG.
As shown in FIG. 14, the gate signal at the time of the step-down operation is the same as that at the time of the step-up operation, and is an on / off signal having a duty of about 50% with a period T slightly larger than the resonance period determined by the LC series bodies LC12, LC23, LC34. . Reference numerals 1k and 1l denote gate pulses, which are generated in a period substantially coincident with the period t which is a half of the resonance period.

When the high-voltage side MOSFETs Mos1H, Mos2H, Mos3H, and Mos4H of each circuit A1c to A4c are turned on by the gate pulse 1k to the high-voltage side MOSFET, there is a voltage difference, so some energy stored in the smoothing capacitor Cs4 Is transferred to the capacitor Cr34, and the energy charged in the capacitors Cr12 and Cr23 is transferred to the smoothing capacitors Cs2 and Cs3 through the following path.
Cs4⇒Mos4H⇒Lr34⇒Cr34⇒Mos3H
Cr23⇒Lr23⇒Mos3H⇒Cs3⇒Mos2H
Cr12⇒Lr12⇒Cr23⇒Lr23⇒Mos3H⇒Cs3⇒Cs2⇒Mos1H

Next, when Mos1L, Mos2L, Mos3L, and Mos4L, which are the low-voltage side MOSFETs of the circuits A1c to A4c, are turned on by the gate pulse 1l to the low-voltage side MOSFET, there is a voltage difference, so the energy charged in the capacitor Cr34 is smoothed. A part of the energy stored in the smoothing capacitors Cs1 and Cs2 is transferred to the capacitors Cs3 and Crs23 through the following path.
Cr34⇒Lr34⇒Mos4L⇒Cs3⇒Mos3L
Cs2⇒Mos3L⇒Lr23⇒Cr23⇒Mos2L
Cs1⇒Cs2⇒Mos3L⇒Lr23⇒Cr23⇒Lr12⇒Cr12⇒Mos1L

  Thus, in the step-down operation, energy is transferred from the smoothing capacitors Cs1, Cs2, and Cs4 to the smoothing capacitor Cs3 by charging and discharging the capacitors Cr12, Cr23, and Cr24. Then, the voltage V2 input between the voltage terminals VHh and VHl is converted to a voltage V1 that is stepped down by about 1/4 and output between the voltage terminals VL and Vcom.

As shown in FIGS. 13 and 14, the directions of the currents I12, I23, and I34 flowing through the LC series bodies LC12, LC23, and LC34 of the respective voltage stages are reversed between the boost operation and the buck operation. In any case, I12: I23: I34 = 1: 2: 1. In this case, the maximum current values are an effective value of 20 Arms for I12, an effective value of 40 Arms for I23, and an effective value of 20 Arms for I34.
As described above, the LC series body LC12 has one capacitor element and one inductor element arranged in parallel, the LC series body LC23 has two capacitor elements and two inductor elements arranged in parallel, and the LC series body LC34 has Each of the capacitor element and the inductor element is composed of one piece. That is, as in the first embodiment, the LC series bodies LC12, LC23, LC34 of each voltage stage are the minimum necessary to arrange capacitor elements and inductor elements in parallel according to the maximum current values of the flowing currents I12, I23, I34. The limited number is determined, and the closer to the low-voltage side voltage terminals VL and Vcom, the larger the capacitor capacity, the smaller the inductance, and the equal resonance period.

  For this reason, as in the first embodiment, the sizes of the capacitors and inductors constituting the LC series bodies LC12, LC23, and LC34 can be easily optimized, and a small and inexpensive device configuration can be realized. Moreover, since each LC serial body LC12, LC23, and LC34 is configured using the capacitor element and the inductor element having the same specifications, the component cost can be further reduced.

In the first embodiment, the low voltage side voltage terminals VL and Vcom are connected to both terminals of the smoothing capacitor Cs1, but in this embodiment, the smoothing of the circuit A3c located between the other circuits is performed. Connected to both terminals of the capacitor Cs3, the voltage V1 is input between the terminals of the smoothing capacitor Cs3. The current values flowing in the LC series bodies LC12, LC23, and LC34 in the first embodiment are I12r, I23r, and I34r, and the current values flowing in the LC series bodies LC12, LC23, and LC34 in this embodiment are I12, I23, and I34. Then
I12r: I23r: I34r = 3: 2: 1
I12: I23: I34 = 1: 2: 1
I12 = I34 = I34r
It becomes.
In this way, by connecting the low voltage side voltage terminals VL and Vcom serving as input / output voltage terminals to both terminals of the smoothing capacitor Cs3 of the circuit A3c located between the other circuits, the LC series circuit LC12 The current value I12 flowing through can be reduced to 1/3 compared to the case of the first embodiment. For this reason, the current ratings of the energy transfer inductor Lr and the capacitor Cr can be lowered, and the inductor Lr and the capacitor Cr can be reduced in size.

Also in this case, the gate pulse of the drive inverter circuit A3c may be longer during the step-up operation, and the gate pulse of the drive inverter circuit A4c may be longer than the gate pulse of the rectifier circuit during the step-down operation. Further, in the rectifier circuit, even if the gate signal passes a period t that is half the resonance period, the current flows backward if the voltage is high, so that the high voltage period does not exceed the period t that is 1/2 the resonance period. Thus, the reverse current is prevented by the parasitic diode of the MOSFET. Among the rectifier circuits A1c to A3c for step-down operation, the circuits A1c and A2c are also circuits for driving, but are regarded as rectifier circuits because they are circuits that prevent backflow by the parasitic diode of the MOSFET as described above. .
Further, as in the other embodiments, since the resonance periods of the LC series bodies LC12, LC23, and LC34 are equal, it is not necessary to change the gate signal of each rectifier circuit according to each resonance period, and it is easily effective. In addition, a highly efficient DC / DC power converter can be realized by utilizing the resonance phenomenon. Furthermore, the use of MOSFETs in the rectifier circuit can reduce conduction loss compared to diodes, further improving conversion efficiency.

  Also in this embodiment, the LC serial bodies LC12, LC23, and LC34 may be configured as shown in the second and third embodiments, and each has the same effect.

  In the eighth embodiment, the low voltage side voltage terminals VL and Vcom are connected to both terminals of the smoothing capacitor Cs3. However, the low voltage side voltage terminals VL and Vcom may be connected to both terminals of the smoothing capacitor Cs2. Similarly, the same effect as in the eighth embodiment can be obtained. Furthermore, even when the number of stages of the rectifier circuit is increased, the same effect can be obtained by connecting the low voltage side voltage terminals VL and Vcom to both terminals of the smoothing capacitor Cs of the circuit located in the middle between other circuits. can get.

Embodiment 9 FIG.
Next, a DC / DC power converter according to Embodiment 9 of the present invention will be described with reference to the drawings. FIG. 15 shows a circuit configuration of a DC / DC power conversion apparatus according to Embodiment 9 of the present invention.
In the ninth embodiment, a step-up DC / DC power converter that transfers energy from a voltage V1 between voltage terminals VL and Vcom to a voltage V2 between voltage terminals VHh and VHl will be described. Similar to the eighth embodiment, the voltage V2 is about four times the voltage V1, V1 is 50V, and V2 is about 200V.
As shown in FIG. 15, circuits A1d to A4d are used instead of the circuits A1c to A4c in the DC / DC power converter according to the eighth embodiment shown in FIG. 12, and the circuit A3d has the same configuration as the circuit A3c. In the circuits A1d, A2d, A4d, two MOSFETs (Mos1L, Mos1H) (Mos2L, Mos2H) (Mos4L, Mos4H) are replaced with diodes (Di1L, Di1H) (Di2L, Di2H) (Di4L, Di4H), respectively. That is, the driving inverter circuit A3d is configured by connecting two MOSFETs (Mos3L, Mos3H) as a low-voltage side switch and a high-voltage side switch in series and connecting between both terminals of the smoothing capacitor Cs3. The rectifier circuits A1d, A2d, and A4d are each connected between two terminals of each smoothing capacitor Cs1, Cs2, and Cs4 by connecting two diodes (Di1L, Di1H) (Di2L, Di2H) (Di4L, Di4H) in series. Composed. Accordingly, the gate drive circuit 113, the photocouplers 123H and 123L, the power supply Vs3, and the gate signals Gate3H and Gate3L for driving the MOSFET are deleted except for those for the MOSFETs (Mos3L and Mos3H). In this case, the control circuit 13c Outputs only gate signals Gate3H and Gate3L. Other configurations are the same as those in the eighth embodiment shown in FIG.

Next, the operation will be described.
The drive inverter circuit A3d sends the energy input between the voltage terminals VL-Vcom to the high voltage side by the on / off operation of the MOSFETs (Mos3L, Mos3H). The rectifier circuits A1d, A2d, A4d are driven inverter circuit A3d The current driven by is rectified and energy is transferred to the high voltage side.
FIG. 16 shows a gate signal Gate3H to the high-voltage side MOSFET, a gate signal Gate3L to the low-voltage side MOSFET, and currents I12, I23, and I34 flowing through the LC series bodies LC12, LC23, and LC34. As shown in FIG. 16, the gate signal Gate3H and the gate signal Gate3L are the gate signals Gate1H, Gate2H, Gate3H, Gate4H and the gate signals Gate1L, Gate2L, Gate3L, It is the same as Gate4L.
In the boosting operation of the eighth embodiment, since the current flowing through the MOSFET in the rectifier circuit flows in the diode in this embodiment, conduction loss occurs. Due to the same boosting operation, the currents I12, I23, I34 flowing through the LC series bodies LC12, LC23, LC34 are substantially the same as in the eighth embodiment.

Thus, as in the eighth embodiment, the LC series bodies LC12, LC23, LC34 of each voltage stage are arranged in parallel with the capacitor elements and the inductor elements according to the maximum current values of the flowing currents I12, I23, I34. The minimum required number is determined, and the closer to the low voltage side voltage terminals VL and Vcom, the larger the capacitor capacity and the smaller the inductance, and the equal resonance periods are set.
Therefore, similar to the eighth embodiment, the sizes of capacitors and inductors constituting each LC series body LC12, LC23, LC34 can be easily optimized, and a small and inexpensive apparatus configuration can be realized. Moreover, since each LC serial body LC12, LC23, and LC34 is configured using the capacitor element and the inductor element having the same specifications, the component cost can be further reduced.

  In addition, by connecting the low voltage side voltage terminals VL and Vcom to both terminals of the smoothing capacitor Cs3 of the circuit A3d located between the other circuits, the current value I12 flowing through the LC series body LC12 can be obtained as described above. Compared to the case of Form 1, it can be reduced to 1/3. For this reason, the current ratings of the energy transfer inductor Lr and the capacitor Cr can be reduced, and the inductor Lr and the capacitor Cr can be miniaturized.

Embodiment 10 FIG.
Next, a DC / DC power conversion apparatus according to Embodiment 10 of the present invention will be described with reference to the drawings. FIG. 17 shows a circuit configuration of a DC / DC power converter according to Embodiment 10 of the present invention.
In the tenth embodiment, a step-down DC / DC power converter that transfers energy from a voltage V2 between voltage terminals VHh and VHl to a voltage V1 between voltage terminals VL and Vcom is shown. Similar to the eighth embodiment, the voltage V2 is about four times the voltage V1, V1 is 50V, and V2 is about 200V.
In this embodiment, as shown in FIG. 17, circuits A1e to A4e are used in place of the circuits A1c to A4c in the DC / DC power converter according to the eighth embodiment shown in FIG. 12, and the circuits A1e, A2e, A4e has the same configuration as the circuits A1c, A2c, A4c, and the circuit A3e has two MOSFETs (Mos3L, Mos3H) replaced with diodes (Di3L, Di3H), respectively. In other words, the drive inverter circuit A4e and the rectifier circuits A1e, A2e are configured by connecting two MOSFETs in series as low-voltage side switches and high-voltage side switches and connecting them between both terminals of the smoothing capacitors Cs4, Cs1, Cs2. Is done. The rectifier circuit A3e is configured by connecting two diodes (Di3L, Di3H) in series and connecting between both terminals of the smoothing capacitor Cs3. Accordingly, the gate drive circuit 113, the photocouplers 123H and 123L, the power supply Vs3, and the gate signals Gate3H and Gate3L for driving the MOSFET in the circuit A3c in the eighth embodiment are deleted. In this case, the gate signal is output from the control circuit. Only Gate1H, Gate2H, Gate4H, Gate1L, Gate2L, Gate4L are output. Other configurations are the same as those in the eighth embodiment shown in FIG.

  In the step-down operation of the eighth embodiment, since the current flowing through the MOSFET in the rectifier circuit A3c flows through the diode in the rectifier circuit A3e in this embodiment, conduction loss occurs. The currents I12, I23, and I34 flowing through the LC series bodies LC12, LC23, and LC34 by the step-down operation similar to that in the eighth embodiment are substantially the same as those in the eighth embodiment.

Thus, as in the eighth embodiment, the LC series bodies LC12, LC23, LC34 of each voltage stage are arranged in parallel with the capacitor elements and the inductor elements according to the maximum current values of the flowing currents I12, I23, I34. The minimum required number is determined, and the closer to the low voltage side voltage terminals VL and Vcom, the larger the capacitor capacity and the smaller the inductance, and the equal resonance periods are set.
Therefore, similar to the eighth embodiment, the sizes of capacitors and inductors constituting each LC series body LC12, LC23, LC34 can be easily optimized, and a small and inexpensive apparatus configuration can be realized. Moreover, since each LC serial body LC12, LC23, and LC34 is configured using the capacitor element and the inductor element having the same specifications, the component cost can be further reduced.

  In addition, by connecting the low voltage side voltage terminals VL and Vcom to both terminals of the smoothing capacitor Cs3 of the circuit A3e located between the other circuits, the current value I12 flowing through the LC series body LC12 can be calculated as described above. Compared to the case of Form 1, it can be reduced to 1/3. For this reason, the current ratings of the energy transfer inductor Lr and the capacitor Cr can be reduced, and the inductor Lr and the capacitor Cr can be miniaturized.

  In the ninth and tenth embodiments, the LC serial bodies LC12, LC23, and LC34 may be configured as shown in the second and third embodiments, and each has the same effect.

In each of the above embodiments, the power MOSFET in which the parasitic diode is formed between the source and the drain is used as the switching element in the driving inverter circuit and the rectifier circuit. However, the control electrode such as IGBT can be turned on and off. Other semiconductor switching elements that can be controlled may be used, in which case a diode connected in antiparallel is used, and this diode functions as a parasitic diode of the power MOSFET. Thereby, the same effect is acquired by the control similar to said each embodiment.
In addition, it goes without saying that the above embodiments can be applied to DC / DC power converters having various voltage ratios in which the number of stages of the rectifier circuit is changed.

Embodiment 11 FIG.
In the plurality of circuits constituting the DC / DC power conversion device according to each of the above embodiments, the power supply Vsk (Vs0 to Vs4) provided for driving the MOSFET, gate drive circuit, photocoupler, etc. in the circuit is as follows: Explained.
FIG. 18 is a diagram illustrating a circuit configuration of the power supply Vsk. The power source Vsk of each circuit, for example, the circuits A1 to A4 of the first embodiment, uses the voltage generated in the smoothing capacitors Cs (k) (Cs1 to Cs4) in each circuit as the input voltage Vsi (k) and the output terminal Vsh ( An output voltage Vso (k) is generated between k) and Com (k).
The reference voltage of the voltages Vso (k) and Vsi (k) is Com (k). The high voltage side terminal of the smoothing capacitor Cs (k) is connected to the source terminal of the p-type MOSFET M2, and the drain terminal of the MOSFET M2 is connected to the cathode terminal of the diode D1 and one terminal of the choke coil L1. The anode terminal of the diode D1 is connected to the reference voltage Com (k), the other terminal of the choke coil L1 is connected to one terminal of the capacitor C2, and the other terminal of the capacitor C2 is connected to the reference voltage Com (k). ing. The capacitor Cs (k), the capacitor C2, the MOSFET M2, the diode D1, and the choke coil L1 constitute a non-insulated step-down DC / DC converter 10, and the input voltage Vsi (k) is output voltage via the DC / DC converter 10. Converted to Vso (k).

Capacitor C1, capacitor C2, and zener diode Z1 are connected in parallel, the anode terminal side of zener diode Z1 is connected to reference voltage Com (k), and the cathode terminal side of zener diode Z1 is connected to the terminal of choke coil L1. ing. An output voltage Vso (k) is generated in the parallel body of C1, C2, and Z1. The voltage Vso (k) is supplied to the clock generation circuit d1, the error amplification circuit d2, and the comparator circuit d3, and the circuits d1 to d3 operate. The supply of the voltage Vso (k) to the error amplifier circuit d2 and the comparator circuit d3 is not shown.
The output of the clock generation circuit d1 is input to one of the inputs of the comparator circuit d3 through a sawtooth wave forming unit constituted by a resistor R3 and a capacitor C3. The target voltage composed of the resistor R2 and the Zener diode Z2 is input to one of the inputs of the error amplifier circuit d2, and the measured voltage of Vso (k) is divided by the resistors R3 and R4 to the other input. Have been entered. The output of the error amplifier circuit d2 is input to the other input of the comparator circuit d3, and its connection point is connected to the connection point of the resistors R5 and R6. The other terminal of the resistor R5 is connected to the output terminal Vsh (k) of the voltage Vso (k), and the other terminal of the resistor R6 is connected to the reference voltage Com (k).
The output terminal of the comparator circuit d3 is connected to the gate terminal of the n-type MOSFET M1, the source terminal of the MOSFET M1 is connected to the reference voltage Com (k), and the drain terminal is connected to one terminal of the resistor R7. The other terminal of the resistor R7 is connected to the gate terminal of the MOSFET M2 and one terminal of the resistor R8. The other terminal of the resistor R8 is connected to the source terminal of the MOSFET M2.

The operation of the power supply Vsk configured as described above will be described. In the step-down operation, since the energy source is connected between VH and Vcom, a voltage is generated in the smoothing capacitor Cs (k) and the power supply Vsk operates.
On the other hand, in the step-up operation, an energy source is connected between VL and Vcom and a voltage is generated in the smoothing capacitor Cs1, but the other smoothing capacitors Cs (k) are in a state where no voltage is generated at the start of operation. is there. However, when the power supply Vs1 operates with the voltage of the smoothing capacitor Cs1 and the MOSFET in the circuit A1 is turned on and off, the parasitic diodes of the MOSFETs in the circuits A2 to A4 operate, and energy is transferred to the smoothing capacitors Cs2, Cs3, and Cs4. Transition. Although the power conversion efficiency of the operation using this parasitic diode is not good, it takes less than 1 second for energy to transfer to each smoothing capacitor Cs (k). Thus, a voltage is generated in each smoothing capacitor Cs (k), and each power supply Vsk operates.

Details of the operation will be described. When a voltage is formed in the smoothing capacitor Cs (k), the capacitors C1 and C2 are charged through the resistor R1. The voltage is the Zener voltage of the Zener diode Z1, which is 16V here. By supplying this voltage, an output voltage Vso (k) is generated in the parallel body of C1, C2, and Z1, and is supplied to the clock generation circuit d1, the error amplification circuit d2, and the comparator circuit d3, and the circuits d1 to d3 operate. At the same time, the power supply Vsk operates.
Since the resistor R1 has a relatively large resistance value in order to suppress power loss, energy supply via the resistor R1 before the operation of the power supply Vsk is not sufficient to operate the MOSFETs in each circuit. When the power supply Vsk starts to operate, the non-insulated DC / DC converter 10 operates and is converted from the voltage Vsi (k) to the voltage Vso (k) via the DC / DC converter 10. Enough to operate the MOSFETs in the circuit.

  FIG. 19 shows the voltage Da at the input terminal on the error amplifier circuit d2 side of the comparator circuit d3, the voltage Db at the input terminal on the clock generation circuit d1 side, the voltage Dc at the output terminal, and the gate voltage Dd of the MOSFET M2. The error amplifier circuit d2 outputs a voltage Da such that the voltage between the two input terminals becomes zero. That is, the voltage Da is determined so that the output voltage Vso (k) (15V) becomes the target voltage (15V) determined by the Zener diode Z2. The voltage Db is a sawtooth voltage, and is formed by passing a rectangular wave voltage from the clock generation circuit d1 through a CR circuit. The voltages Da and Db are compared by the comparator circuit d3 to form a rectangular wave voltage Dc. For example, when the output voltage Vso (k) is suppressed, the voltage Da is lowered, and as a result, the high voltage period of the rectangular wave voltage Dc is shortened. The MOSFET M1 is turned on and off by the rectangular wave voltage Dc, and the voltage at the gate terminal of the MOSFET M2 changes to low and high with reference to the voltage at the source terminal of the MOSFET M1. Since the MOSFET M2 is a p-type MOSFET, it operates on when low and off when high. The voltage between the gate and source of the MOSFET M2 is within the maximum rating due to the voltage division between the resistors R7 and R8. As described above, the MOSFET M2 is turned on and off by controlling the on-time, thereby transferring energy from the smoothing capacitor Cs (k), and the voltage Vso (k) between the output terminals Com (k) and Vsh (k) is predetermined. The voltage is controlled to be 15V.

  In this embodiment, power is supplied from a smoothing capacitor Cs (k) in each circuit via a non-insulated DC / DC converter 10 to a power source Vsk that drives each circuit constituting the DC / DC power converter. It was configured as follows. For this reason, wiring between the input voltage unit and each power source Vsk, a connector therefor, and the like are unnecessary, and it is not necessary to insulate each power source using a transformer, and the power source configuration is small and has high conversion efficiency. Thereby, high efficiency and miniaturization of the DC / DC power converter can be achieved.

  In the above embodiment, the DC / DC converter 10 has a step-down circuit configuration assuming that the input voltage Vsi (k) is 20 V or higher. However, the input voltage Vsi (k) is low, for example, 10 V or lower. In this case, a step-up DC / DC converter 10 is used.

  In the above embodiment, the reference voltage of the power source Vsk that drives each circuit of the DC / DC power converter is Com (k), and the control unit such as the gate drive circuit in each circuit is the reference voltage Com (k). However, the control unit such as the gate drive circuit in each circuit may be configured with the voltage reference of the voltage terminal Vcom, and the MOSFET M2 may be driven based on the voltage Vcom with the reference voltage of the power supply Vsk as Vcom. Although the routing is somewhat complicated, the power supply configuration has good conversion efficiency.

It is a figure which shows the main circuit of the DC / DC power converter device by Embodiment 1 of this invention. It is a figure which shows the control circuit of the DC / DC power converter device by Embodiment 1 of this invention. It is a figure which shows the gate signal at the time of the pressure | voltage rise operation by Embodiment 1 of this invention, and the current waveform of each part. It is a figure which shows the gate signal at the time of the pressure | voltage fall operation by Embodiment 1 of this invention, and the current waveform of each part. It is a figure which shows the circuit structure of the DC / DC power converter device by Embodiment 4 of this invention. It is a figure which shows the gate signal at the time of the pressure | voltage rise operation by Embodiment 4 of this invention, and the current waveform of each part. It is a figure which shows the main circuit of the DC / DC power converter device by Embodiment 5 of this invention. It is a figure which shows the main circuit of the DC / DC power converter device by Embodiment 6 of this invention. It is a figure which shows the control circuit of the DC / DC power converter device by Embodiment 6 of this invention. It is a figure which shows the gate signal at the time of the pressure | voltage rise operation by Embodiment 6 of this invention, and the current waveform of each part. It is a partial circuit diagram of the DC / DC power converter device by Embodiment 7 of this invention. It is a figure which shows the main circuit of the DC / DC power converter device by Embodiment 8 of this invention. It is a figure which shows the gate signal at the time of the pressure | voltage rise operation by Embodiment 8 of this invention, and the current waveform of each part. It is a figure which shows the gate signal at the time of the pressure | voltage fall operation by Embodiment 8 of this invention, and the current waveform of each part. It is a figure which shows the circuit structure of the DC / DC power converter device by Embodiment 9 of this invention. It is a figure which shows the gate signal at the time of the pressure | voltage rise operation by Embodiment 9 of this invention, and the current waveform of each part. It is a figure which shows the main circuit of the DC / DC power converter device by Embodiment 10 of this invention. It is a figure which shows the structure of the power supply Vsk of each circuit by Embodiment 11 of this invention. It is a figure which shows the voltage waveform of each part of the power supply Vsk by Embodiment 11 of this invention.

Explanation of symbols

1a to 1l gate pulse, 10 DC / DC converter, 13, 13a to 13c control circuit,
A1-A4 circuit (drive inverter circuit / rectifier circuit),
A1a ~ A4a circuit (drive inverter circuit / rectifier circuit),
A1b to A4b circuit (drive inverter circuit / rectifier circuit),
A1c ~ A1c circuit (drive inverter circuit / rectifier circuit),
A1d to A1d circuit (drive inverter circuit / rectifier circuit),
A1e to A1e circuit (drive inverter circuit / rectifier circuit),
B0-B4 circuit (drive inverter circuit / rectifier circuit),
B0a circuit (drive inverter circuit / rectifier circuit),
Cs0 to Cs4 smoothing capacitor, Di1L to Di4L, Di1H to Di4H diode,
Mos1L to Mos4L, Mos1H to Mos4H, Mos0AL, Mos0BL, Mos0AH, Mos0BH MOSFET,
Cr01, Cr12, Cr23, Cr34 capacitors,
Cr01A to Cr01D, Cr12A to Cr12C, Cr23A, Cr23B, Cr34A capacitor elements,
Lr01, Lr12, Lr23, Lr34 inductors,
Lr01A to Lr01D, Lr12A to Lr12C, Lr23A, Lr23B, Lr34A inductor elements,
LC01, LC12, LC23, LC34 LC series body, Tr transformer,
Gate1L to Gate4L, Gate1H to Gate4H Gate signal,
Gate0AL, Gate0BL, Gate0AH, Gate0BH Gate signal, t Resonance period / 2,
Vs0 to Vs4, Vsk power supply, VL, Vcom low voltage side voltage pin, VL, Vcom0 low voltage side voltage pin,
VH, Vcom High voltage side voltage terminal, VHh, VHl High voltage side voltage terminal.

Claims (12)

Three or more circuits composed of a plurality of semiconductor switching elements and smoothing capacitors whose ON / OFF operations are controlled by the control electrode are connected in a line by arranging a series body of capacitors and inductors between adjacent circuits. A low voltage side voltage terminal and a high voltage side voltage terminal to be terminals are respectively connected to the terminals of the predetermined smoothing capacitor,
In the plurality of series bodies, the closer to the low voltage side voltage terminal, the larger the capacitor capacity and the smaller the inductance, and the resonance periods determined by the capacitor capacity and the inductance are set to be equal, respectively.
The DC circuit is characterized in that DC / DC conversion is performed by charging / discharging each of the series capacitors using a predetermined circuit among the plurality of circuits as a drive inverter circuit and another circuit as a rectifier circuit. / DC power converter. Each of the circuits is a circuit in which a high-voltage side switch and a low-voltage side switch that are the plurality of semiconductor switching elements are connected in series and connected between positive and negative terminals of the smoothing capacitor, the plurality of circuits are connected in series, 2. The DC circuit according to claim 1, wherein the series body is connected between intermediate terminals of adjacent circuits, with a connection point between the high-voltage side switch and the low-voltage side switch in each circuit as an intermediate terminal. / DC power converter. According to a circuit in which two semiconductor switching elements whose on / off operations are controlled by a control electrode are connected in series between the positive and negative terminals of the smoothing capacitor, and a circuit in which two diode elements are connected in series between the positive and negative terminals of the smoothing capacitor Three or more circuits are connected in a row by arranging a series of capacitors and inductors between adjacent circuits, respectively, and the low voltage side voltage terminal and the high voltage side voltage terminal, which are input / output voltage terminals, are respectively set to the predetermined smoothing Prepare to connect to the capacitor terminal,
In the plurality of series bodies, the closer to the low voltage side voltage terminal, the larger the capacitor capacity and the smaller the inductance, and the resonance periods determined by the capacitor capacity and the inductance are set to be equal, respectively.
Among the plurality of circuits, a predetermined circuit composed of the two series semiconductor switching elements is used as a drive inverter circuit, and another circuit is used as a rectifier circuit. DC / DC power converter characterized by performing. 4. The DC / DC power converter according to claim 3, wherein the series body is connected between the intermediate terminals of adjacent circuits, with the connection point of the two series elements in each circuit as an intermediate terminal. Comprising a transformer, wherein the plurality of circuits are composed of a first circuit connected to a primary winding of the transformer and a second circuit connected to a secondary winding of the transformer, and the series body is 4. The DC / DC power converter according to claim 1, wherein the DC / DC power converter is connected in series to the primary winding or the secondary winding. The low voltage side voltage terminal is connected to the positive and negative terminals of a smoothing capacitor of a predetermined circuit in the plurality of circuits, and both sides of the predetermined circuit are connected to other circuits in the plurality of circuits in the middle. The DC / DC power converter according to claim 1, wherein the DC / DC power converter is located. 7. The DC / DC according to claim 1, wherein each of the semiconductor switching elements is a power MOSFET having a parasitic diode between a source and a drain, or a semiconductor switching element in which diodes are connected in antiparallel. DC power converter. In the rectifier circuit configured by the semiconductor switching element, an on period of the semiconductor switching element in the rectifier circuit does not exceed a half period of a resonance period of the series body. The DC / DC power converter according to claim 7. 9. The DC / DC power converter according to claim 1, wherein a capacitor capacity and an inductance of each series body are determined according to a maximum current value flowing through each series body. The capacitor of each series body is configured by arranging one or a plurality of capacitor elements having the same specifications in parallel, and the inductor is configured by arranging one or a plurality of inductor elements having the same specifications in parallel, The DC / DC power converter according to any one of claims 1 to 8, wherein the number of the capacitor elements and the inductor elements arranged in parallel increases as the voltage terminal is closer to the low voltage side voltage terminal. 11. The DC / DC power conversion according to claim 10, wherein the number of the capacitor elements and the inductor elements of each series body arranged in parallel is determined according to the maximum current value flowing through each series body. apparatus. Each circuit composed of the semiconductor switching element includes a power source for operating the circuit, and the power source is supplied with power from a smoothing capacitor in each circuit via a DC / DC converter. The DC / DC power converter according to any one of claims 1 to 11.

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