JP2008041059A - Multiprocessor controller and information processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a controller which intermediates a reset operation between processors of an information processor comprised of multiprocessors. <P>SOLUTION: This processor controller has: first mask setting means in which whether or not to mask reset release instructions for instructing starting of processors also from other processors during reset of the processors; first default setting means for setting any one of the first mask setting means so as not to mask the reset release instructions when the whole device is in a reset state; second mask setting means in which whether or not to mask a reset instruction for instructing reset of peripheral devices are set from other processors and a processor controller which resets the peripheral devices to reset instructions from the respective processors based on results after being masked by the second mask setting means. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a multiprocessor control device, and more particularly to reset control of a processor and peripheral devices.

  In recent home appliances and the like, multimedia processing has progressed, and higher processing power has been demanded. In order to compensate for this with the current manufacturing technology, an information processing apparatus in which a plurality of (multi) processors are mounted in one apparatus has been proposed.

  However, there are many issues to consider such as arbitration between processors when handling peripheral devices.

For example, a method for controlling the startup of a slave processor by appropriately replacing boot program code to be read has been proposed (see Patent Document 1).
JP-A-8-161283

  By using a multiprocessor as the information processing apparatus, it is possible to increase the processing capability while using the current processor.

However, for example, when resetting the information processing apparatus, if a plurality of processors reset and reset peripheral devices at their own timing, normal operation is not performed as a whole.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a control device that arbitrates a reset operation between processors of an information processing device configured by a multiprocessor.

  The processor control device according to the present invention is a device for controlling a plurality of processors sharing a peripheral device, provided for each processor, and masking a reset release instruction for instructing activation of the processor during reset. A first mask setting means capable of setting whether or not to perform from another processor, and when the entire apparatus is in a reset state, any one of the first mask setting means is provided. First initialization means for setting so as not to mask, and provided for each processor, whether or not the processor masks a reset instruction for instructing reset of the peripheral device can also be set from other processors Second mask setting means and all the second mask setting means not to mask when the entire apparatus is in a reset state. Second initial setting means, and peripheral device reset means for generating a reset instruction instructing the peripheral device based on a reset instruction instructed by each processor and masked by the second mask setting means A processor control device is provided.

  Further, according to the information processing apparatus of the present invention, a plurality of processors, peripheral devices shared by the processors, and a processor are provided for each processor. The first mask setting means that can also be set by other processors and whether the mask setting means is masked when one of the first mask setting means is in the reset state. A first initial setting means for setting the processor and each processor, and whether the processor masks a reset instruction for instructing the reset of the peripheral device can be set from another processor. 2 mask setting means and a second initial setting for setting all the second mask setting means not to mask when the whole is in a reset state And a peripheral device reset means for generating a reset instruction for instructing the peripheral device based on the reset instruction after being masked by the second mask setting means, which is instructed by each processor. An information processing apparatus is provided.

  ADVANTAGE OF THE INVENTION According to this invention, the information processing apparatus of a multiprocessor structure is realizable by providing the control apparatus which arbitrates the reset operation between the processors of the information processing apparatus comprised by the multiprocessor.

  FIG. 1 is a diagram illustrating an example of a block diagram of the information processing apparatus according to the present embodiment. In FIG. 1, an information processing apparatus 100, a CPU 0101, a CPU 1102, a boot address conversion unit 103, an internal bus 104, a peripheral device unit 105, a CPU reset unit 106, a peripheral device reset unit 107, and a debugger 108 are shown.

  The information processing apparatus 100 corresponds to, for example, a home appliance such as a personal computer (PC), a television, or a video. A plurality of CPUs (Central Processing Units) are incorporated, and a predetermined process is realized by executing a program code (not shown) described in advance.

  The CPU 0101 and the CPU 1102 are CPUs built in the information processing apparatus 100 and control the information processing apparatus 100 according to the program code. The CPU 0101 and CPU 1102 of this embodiment have equivalent interfaces as configurations, and both can be master processors in the information processing apparatus 100. At this time, the other CPU which has become the master processor becomes a slave processor.

  The boot address conversion unit 103 has a function that is provided separately for each of the CPU 0101 and the CPU 1102 and converts an address at which the CPU tries to read a program code (boot code) when each CPU is booted. Usually, the CPU is configured to automatically read out the program code stored at a predetermined address (boot address) on the memory immediately after resetting and execute the startup process. A user of this CPU can perform a desired operation by assigning a boot code describing a process to be performed by the CPU at the time of resetting to the boot address. The boot address conversion unit 103 of this embodiment is used when it is desired to process different boot codes for each of a plurality of CPUs.

  The internal bus 104 is a bus that realizes communication between the CPU 0101 or the CPU 1102 and the component modules in the information processing apparatus 100.

  The peripheral device unit 105 corresponds to a storage device such as a magnetic disk device (HDD) or a memory, and an input / output device such as a display, a keyboard, or a mouse. These devices are assumed to be reset to an initial state when a reset is input. When the initial state is obtained after resetting, the CPU can be brought into a desired use state only after negotiation and setting for use are performed again by the CPU. When the whole or a part of the information processing apparatus 100 is realized by LSI (Large Scale Integration), a CPU built in a control circuit or the like of the external apparatus 105 performs this.

  The CPU reset unit 106 has a function of selectively or simultaneously resetting the CPU 0101 and the CPU 1102.

  The peripheral device reset unit 107 has a function of resetting the peripheral device unit 105 based on a reset input from the outside or the CPU.

  The debugger 108 is a device for supporting verification during operation verification (debugging) of the information processing apparatus 100. This is not necessary in the normal use state of the information processing apparatus 100. The debugger 108 has a function of giving a predetermined instruction to the CPU 0101 and CPU 1102 during debugging.

  FIG. 2 is a diagram illustrating an example of a circuit diagram of the CPU reset unit 106 according to the present embodiment. In FIG. 2, a CPU0 reset signal and a CPU1 reset signal are generated from a master CPU selection input and a CPU reset input. Here, the reset of CPU0 and CPU1 is based on the premise that the “L” signal is asserted and the “H” signal is negated. That is, when the reset input is changed from “H” to “L”, the reset is reset, and thereafter, this input is changed to “H” to release the reset state and start a predetermined start-up operation.

In the figure, an FF 200 is a flip-flop that has a reset input that presets an output according to an input, and that can set output values from a plurality of CPUs such as a CPU 0101 and a CPU 1102. To set the output value from the CPU, connect the signal line of the CPU whose output value changes by using a dedicated instruction, or assign a specific address on the internal bus 104, and access the assigned address A method of setting a value using as a trigger is conceivable. The AND gate 201 shows a circuit in which the output becomes “H” only when both inputs are “H”. NOT gate 202 exhibits input inversion, which functions to invert the input signal.

  Details of the operation will be described below.

    The master CPU selection input is an input for instructing which of CPU 0101 and CPU 1102 is the master processor. Since this input is input to two FFs 200, one of them is transmitted via the NOT gate 202. For example, if this input is "H", the CPU 0101 is the master processor, and if this input is "L", the CPU 1102 is the master processor. Can be selectively functioning to indicate that

  Consider the case where the master CPU selection input is "H" and the CPU reset input is "H" (negate). Considering the CPU0 reset side, since “H” is input to the FF 200, “H” is output to the AND gate 201. Since the inputs of the AND gate 201 are “H” and “H”, respectively, “H” is output. In this case, CPU0 reset is negated. On the other hand, the CPU1 reset side becomes “L” and is asserted.

  At this time, if the CPU reset input is dropped from "H" to "L" (asserted) to reset the CPU, the value output from the FF 200 is reset to a value based on the master CPU selection input. Even in this case, regardless of the value output by the FF 200, the CPU0 reset is maintained from "H" to "L", and the CPU1 reset is maintained at "L". After a while, when the CPU reset input changes from "L" to "H" (Negate), CPU0 reset changes from "L" to "H" (Negate), but the FF200 on the CPU1 side is "L". Reset can be left "L" (asserted).

  When the value of the master CPU selection input is “L”, the transition of the CPU0 reset and CPU1 reset signal transitions.

  When the CPU reset input is negated, the CPU on which the CPU reset input is negated is the master processor, and the master processor rewrites the output value of the FF 200 corresponding to the CPU on the slave processor side to “H” at an appropriate timing. The master processor can freely control the startup timing of the slave processor.

With this configuration, the master processor can mask the startup of the slave processor until an arbitrary time.

  FIG. 3 is a diagram illustrating an example of a circuit diagram of the peripheral device reset unit 107 according to the present embodiment. FIG. 3 shows an FF 300, an OR gate 301, and an AND gate 302.

  The FF 300 is a flip-flop (Flip-Flop) that can set an output value from a plurality of CPUs such as the CPU 0101 and the CPU 1102 and has a reset input that presets an output according to the input, as in the previous FF 200. Here, different output values can be set for the FF 300 on the CPU0 side and the FF300 on the CPU1 side. The OR gate 301 is a circuit that outputs “H” when either input becomes “H”. The AND gate 302 shows a circuit in which the output becomes “H” only when all the inputs are “H”.

  Consider the case where both the CPU reset input and cold reset input are "H" (negate). At this time, it is assumed that the initial value of FF300 is “L” and the signals from CPU0 and CPU1 are “H” (negate).

  Since the output of the FF 300 is “L” and the signal from the CPU 0 or CPU 1 is “H”, the OR gate 301 becomes “H”. Therefore, since all inputs of the AND 302 are “H”, the peripheral device unit reset is “H” (negate).

  When the CPU reset input falls from “H” to “L” (asserted), one input of the AND gate 302 becomes “L”, so the peripheral device reset is “L”, that is, the peripheral device 105 is asserted. It becomes a state. When the CPU reset input changes from “L” to “H” (negate) after a while, the peripheral device unit 105 starts up in an initial state.

  The signals entered from the CPU 0 and CPU 1 into the OR gate 301 are signals that enable each CPU to reset the peripheral device unit 105 by changing this signal from “H” to “L” (asserted). . At this time, if the output of the FF 300 is set to “H”, the output of the OR gate 301 maintains “H” (negate) even if the reset of the peripheral device unit 105 is asserted by the CPU to which the FF 300 is assigned. Therefore, a reset instruction from a predetermined CPU can be masked from another CPU.

  When the cold reset input changes from “H” to “L” (asserted), the FF 300 is reset to output the initial value “L” regardless of the set value, and the mask state is released.

  With this configuration, it is possible to instruct or mask-control the reset of the peripheral device unit 105 shared by each CPU for each CPU.

  FIG. 4 is a diagram illustrating an example of a block diagram of the boot address conversion unit 103 according to the present embodiment. The boot address conversion unit 103 is provided for each CPU. Since other CPUs have the same configuration, only the boot address conversion unit 103 assigned to the CPU 0101 is described in FIG. A comparator 400, a boot address conversion information setting register 401, a converter 402, and a multiplexer 403 are shown.

  The comparator 400 has a function of receiving address information output for the CPU 0101 to access the peripheral device unit 105 and comparing whether or not the address is included in the boot address area. The boot address here may be determined as a boot address area over a certain size (for example, 4 MB).

  The boot address conversion information setting register 401 is a register that holds information for converting the original boot address set in the design of the CPU. The initial value is set so that the converted address is the same as the original address. The initial value here varies depending on the method of address conversion, but for example, the same bit string as the corresponding bit of the original boot address or a value in which all bits are zero can be considered. This register can be freely set by each CPU including registers assigned to other CPUs.

  The converter 402 has a function of converting the address output from the CPU 0101 based on the address information held in the boot address conversion information setting register 401. As a method of address conversion, for example, a method of replacing a part of the upper bits of the address with address information held in a register, a method of adding the value of the address information, or the like can be considered.

  The multiplexer 403 has a function of selecting either address information output from the CPU 0 or address information output from the converter 402 in accordance with a signal from the comparator 400 and sending it to the address bus. This selection of address information is configured to select a value output from the converter 402 when the comparator 400 determines that it is a boot address, and to select address information output from the CPU 0 in other cases. .

  At the initial stage of starting the information processing apparatus 100, the boot address conversion information setting register 401 is reset to an initial value, and the address information output from each CPU is sent to the address bus as it is.

At this time, only the CPU designated as the master processor by the CPU reset unit 106 is started, and when the boot address conversion information setting register 401 assigned to the CPU to be the other slave processor is converted by the converter 402, the CPU 402 converts the address. The value is set so as to be the address where the desired boot code is placed. After that, the CPU reset unit 106 sets the FF 200 so that the FF 200 assigned to the CPU to be the slave processor becomes “H”. Then, the CPU which becomes the slave processor can be started up with the program code desired by the master processor as the boot code.

  With this configuration, the master processor can arbitrarily set the boot address of the slave processor, and can start up the slave processor with different boot codes.

  FIG. 5 is a diagram illustrating an example of the timing of the CPU reset signal according to the present embodiment.

CPU reset input, CPU0 reset input, and CPU1 reset input are shown in time series.

  Here, the CPU0 reset input is a reset signal input from the CPU0101 shown in FIG. 3, and the CPU1 reset input is a reset signal similarly input from the CPU1102. These signals input from the CPU are, for example, a peripheral device unit 105 based on the logical product of a reset signal instructing the debugger 108 to reset the CPU for debugging and the reset signal of the CPU input from the CPU reset unit 106. The case where the reset of the control is controlled is considered.

  First, at the same time as the CPU reset input changes from the assert ("L") state to the negate ("H") state, the reset input of the CPU 0101 designated as the master processor is negated. The CPU 0101 whose reset input is negated executes its own start-up process. After that, the boot address conversion information setting register 401 assigned to the CPU 1102 is set to a desired value and the mask of the CPU 1102 is released. This release process is performed by setting the output of the FF 200 assigned to the CPU 1102 of the CPU reset unit 106 to be “H”.

  By providing reset arbitration and boot address conversion functions as in this embodiment, it is possible to realize an information processing apparatus that can share a memory space or peripheral device section among multiple processors even if the processor boot address is fixed. It becomes.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

It is a figure which shows an example of the block diagram of the information processing apparatus concerning this embodiment. It is a figure which shows an example of the circuit diagram of the CPU reset part concerning this embodiment. It is a figure which shows an example of the circuit diagram of the peripheral device reset part concerning this embodiment. It is a figure which shows an example of the block diagram of the boot address conversion part concerning this embodiment. It is a figure which shows an example of the timing of the CPU reset signal concerning this embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Information processing apparatus, 101 ... CPU0, 102 ... CPU1, 103 ... Boot address conversion part, 104 ... Internal bus, 105 ... Peripheral device part, 106 ... CPU reset 107, peripheral device reset unit 108, debugger, 200 ... FF, 201 ... AND gate, 202 ... NOT gate, 300 ... FF, 301 ... OR gate, 302 ... AND gate, 400 ... Comparator, 401 ... Boot address conversion information setting register, 402 ... Converter, 403 ... Multiplexer

Claims (8)

A device for controlling a plurality of processors sharing a peripheral device,
A first mask setting means provided for each processor and capable of setting from another processor whether or not to mask a reset release instruction for instructing activation during reset of the processor;
First initial setting means for setting any one of the first mask setting means so as not to be masked when the entire apparatus is in a reset state;
A second mask setting means provided for each processor, wherein the processor can set whether or not to mask a reset instruction for instructing reset of the peripheral device, from another processor;
A second initial setting means for setting all the second mask setting means so as not to mask when the entire apparatus is in a reset state;
Peripheral device reset means for generating a reset instruction for instructing the peripheral device based on a reset instruction after being masked by the second mask setting means, instructed by each processor. Control device.   The processor whose reset release instruction is not masked by the first mask setting means is set not to mask at least one of the first mask setting means set to mask the reset release instruction after startup. The processor control device according to claim 1, wherein: Address information setting means provided for each processor and capable of setting address information from other processors;
Address conversion means for converting an address from which the processor reads the program code using address information set in the address information setting means provided for each processor;
It is determined whether or not the address information sent by the processor corresponds to a boot address area in which a boot code that is read at the time of restart after resetting is stored. If the address information is included in the boot address area, the address conversion means converts it. A multiplexer provided for each processor for selecting address information, otherwise the address information is sent as address information sent by the processor and sent to an address bus;
The processor control device according to claim 1, further comprising:   The address information setting means sets a value in advance so that the address conversion means sets the address information after the conversion to be the same as the address information sent by the processor until the address information is set by any processor. The processor control device according to claim 3, wherein the processor control device is characterized in that: Multiple processors,
Peripheral devices shared by the processor;
A first mask setting means provided for each processor and capable of setting from another processor whether or not to mask a reset release instruction for instructing activation during reset of the processor;
A first initial setting means for setting any one of the first mask setting means so as not to be masked when the entirety is in a reset state;
A second mask setting means provided for each processor, wherein the processor can set whether or not to mask a reset instruction for instructing reset of the peripheral device, from another processor;
Second initial setting means for setting all the second mask setting means so as not to mask when the whole is in a reset state;
Peripheral device reset means for generating a reset instruction for instructing the peripheral device based on a reset instruction after being masked by the second mask setting means, instructed by each processor Processing equipment.   A processor whose reset release instruction has not been masked by the first mask setting means has at least one of the first mask setting means set to mask the reset release instruction after the processor is restarted. 6. The information processing apparatus according to claim 5, wherein the information processing apparatus is set so as not to be masked. Address information setting means provided for each processor and capable of setting address information from other processors;
Address conversion means for converting an address from which the processor reads the program code using address information set in the address information setting means provided for each processor;
It is determined whether or not the address information sent by the processor corresponds to a boot address area in which a boot code that is read at the time of restart after resetting is stored. If the address information is included in the boot address area, the address conversion means converts it. A multiplexer provided for each processor for selecting address information, otherwise the address information is sent as address information sent by the processor and sent to an address bus;
The information processing apparatus according to claim 5, further comprising: The address information setting means sets a value in advance so that the address conversion means sets the address information after the conversion to be the same as the address information sent by the processor until the address information is set by any processor. The information processing apparatus according to claim 7, wherein the information processing apparatus is characterized.

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