JP2007251603A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To precisely remove noise mixed into an input signal in a semiconductor integrated circuit to which the input signal such as a reset signal is input asynchronously with a clock signal from the outside. <P>SOLUTION: The semiconductor integrated circuit is provided with a sampling clock signal generation circuit and a sampling circuit. When the input signal is activated, the sampling clock signal generation circuit generates a sampling clock signal to be used for sampling the input signal. The sampling circuit comprises two or more flip-flops connected subordinately. When the input signal is activated, the sampling circuit samples the input signal at a primary stage synchronizing with the sampling clock signal, and propagates signals obtained by sampling in order. When the input signal is inactivated, the sampling circuit sets the output signal of the flip-flops to be in an inactivated state to generate the input signal to be supplied to an internal circuit on the basis of the output signal of the flip-flop at a final stage. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit including a noise removal circuit for removing noise mixed in an external reset signal of an MCU (Micro Controller Unit) or an input signal having a specific activation level.

  Generally, in an electronic device, there is a problem that noise occurs in a power supply line or a signal line, and a semiconductor integrated circuit mounted in the electronic device malfunctions due to the influence of the noise. In particular, when noise is applied to the reset terminal of the semiconductor integrated circuit and the semiconductor integrated circuit malfunctions, the internal circuit is initialized, which causes a serious problem for the electronic device.

  For example, an MCU used in an electronic device such as an audio or video device includes a CPU (Central Processing Unit) that performs arithmetic processing, a memory that stores programs and data, and control of external circuits. And a peripheral terminal for performing a reset, and a reset terminal for inputting a reset signal from the outside is provided in order to reset the internal circuit when the power is turned on.

  When noise is applied to the input terminal of a semiconductor integrated circuit and the internal circuit operates in synchronization with the clock signal even if the logic level of the input signal is inverted in the input / output cell to which the input terminal is connected, Although it is possible to eliminate the influence of noise by the logic operation of the circuit, the internal circuit operates asynchronously with the clock signal for reset signals, interrupt signals, etc., so that the logic level of such signals is noise. Is reversed, the influence of noise propagates to the internal circuit, causing the semiconductor integrated circuit to malfunction.

  Various techniques have been developed to deal with such problems. For example, in order to remove pulse noise, an analog filter constituted by a resistor and a capacitor is added. Further, when the reset signal is positive logic, the logical product of the reset signal supplied from the outside and the delayed reset signal obtained by delaying the reset signal is obtained, or when the reset signal is negative logic, By obtaining a logical sum of the reset signal and the delayed reset signal, it is possible to remove a noise pulse of a short period (about 1 nanosecond). However, when the pulse width is increased, noise cannot be removed, and the area of the analog filter and the delay circuit is large, so that the chip area is increased.

  Alternatively, if the reset signal or interrupt signal is sampled using the clock signal, noise can be removed. However, when the semiconductor integrated circuit is in a standby state such as a power saving mode, the clock signal is stopped and sampling is performed. I can't do it.

  As a related technique, the following Patent Document 1 discloses noise removal that removes noise applied to a reset signal or the like of a microprocessor by changing the filtering time of the noise removal circuit using a ring oscillator and a frequency divider circuit. A circuit and a chip reset signal generation circuit using the circuit are disclosed.

  The chip reset signal generating circuit includes a first inverter that inputs a reset bar signal and outputs an inverted signal to the first node, and a first node for removing noise included in the first node signal. A noise removing unit that outputs a signal obtained by dividing the received signal to the second node, a second inverter that inverts and outputs the signal of the first node, a signal of the first node, and a signal of the second node; An AND gate that performs an AND logic operation and outputs an output signal of the second inverter as a set signal, an output signal of the AND gate as a reset signal, and an RS flip-flop circuit unit that generates a chip reset signal at an output terminal; It has.

According to this chip reset signal generation circuit, the malfunction is caused by noise by adjusting the ring oscillator unit and the frequency dividing circuit unit so that the period of the noise applied to the reset bar signal becomes smaller than the filtering time to remove the noise. Can be prevented. However, this chip reset signal generation circuit only generates a chip reset signal based on the state of the reset bar signal at two time points, and malfunctions when pulse noise is applied at these two time points. . In addition, this chip reset signal generation circuit does not support a case where there are a plurality of input signals to be subjected to noise removal.
Japanese Patent Laid-Open No. 2002-314386 (first and fourth pages, FIG. 6)

  Therefore, in view of the above points, the present invention removes noise such as pulse noise mixed in an input signal with high accuracy in a semiconductor integrated circuit to which an input signal such as a reset signal is input from the outside asynchronously with a clock signal. An object of the present invention is to realize a noise removal circuit that can cope with a plurality of input signals.

  In order to solve the above problems, a semiconductor integrated circuit according to one aspect of the present invention includes an input circuit that inputs an input signal asynchronously with a clock signal from the outside, buffers the input signal, and outputs the input signal. A sampling clock signal generation circuit for generating a sampling clock signal used for sampling the input signal when the input signal to be activated is activated, and a sampling circuit including a plurality of cascade-connected flip-flops. When the input signal output from the input circuit is activated, the input signal is sampled in the flip-flop at the first stage in synchronization with the sampling clock signal generated by the sampling clock signal generation circuit. Obtained signals in turn in multiple flip-flops At the same time, when the input signal is deactivated, the output signals of a plurality of flip-flops are set to the deactivated state, and supplied to the internal circuit based on the output signal of the final flip-flop. A sampling circuit for generating an input signal to be transmitted.

  Here, when the input signal is negative logic, the sampling circuit calculates the logical sum of the input signal output from the input circuit and the output signal of the final stage flip-flop, thereby supplying the input signal to the internal circuit. When the input signal is positive logic, the input signal supplied to the internal circuit is generated by obtaining the logical product of the input signal output from the input circuit and the output signal of the final stage flip-flop. A logic circuit may be further included.

  Also, the sampling clock signal generation circuit generates a sampling clock signal by dividing the oscillation signal generated by the ring oscillator that generates an oscillation signal by performing an oscillation operation and the oscillation frequency by a desired division ratio. A frequency divider circuit may be included.

  This semiconductor integrated circuit supplies an internal circuit based on a plurality of input circuits to which a plurality of input signals are respectively input asynchronously with a clock signal and a plurality of input signals respectively output from the plurality of input circuits. A plurality of sampling circuits that respectively generate a plurality of input signals may be provided.

  Furthermore, the sampling circuit further includes a logic circuit that changes the operation of the plurality of flip-flops according to an activation level switching signal having a different level depending on whether an input signal input from the outside is positive logic or negative logic. Also good.

  In this semiconductor integrated circuit, the operation of the sampling clock signal generation circuit may be stopped when an input signal supplied from the sampling circuit to the internal circuit is deactivated.

  According to the present invention, when the input signal is deactivated, the pulse noise mixed in the input signal is set by deactivating the output signals of the plurality of flip-flops that sample and propagate the input signal. It is possible to realize a noise removal circuit that can remove noise such as the above with high accuracy and can also handle a plurality of input signals.

The best mode for carrying out the present invention will be described below in detail with reference to the drawings. The same constituent elements are denoted by the same reference numerals, and the description thereof is omitted.
FIG. 1 is a block diagram showing a schematic configuration of a semiconductor integrated circuit according to first to fourth embodiments of the present invention. In the following embodiments, an example in which the present invention is applied to an MCU (Micro Controller Unit) will be described.

  As shown in FIG. 1, the MCU 100 is a single chip MCU including an input / output cell region 1 in which a plurality of input / output cells are formed, a noise elimination circuit 2, and an internal region 3. A plurality of input / output terminals connected to the input / output cells; The internal area 3 includes a CPU 31 that performs arithmetic processing, a memory area 32 in which a memory that stores programs and data is formed, and a peripheral circuit area 33 in which peripheral circuits that control external circuits and the like are formed. .

  In an actual layout, a plurality of input / output cells are formed at the periphery of the chip, and a plurality of input / output terminals are arranged along the four sides of the chip. The plurality of input / output terminals and input / output cells may be provided separately for input only and output only, or may be provided for both input and output. In the following, a case where an input-only input terminal and an input cell are provided will be described.

  FIG. 2 is a circuit diagram showing a configuration example of a noise removal circuit built in the semiconductor integrated circuit according to the first embodiment of the present invention. The noise removal circuit 2 includes a sampling clock signal generation circuit 20 and a sampling circuit 21. An input signal such as a reset signal is input to the input terminal (pad) PD1 from the outside asynchronously with the clock signal. In the present embodiment, a case where a negative logic (low active) external input signal SIG11 is input to the input terminal PD1 will be described. The external input signal SIG11 is input to the sampling clock signal generation circuit 20 and the sampling circuit 21 via the input buffer 11 provided in the input cell.

  The sampling clock signal generation circuit 20 includes an inverter 201, a NAND circuit 202, and a plurality of buffers 203, 204, 205,... Connected in series. The NAND circuit 202, the buffer 203, and the like constitute a ring oscillator and oscillate at a predetermined frequency when the external input signal SIG11 is activated to a low level. As a result, the NAND circuit 202 outputs the sampling clock signal SCLK.

  The sampling circuit 21 includes a plurality of D flip-flops 211 to 213 and an OR circuit 214. Here, three flip-flops are shown, but the number of flip-flops may be two or more, preferably three or more. The external input signal SIG11 output from the buffer 11 is input to the data input terminal D of the flip-flop 211, the preset terminal P of the flip-flops 211 to 213, and one input terminal of the OR circuit 214. The sampling clock signal SCLK output from the NAND circuit 202 is input to the clock signal input terminals of the flip-flops 211 to 213.

  While the external input signal SIG11 is inactivated to the high level, the flip-flops 211 to 213 are preset, and the outputs of the flip-flops 211 to 213 are at the high level. When the external input signal SIG11 is activated to a low level, the flip-flop 211 samples the external input signal SIG11 in synchronization with the rising edge of the first pulse included in the sampling clock signal SCLK. The result is output from the data output terminal Q as data Q1.

  In synchronization with the rising edge of the second pulse included in the sampling clock signal SCLK, the flip-flop 212 holds the data Q1 output from the flip-flop 211, and uses the result as data Q2 as the data output terminal Q. Output from. The flip-flop 211 samples the external input signal SIG11 and outputs the result as new data Q1 from the data output terminal Q.

  In synchronization with the rising edge of the third pulse included in the sampling clock signal SCLK, the flip-flop 213 holds the data Q2 output from the flip-flop 212, and uses the result as data Q3 for the data output terminal Q. Output from. Similarly, the flip-flop 212 holds new data Q1 output from the flip-flop 211, and outputs the result from the data output terminal Q as new data Q2. The flip-flop 211 samples the external input signal SIG11 and outputs the result as new data Q1 from the data output terminal Q.

  Here, when the external input signal SIG11 is continuously activated to the low level, the data Q1 to Q3 become the low level, but when the external input signal SIG11 becomes the high level even for a moment, the flip-flops 211 to 213 is preset, and the data Q1 to Q3 become high level.

  Data Q 3 output from the data output terminal Q of the flip-flop 213 is input to the other input terminal of the OR circuit 214. Thereby, the OR circuit 214 sets the internal input signal SIG12 to low level only when the external input signal SIG11 is activated to low level and the data Q3 output from the flip-flop 213 is low level. Activate.

Next, the operation of the noise removal circuit shown in FIG. 2 will be described with reference to FIGS.
FIG. 3 is a timing chart showing the waveform of each signal when the external input signal is activated. The external input signal SIG11 is activated to a low level for a predetermined period from a state deactivated to a high level.

  In the sampling clock signal generation circuit 20, when the external input signal SIG11 is inactivated to high level, the output signal of the inverter 201 becomes low level and is input to one input terminal of the NAND circuit 202. Therefore, the output signal of the NAND circuit 202 is fixed at a high level and does not form a clock signal.

  When the external input signal SIG11 is activated to a low level, the output signal of the inverter 201 becomes a high level and is input to one input terminal of the NAND circuit 202. The output signal of the NAND circuit 202 is input to the other input terminal of the NAND circuit 202 via the buffers 203, 204, 205,. Accordingly, the output signal of the NAND circuit 202 is repeatedly inverted at a predetermined time interval to form the sampling clock signal SCLK.

  As a result, as shown in FIG. 3, when the external input signal SIG11 is deactivated to a high level, the sampling clock signal SCLK is not generated, and when the external input signal SIG11 is activated to a low level. A sampling clock signal SCLK is generated. In FIG. 3, one cycle of the sampling clock signal SCLK is represented by “T”. When the external input signal SIG11 is deactivated again to a high level, the sampling clock signal SCLK stops.

  In the sampling circuit 21, the flip-flop 211 receives the external input signal SIG11 and changes the state of the data Q1 to the low level in synchronization with the rising edge of the sampling clock signal SCLK. Similarly, the flip-flop 212 receives the data Q1, and changes the state of the data Q2 to the low level in synchronization with the rising edge of the sampling clock signal SCLK. The flip-flop 213 receives the data Q2, and changes the state of the data Q3 to a low level in synchronization with the rising edge of the sampling clock signal SCLK.

  That is, as shown in FIG. 3, the data Q2 changes to the low level with a delay of one clock cycle T from the data Q1. Similarly, the data Q3 changes to the low level with a delay of one clock period T from the data Q2. Therefore, the data Q3 changes to a low level with a delay of two clock cycles from the rising edge of the sampling clock signal immediately after the external input signal SIG11 is activated.

  When the external input signal SIG11 is deactivated again to the high level, the preset terminals of the flip-flops 211 to 213 are set to the high level, so that the flip-flops 211 to 213 output the high-level data Q1 to Q3.

  Since the OR circuit 214 outputs the logical sum of the external input signal SIG11 and the data Q3 as the internal input signal SIG12, as shown in FIG. 3, the internal input signal SIG12 is immediately after the external input signal SIG11 is activated. When the external input signal SIG11 is deactivated again, it changes to the high level after a delay of two clock cycles from the rising edge of the sampling clock signal.

  FIG. 4 is a timing chart showing the waveform of each signal when pulse noise having a short pulse width is mixed in the external input signal. When the external input signal SIG11 changes to low level for a short period due to noise, the NAND circuit 202 starts outputting the sampling clock signal SCLK.

  The flip-flop 211 receives the external input signal SIG11, and changes the state of the data Q1 to the low level in synchronization with the rising edge of the sampling clock signal SCLK. Similarly, the flip-flop 212 receives the data Q1, and changes the state of the data Q2 to a low level in synchronization with the rising edge of the sampling clock signal SCLK.

  The data Q2 changes to the low level with a delay of one clock period T from the change of the data Q1. Immediately thereafter, since the external input signal SIG11 changes to high level, the data Q2 changes to high level at the same time, and the sampling clock signal SCLK also stops. As a result, the data Q3 does not change to the low level and maintains the high level. Since the OR circuit 214 outputs the logical sum of the external input signal SIG11 and the data Q3 as the internal input signal SIG12, the internal input signal SIG12 also maintains a high level as shown in FIG. That is, the noise mixed in the external input signal SIG11 is filtered and does not propagate to the internal region 3 (FIG. 1).

  Here, the period for filtering noise can be adjusted by the oscillation frequency in the sampling clock signal generation circuit 20 and the number of flip-flops in the sampling circuit 21. The oscillation frequency in the sampling clock signal generation circuit 20 can be adjusted by the number of stages of buffers connected in series.

  Further, when the external input signal SIG11 is inactivated, the sampling clock signal generation circuit 20 stops oscillating, so that it is possible to suppress the generation of extra current consumption. Even when the external input signal SIG11 is positive logic (high active), by changing the logic circuit accordingly, it is possible to realize a noise removal circuit that exhibits the same effect as in the present embodiment. it can.

Next, a second embodiment of the present invention will be described.
FIG. 5 is a circuit diagram showing a configuration example of a noise removal circuit built in a semiconductor integrated circuit according to the second embodiment of the present invention. In the second embodiment, a plurality of external input signals (for example, three external input signals SIG11 to SIG31 are shown) are input to the noise removal circuit 5. The noise removal circuit 5 includes a sampling clock signal generation circuit 50 and a plurality of sampling circuits (showing first to third sampling circuits 21a to 21c as examples). The configuration of each of the sampling circuits 21a to 21c is the same as that of the sampling circuit 21 in the first embodiment shown in FIG.

  A plurality of external input signals SIG11 to SIG31 are input to the sampling clock signal generation circuit 50 and the corresponding sampling circuits 21a to 21c via the input terminals PD1 to PD3 and the input buffers 11 to 13 provided in the input cells, respectively. The Here, it is assumed that the external input signal SIG11 is positive logic, and the external input signals SIG21 and SIG31 are negative logic.

  The sampling clock signal generation circuit 50 includes inverters 501 and 502 for inverting a negative logic external input signal, a three-input OR circuit 503, a NAND circuit 202, buffers 203, 204, 205,. And a frequency dividing circuit 504. The NAND circuit 202, the buffer 203, and the like constitute a ring oscillator as in the sampling clock signal generation circuit 20 shown in FIG.

  The OR circuit 503 activates the sampling clock enable signal EBL to a high level when any external input signal is activated. When the sampling clock enable signal EBL is activated, the ring oscillator constituted by the NAND circuit 202, the buffer 203, and the like starts an oscillation operation.

  The oscillation signal output from the ring oscillator is supplied to the frequency dividing circuit 504, and the frequency dividing circuit 504 divides the oscillation signal to generate the sampling clock signal SCLK. Note that the configuration may be such that the sampling clock enable signal EBL is supplied to the reset terminal (negative logic) of the frequency dividing circuit 504 in order to initialize the frequency dividing circuit 504 when any external input signal is not activated. .

  Generally, in a ring oscillator composed of a plurality of gates having a delay time, in order to reduce the oscillation frequency and increase the period of the oscillation signal, the number of gates is increased. There is a problem that it gets bigger. Therefore, in the second embodiment, by arranging the frequency dividing circuit 504 at the subsequent stage of the ring oscillator, a sampling clock signal having a large cycle is obtained without increasing the circuit scale.

  The sampling clock signal SCLK output from the frequency dividing circuit 504 is supplied to the first to third sampling circuits 21a to 21c. As described in the first embodiment, the first to third sampling circuits 21a to 21c filter the noise mixed in the external input signals SIG11 to SIG31 in a predetermined period, and perform the first operation. To output third internal input signals SIG12 to SIG32.

Next, a third embodiment of the present invention will be described.
FIG. 6 is a circuit diagram showing a configuration example of a noise removal circuit built in a semiconductor integrated circuit according to the third embodiment of the present invention. In the third embodiment, the case where the external input signal is positive logic or negative logic can be handled.

  The noise removal circuit 6 includes a sampling clock signal generation circuit 60 and a sampling circuit 61. The external input signal SIG41 is input to the sampling clock signal generation circuit 60 and the sampling circuit 61 via the input terminal PD1 and the input buffer 11 provided in the input cell.

  The activation level switching signal ACT is input to the sampling clock signal generation circuit 60 and the sampling circuit 61. The activation level switching signal ACT represents the level when the external input signal SIG41 is inactivated. When the external input signal SIG41 is positive logic (high active), the activation level switching signal ACT becomes low level, and the external input signal SIG41. When is negative logic (low active), it becomes high level.

  In the sampling clock signal generation circuit 60, the external input signal SIG41 output from the input buffer 11 is input to one input terminal of an exclusive OR (EOR) circuit 601, and the activation level switching signal ACT is input to the EOR circuit 601. Is input to the other input terminal. The EOR circuit 601 activates the sampling clock enable signal EBL to a high level when the external input signal SIG41 is activated. The other configuration of the sampling clock signal generation circuit 60 is the same as that of the second embodiment shown in FIG.

  The sampling circuit 61 includes a NAND circuit 611, an OR circuit 612, D flip-flops 613 and 614, an AND circuit 615, and a NAND circuit 616. The AND circuit 615 has two non-inverting input terminals and one inverting input terminal, and the NAND circuit 616 has two inverting input terminals and one non-inverting logic output terminal.

  The external input signal SIG41 is connected to one input terminal of the NAND circuit 611, one input terminal of the OR circuit 612, the data input terminal of the flip-flop 613, and one non-inverting input of the AND circuit 615 via the buffer 11. The terminal and one inverting input terminal of the NAND circuit 616 are connected.

  The activation level switching signal ACT is connected to the other input terminal of the NAND circuit 611, the other input terminal of the OR circuit 612, the inverting input terminal of the AND circuit 615, and the non-inverting input terminal of the NAND circuit 616. Yes. The activation level switching signal ACT may be a signal from the outside of the semiconductor integrated circuit or a signal generated inside the semiconductor integrated circuit.

  The output signal of the NAND circuit 611 is input to the preset terminal P bar (negative logic) of the flip-flops 613 and 614. The output signal of the OR circuit 612 is input to the reset terminal R bar (negative logic) of the flip-flops 613 and 614. The sampling clock signal SCLK output from the frequency dividing circuit 504 is connected to the clock signal input terminals of the flip-flops 613 and 614. Data Q1 output from the flip-flop 613 is input to the data input terminal D of the flip-flop 614, and data Q2 output from the flip-flop 614 is one non-inverting input terminal of the AND circuit 615 and one of the NAND circuit 616. Are input to two inverting input terminals.

  When the external input signal SIG41 is positive logic (high active), the AND circuit 615 outputs the first internal input signal SIG42. At this time, the NAND circuit 616 sets the second internal input signal SIG52 to the high level. Fix it. On the other hand, when the external input signal SIG41 is negative logic (low active), the NAND circuit 616 outputs the second internal input signal SIG52. At this time, the AND circuit 615 sets the first internal input signal SIG42 to low. Pin to level.

Next, the operation of the noise removal circuit in the third embodiment will be described. First, the case where the external input signal SIG41 is positive logic (high active) will be described.
When the external input signal SIG41 is positive logic (high active), the activation level switching signal ACT is set to low level. When the activation level switching signal ACT having the low level is input to the non-inverting input terminal of the NAND circuit 616, the second internal input signal SIG52 is fixed to the high level.

  When the external input signal SIG41 is activated from low level to high level, the sampling clock enable signal EBL becomes high level. Accordingly, in the sampling clock signal generation circuit 60, the ring oscillator operates to generate the sampling clock signal SCLK.

  Further, since the activation level switching signal ACT input to the inverting input terminal of the AND circuit 615 is at a low level, the external input signal SIG41 that has passed through the flip-flops 613 and 614 while the external input signal SIG41 is at a high level. Is output from the AND circuit 615 as the first internal input signal SIG42. When the external input signal SIG41 becomes low level again, the flip-flops 613 and 614 are reset, and the first internal input signal SIG42 is inactivated to low level.

  Next, a case where the external input signal SIG41 is negative logic (low active) will be described. When the external input signal SIG41 is negative logic (low active), the activation level switching signal ACT is set to high level. When the high level activation level switching signal ACT is input to one inverting input terminal of the AND circuit 615, the first internal input signal SIG42 is fixed to the low level.

  When the external input signal SIG41 is activated from high level to low level, the sampling clock enable signal EBL becomes high level. Accordingly, in the sampling clock signal generation circuit 60, the ring oscillator operates to generate the sampling clock signal SCLK.

  In addition, since the activation level switching signal ACT input to the non-inverting input terminal of the NAND circuit 616 is at a high level, the external input signal that has passed through the flip-flops 613 and 614 while the external input signal SIG41 is at a low level. The SIG 41 is output from the NAND circuit 616 as the second internal input signal SIG 52. When the external input signal SIG41 becomes high level again, the flip-flops 613 and 614 are preset, and the first internal input signal SIG42 is inactivated to high level.

  As a result, even if noise is mixed in the external input signal SIG41, the noise mixed in a predetermined period can be filtered in the same manner as described in the first embodiment. In the third embodiment, when there is a first mode in which a single external input signal SIG41 is activated at a high level and a second mode in which it is activated at a low level, the activation level is present. Any mode can be supported by supplying the switching signal ACT. Further, by sharing the same noise removal circuit in a plurality of modes, it is possible to prevent an increase in circuit scale.

Next, a fourth embodiment of the present invention will be described.
FIG. 7 is a circuit diagram showing a configuration example of a noise removal circuit built in a semiconductor integrated circuit according to the fourth embodiment of the present invention. The noise removal circuit 7 includes a sampling clock signal generation circuit 70 and a sampling circuit 21. The configuration of the sampling circuit 21 is the same as that in the first embodiment shown in FIG. A negative logic (low active) external input signal SIG11 is input to the sampling clock signal generation circuit 70 and the sampling circuit 21 via the input terminal PD1 and the input buffer 11 provided in the input cell.

  In the sampling clock signal generation circuit 70, the external input signal SIG11 output from the input buffer 11 is input to the inverting input terminal of the AND circuit 701, and the internal input signal SIG12 is input to the non-inverting input terminal of the AND circuit 701. . The other configuration of the sampling clock signal generation circuit 70 is the same as that of the first embodiment shown in FIG.

  The output of the AND circuit 701 is input to one input terminal of the NAND circuit 202 as the sampling clock enable signal EBL. The ring oscillator constituted by the NAND circuit 202 and the buffers 203, 204, 205,... Starts an oscillation operation when the sampling clock enable signal EBL is activated to a high level.

Next, the operation of the noise removal circuit in the fourth embodiment will be described.
When the external input signal SIG11 is inactivated to the high level, the clock enable signal EBL is at the low level, and the sampling clock signal SCLK is not generated. Further, the internal input signal SIG12 is deactivated to a high level.

  When the external input signal SIG11 is activated from high level to low level, the sampling clock enable signal EBL becomes high level, and the ring oscillator generates the sampling clock signal SCLK. Therefore, the external input signal SIG11 sequentially passes through the flip-flops 211 to 213 and is output from the OR circuit 214 as the internal input signal SIG12.

  When the internal input signal SIG12 is activated from the high level to the low level, the output of the AND circuit 701 becomes the low level, the oscillation operation in the ring oscillator is stopped, and the sampling clock signal SCLK is suppressed. Thus, in the fourth embodiment, by providing a function of stopping the ring oscillator at the timing when the internal input signal SIG12 is deactivated, it is possible to reduce current consumption due to unnecessary oscillation operation.

The block diagram which shows schematic structure of the semiconductor integrated circuit which concerns on 1st-4th embodiment. FIG. 3 is a circuit diagram illustrating a configuration example of a noise removal circuit according to the first embodiment. The timing chart which shows the waveform of each signal when an external input signal is activated. The timing chart which shows the waveform of each signal when pulse noise is mixed. The circuit diagram which shows the structural example of the noise removal circuit in 2nd Embodiment. The circuit diagram which shows the structural example of the noise removal circuit in 3rd Embodiment. The circuit diagram which shows the structural example of the noise removal circuit in 4th Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Input / output cell area, 2, 5-7 Noise removal circuit, 3 Internal area, 11-13 Input buffer, 20, 50, 60, 70 Sampling clock signal generation circuit 21, 61 Sampling circuit, 21a-21c 1st-1st 3 sampling circuits, 31 CPU, 32 memory area, 33 peripheral circuit area, 100 MCU, 201, 501, 502 inverter, 202, 611, 616 NAND circuit, 203-205 buffer, 211-213, 613, 614 flip-flop, 214, 503, 612 OR circuit, 504 frequency dividing circuit, 601 exclusive OR circuit, 615, 701 AND circuit, PD1-PD3 input terminal

Claims (6)

An input circuit that inputs an input signal asynchronously with the clock signal from the outside, and buffers and outputs the input signal;
A sampling clock signal generation circuit for generating a sampling clock signal used for sampling the input signal when the input signal output from the input circuit is activated;
A sampling circuit including a plurality of cascade-connected flip-flops, which is synchronized with a sampling clock signal generated by the sampling clock signal generation circuit when an input signal output from the input circuit is activated. Then, the input signal is sampled in the first flip-flop, the signals obtained by the sampling are sequentially propagated in the plurality of flip-flops, and when the input signal is deactivated, the plurality of flip-flops The sampling circuit that generates an input signal to be supplied to the internal circuit based on the output signal of the flip-flop at the final stage by setting the output signal to an inactive state;
A semiconductor integrated circuit comprising:   When the input signal is negative logic, the sampling circuit obtains an input signal supplied to the internal circuit by calculating a logical sum of the input signal output from the input circuit and the output signal of the final flip-flop. When the input signal is positive logic, the input signal supplied to the internal circuit is generated by obtaining the logical product of the input signal output from the input circuit and the output signal of the final stage flip-flop. The semiconductor integrated circuit according to claim 1, further comprising a logic circuit. The sampling clock signal generation circuit includes:
A ring oscillator that generates an oscillation signal by performing an oscillation operation;
A frequency dividing circuit for generating a sampling clock signal by dividing the oscillation signal generated by the ring oscillator by a desired frequency dividing ratio;
The semiconductor integrated circuit according to claim 1, comprising: A plurality of the input circuits to which a plurality of input signals are respectively input asynchronously with the clock signal;
A plurality of sampling circuits that respectively generate a plurality of input signals to be supplied to an internal circuit based on a plurality of input signals respectively output from the plurality of input circuits;
The semiconductor integrated circuit according to claim 1, further comprising:   The sampling circuit further includes a logic circuit that changes operations of the plurality of flip-flops according to an activation level switching signal having different levels depending on whether an externally input signal is positive logic or negative logic. The semiconductor integrated circuit according to claim 1. 4. The semiconductor integrated circuit according to claim 1, wherein an operation of the sampling clock signal generation circuit is stopped when an input signal supplied from the sampling circuit to an internal circuit is deactivated. 5.

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