JP2007014361A - Power device and magnetic resonance imaging system using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power device and a magnetic resonance imaging system using the same which improve the relationship between output voltage and conduction rate of a semiconductor switch of a multilevel PWM inverter and reduce output current ripple. <P>SOLUTION: The power device comprises the multilevel PWM (pulse width modulation) inverters 12 having the same number of levels, current detection means 18, and switching control means 19 for actuating and controlling the semiconductor switches of the multilevel PWM inverters in accordance with voltage command signals from current control sections 41. The switching control means 19 of the power device generates a standard triangular wave from a triangular wave generation section 40. A shifted triangular wave having a predetermined shifted phase is then generated, and comparison sections 42b and 42c compares the standard triangular wave, shifted triangular wave and the voltage command signal. The compared results are added by an addition section 42d. The value added by the addition section and a reference comparison value are compared to generate a PWM control signal, and the semiconductor switches of the inverter are actuated and controlled. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a power supply device, and in particular, a power supply device suitable for various power sources required for generating a static magnetic field, a gradient magnetic field, and a high-frequency magnetic field that require high power, and a magnetic resonance imaging apparatus (hereinafter referred to as an MRI apparatus) using the same ).

An MRI device applies a high-frequency magnetic field in a pulsed manner to a test object placed in a static magnetic field, detects a nuclear magnetic resonance signal generated from the test object, and forms a spectrum and an image based on this detection signal It is.
This MRI apparatus is equipped with a superconducting coil that generates a static magnetic field, a gradient coil for generating a gradient magnetic field superimposed on the static magnetic field, and a high-frequency coil for generating a high-frequency magnetic field as a magnetic field generating coil. Yes.
These magnetic field generating coils are provided with a power supply device for controlling the magnitude and timing of an applied current in order to generate a magnetic field having a predetermined magnetic field strength.

In such an MRI apparatus, the magnetic field strength of a static magnetic field, a gradient magnetic field, and a high-frequency magnetic field greatly affects noise on an image finally obtained and imaging time.
In addition, as a magnetic field power source for an MRI apparatus in order to obtain an image useful for diagnosis in a short time, the current flowing through the magnetic field coil that generates the magnetic field has a short rise and fall time, and the ripple and fluctuation of the current after the rise are short. There is no need for a highly stable and highly accurate power supply.

As such a high-current, high-accuracy power supply device, a multi-level PWM (Pulse Width Modulation) inverter constitutes a switching power supply, and the load of this switching power supply is used as a magnetic field generating coil of the MRI apparatus There is what is disclosed in 1.
Japanese Patent Laid-Open No. 2004-266884

What is important for application to a power supply device for an MRI apparatus is to improve the accuracy of the output voltage, and in particular to improve the accuracy of the output voltage near zero in order to supply a stable DC current.
That is, it is necessary to make the current flowing through the magnetic field coil coincide with the current command value of the coil and to make the current low ripple, and in particular, it is necessary to reduce the output voltage zero and the ripple near the zero.

The power supply device using the multilevel PWM inverter of Patent Document 1 has output voltage level switching.
At this switching point, when switching from a low potential level to a high potential level, the PWM control pulse width for controlling the low potential voltage is maximized, and the PWM control pulse width for controlling the high potential voltage is Minimal.
Conversely, when switching from a high potential level to a low potential level, the PWM control pulse width for controlling the high potential voltage is minimized, and the PWM control pulse width for controlling the low potential voltage is maximized. .
These minimum pulse width and maximum pulse width are limited by hardware due to the presence of dead time, and due to this limitation, an area where the average output voltage becomes discontinuous (dead band area) occurs near the level switching, and the output current is reduced. It becomes impossible to control with high accuracy.
Note that the dead time is the time during which both the upper and lower arms become non-conductive in order to prevent the DC power supply short circuit of the multi-level PWM inverter due to the switching speed variation of the switching elements and the like. This time is called dead time.

In the above multi-level PWM inverter, in general, from the viewpoint of ensuring withstand voltage, reducing noise and suppressing leakage current, the intermediate potential of the DC voltage source can be grounded to an odd number such as 3 levels or 5 levels. A multi-level PWM inverter is often used.
However, since the multi-level PWM inverter of the odd level is configured by connecting DC voltages having the same number of levels minus one in series to form a DC voltage source, the number of DC voltages having the same voltage is The voltage at the connection point of the DC voltage is a voltage level switching voltage.
This switching of the output voltage level causes a discontinuous period in the relationship between the conduction ratio of the semiconductor switch of the multi-level PWM inverter and the output voltage due to the existence of the dead time and the limitations of the minimum pulse width and maximum pulse width. Also, the generated current ripple cannot be ignored. Note that the period of discontinuity does not occur directly due to dead time, but the existence of the dead time limits the minimum and maximum pulse width of the PWM control pulse, and the effect is large. Indirectly, the dead time is a cause of the dead zone region in the vicinity of level switching.

  As described above, in the multilevel PWM inverter, the problem of the dead zone and current ripple occurs near the level switching, and the influence of the minimum pulse width limitation is large especially near the output voltage of zero, which causes the output current ripple to be reduced. Increase. When this power supply device is used for a gradient magnetic field generating power supply device of an MRI apparatus, the current ripple causes a reduction in image quality of the MRI image. However, this problem has not been taken into consideration in the above-mentioned Patent Document 1.

  Accordingly, an object of the present invention is to improve the relationship between the conduction ratio of the semiconductor switch of the multilevel PWM inverter and the output voltage and reduce the output current ripple in the vicinity of zero of the output voltage generated by limiting the minimum pulse width of PWM control. And a magnetic resonance imaging apparatus using the same.

  The power supply device of the present invention constitutes a switching power supply using a multi-level PWM inverter, uses the multiphase carrier system for PWM control of the switching power supply, and achieves the above object by shifting the phase between the multiphase carrier waves, The magnetic resonance imaging apparatus of the present invention achieves the above object by using the power supply device as a magnetic field generating power supply device, and is specifically achieved by the following means.

  (1) A power supply device of the present invention includes a pulse width modulation control multilevel inverter (multilevel PWM inverter), current detection means for detecting an output current to the load of the multilevel PWM inverter, and detection by the current detection means Switching control means for driving and controlling the multi-level PWM inverter by a control signal for controlling the difference between the value and the current command value to be zero. Based on the control signal and the multiphase carrier generation means for generating, the carrier phase shift means for shifting the phase of the multiphase carrier, the carrier generated by the multiphase carrier generation means and the carrier phase shift means, and the control signal Drive signal generation means for driving and controlling the multi-level PWM inverter.

  The multiphase carrier generation means and the carrier phase shift means are means for generating a reference carrier and a carrier whose phase is shifted from the carrier, and the drive signal generation means is the reference carrier and the phase. A first comparison means for comparing the control signal with the shifted carrier wave, a means for adding the output of the first comparison means, and a second for comparing the output of the addition means and a plurality of reference comparison values And comparing means.

  (2) The multi-level PWM inverter is a plurality of parallel-connected multi-level PWM inverters having the same number of levels, further comprising phase shift means between parallel inverters for shifting a switching phase between the plurality of multi-level inverters. .

  (3) Further, the magnetic resonance imaging apparatus of the present invention includes a pulse width modulation control multilevel PWM inverter, a current detection means for detecting an output current to the load of the multilevel PWM inverter, and a detection value by the current detection means. And a switching control means for driving and controlling the multi-level inverter by a control signal for controlling the difference between the current command value and the current command value to be zero, wherein the load generates a magnetic field The above-described power source device (1) is used as the magnetic field generating power source device.

  Furthermore, the magnetic resonance imaging apparatus of the present invention includes a plurality of parallel-connected multi-level PWM inverters of the same level, current detection means for detecting an output current to the load of each of the multi-level PWM inverters, A magnetic resonance imaging apparatus having a power supply device including a switching control unit that drives and controls the multilevel PWM inverter by a control signal that controls a difference between a detection value by a current detection unit and a current command value to be zero. The load is a magnetic field generating coil, and the magnetic field generating power supply device is provided with phase shift means between parallel inverters for shifting the switching phase between the plurality of multilevel PWM inverters.

In this way, the multi-phase carrier generated by the multi-phase carrier generating means is used as the carrier of the multi-level PWM inverter, the phase between these multi-phase carriers is shifted to an arbitrary phase by the carrier phase shift means, and the multi-phase carrier generation is performed. And a carrier current generated by the carrier phase shift means and a load current control signal (a signal for controlling the difference between the output current to the load of the multilevel PWM inverter and the current command value to be zero). Since the multilevel PWM inverter is driven and controlled, the operation PWM control signal (PWM Upper, PWM Lower, PWM 1 Upper, PWM 1 Lower, PWM 2 Upper, PWM 2 Lower, PWM 1 Upper, PWM 1 MID in the embodiment) The minimum pulse width of signals (Upper, PWM 1 MID Lower, PWM 1 Lower, etc.) can be kept away from near zero of the output voltage.
As a result, the discontinuity of the output voltage near zero is improved, and the relationship between the conduction ratio Duty of the semiconductor switch of the multilevel PWM inverter and the output voltage is a continuous characteristic with no dead band.
Therefore, the output voltage zero and the current ripple flowing through the load near the zero can be reduced, and the image quality of the magnetic resonance imaging apparatus using the power supply apparatus is remarkably improved.
In addition, since the frequency of the above-mentioned operation PWM signal is also half that of the prior art, the switching loss of the semiconductor switch is greatly reduced, and a semiconductor switch with a smaller current capacity can be used to obtain the same output, so a multi-level PWM inverter A power supply device using a circuit and a magnetic resonance imaging apparatus using the same can be made small and inexpensive.
In addition, a plurality of multi-level PWM inverters of the same level are connected in parallel, and phase shift means between parallel inverters for shifting the switching phase between the plurality of multi-level PWM inverters is provided. The output current ripples operate to cancel each other, thereby significantly reducing the ripple of current flowing through the load.
Therefore, the image quality of the magnetic resonance imaging apparatus is further improved by using this power supply apparatus for the magnetic resonance imaging apparatus.

As described above, according to the present invention, since the power supply apparatus uses a multiphase carrier system for PWM control of a multilevel PWM inverter and shifts the phase between the multiphase carrier waves, the power generation apparatus is generated by limiting the minimum pulse width of PWM control. The relation between the conduction ratio of the semiconductor switch of the multi-level PWM inverter near the output voltage and the output voltage is improved, and the ripple of the output current can be reduced. Therefore, the image quality of the magnetic resonance imaging apparatus using this power supply apparatus is remarkably improved.
In addition, since multiple parallel-level PWM inverters with the same number of levels are connected in parallel and phase-shifting means between parallel inverters that shifts the switching phase between these multiple-level PWM inverters is provided, the ripple of current flowing in the load of output current is The image quality of the magnetic resonance imaging apparatus using this power supply apparatus is further improved and further improved.

Preferred embodiments of a power supply apparatus and a magnetic resonance imaging apparatus using the same according to the present invention will be described below in detail with reference to the accompanying drawings.
FIG. 1 is a block configuration diagram showing a gradient magnetic field power supply device of an MRI apparatus as a power supply device according to the first embodiment of the present invention.
This gradient magnetic field power supply device 2 is configured to supply power from a three-phase AC power source 3 and connect to a gradient magnetic field coil 1 that is a load to supply current. An AC-DC converter 4 that converts AC voltage into DC voltage, a smoothing capacitor 5 that is connected to the output side of the AC-DC converter 4 to smooth the DC voltage, and is connected to the smoothing capacitor 5 for smoothing. Current amplifiers 9 to 11 that receive the converted DC voltage and supply current to the X-axis coil 6, the Y-axis coil 7, and the Z-axis coil 8 of the gradient magnetic field coil 1, respectively.

  The current amplifier 9 includes a multi-level PWM inverter 12 connected in parallel to a smoothing capacitor 5 that is an input DC voltage source, and an output of the multi-level PWM inverter 12 to an X-axis coil 6 of a gradient coil 1 that is a load. Supply current detection means 18 for detecting the current flowing in the X-axis coil, and input the current command value from the sequencer 20 of the MRI apparatus and the current detection value output from the current detection means 18, and the difference between the two A switching control circuit 19 that drives and controls the multi-level PWM inverter 12 so that becomes zero, and a multi-phase carrier wave (hereinafter referred to as a carrier wave) for the PWM control of the multi-level PWM inverter 12 provided in the switching control circuit 19 And a control means for shifting the phase between the majority carriers.

  The current amplifier 10 has the same configuration, and the Y-axis coil 7 is connected to the output side of the multilevel PWM inverter 12, and detects the current command value from the sequencer 20 of the MRI apparatus and the current flowing through the Y-axis coil 7 as a load. A switching control circuit 19 that inputs the current detection value of the current detection means 18 and drives and controls the multilevel PWM inverter 12 so that the difference between the two becomes zero, and the switching control circuit 19 provided with the multilevel PWM The multiphase carrier method is used for PWM control of the inverter 12, and control means for shifting the phase between the multiphase carriers is provided.

  The current amplifier 11 has the same configuration, and a Z-axis coil 8 is connected to the output side of the multi-level PWM inverter circuit 12 to detect a current command value from the sequencer 20 of the MRI apparatus and a current flowing through the Z-axis coil. A switching control circuit 19 that inputs the current detection value of the means 18 and drives and controls the multilevel PWM inverter 12 so that the difference between the two becomes zero, and the multilevel PWM inverter 12 provided in the switching control circuit 19 The PWM control uses a multiphase carrier system, and includes control means for shifting the phase between the multiphase carriers.

FIG. 2 is a circuit diagram of a three-level PWM inverter as the multi-level PWM inverter 12.
The three-level PWM inverter is configured to connect DC voltage sources E and E0 to its inputs and output arbitrary voltage waveforms to its output terminals A and B.
In addition, this three-level PWM inverter connects the voltage dividing capacitors 21 and 22 between the DC voltage source E-E0 to divide the DC voltage into two (E / 2), and two pairs of MOSFETs connected in reverse parallel ( Metal Oxide Semiconductor Field Effet Transistor (MOS-type field effect transistor) has 4 sets of arms 27 to 30 in which diode switches 25 and 26 and diodes 25 and 26 are connected in series. ing.
The diodes 31, 32, 33, and 34 are connected between the connection point of the voltage dividing capacitors 21 and 22 (level 2 potential) and the connection point of the semiconductor switch of each arm 27-30 in the full bridge configuration. .
That is, the diode 31 is connected between the connection point of the semiconductor switches 23 and 24 of the arm 27 and the connection point of the voltage dividing capacitors 21 and 22 as shown in the figure, and the connection point of the semiconductor switches 23 and 24 of the arm 28 and the connection point. The diode 32 is connected between the connection point of the voltage capacitors 21 and 22, the diode 33 is connected between the connection point of the semiconductor switches 23 and 24 of the arm 29 and the connection point of the voltage dividing capacitors 21 and 22, and the semiconductor of the arm 30. A diode 34 is connected between the connection point of the switches 21 and 22 and the connection point of the voltage dividing capacitors 21 and 22.

  Here, by making the semiconductor switches 23 and 24 of the arm 27 conductive, a voltage of + E can be output to the output terminal A, and the semiconductor switches 23 and 24 of the arm 27 and the semiconductor switch 23 of the arm 28 are made conductive. Can output a voltage of + E / 2 to the output terminal A, and can further output a voltage of 0 to the output terminal A by making the semiconductor switches 23 and 24 of the arm 28 conductive. , Can output 3 levels of voltage.

The same applies to the output terminal B. As a result, five voltages from -E to + E (-E, -E / 2, 0, + E / 2, E ) Can be output.
Furthermore, by controlling these, any voltage can be output between -E and + E, where the ripple of the output current is very small.

Here, before describing the operation of the multilevel PWM inverter of FIG. 1 used in the power supply device of the present invention, the multiphase carrier system used in the present invention will be described.
The polyphase carrier method uses a triangular wave carrier (carrier) whose phase is shifted by 2π / n, which is one less than the number of levels, from the PWM signal obtained from each carrier signal and the comparison signal. An operation PWM signal is obtained, and the semiconductor switch of the multilevel PWM inverter is subjected to switching control by the operation PWM signal.

  In the case of a three-level inverter, as shown in FIG. 3, two carriers A and B in (a) are used as the triangular wave carrier, and the phases of Carrier A and Carrier B are shifted by 180 degrees. From (b) PWM A and PWM B obtained by comparing each carrier and voltage command (Voltage Command), (c) PWM Upper (PWM A AND PWM B) and PWM Lower (PWM A OR PWM B), the switching control of the semiconductor switch of the three-level PWM inverter is performed. In the case of FIG. 2, the semiconductor switch 23 of the arm 27 is controlled by a signal obtained by inverting the PWM Upper signal, and the semiconductor of the arm 28 is controlled by the PWM Upper signal. The switch 23 controls the semiconductor switch 24 of the arm 27 with a signal obtained by inverting the PWM Lower signal, and controls the semiconductor switch 24 of the arm 28 with the PWM Lower signal.

When this method is used, as shown by the round solid line in Fig. 3 (a), the PWM Upper and PWM Lower are limited to the minimum pulse width near the output voltage zero (the pulse width should be narrower than this). As shown in FIG. 4, the relationship between the conduction ratio Duty of the semiconductor switch of the multilevel PWM inverter and the output voltage becomes discontinuous near zero voltage.
Thus, the problem of discontinuity near zero of the output voltage remains only by using the multiphase carrier system for the triangular wave carrier.
Therefore, the present invention solves the above problem by shifting the phase of the multiphase carrier.

FIG. 5 is a configuration diagram of the switching control circuit 19 which is the main part of the present invention in the first embodiment of the present invention in which the phases of the multiphase carriers are shifted, and the multilevel PWM inverter 12 (see FIGS. 1 and 2). 4 shows a circuit for controlling the switching of the semiconductor switches 23 and 24 of the arms 27 and 28 on the output terminal A side, and the semiconductor switches 23 and 24 of the arms 29 and 30 on the output terminal B side Since switching control can be performed with the same configuration, it is omitted.
Note that 23a, 24a and 23b, 24b of the multi-level PWM inverter 12 are circuits for driving the semiconductor switches 23, 24.

The operation of the first embodiment of the present invention will be described using the switching control circuit 19 of FIG. 5 and the waveform diagrams of the respective parts of FIG.
In FIG. 5, the switching control circuit 19 is a circuit that generates a plurality of carrier signals during one cycle of the operating frequency of the multilevel PWM inverter to generate a PWM control signal, and a triangular wave generator 40 that generates a carrier signal, The current command value output from the MRI sequencer 20 (see FIG. 1) is input, and the difference between this current command value and the detected value by the current detecting means 18 for detecting the gradient coil current that is the load current becomes zero. A current control unit 41 that outputs a current control signal for control, an upper semiconductor switch 23 of the arms 27 and 28 of the multilevel PWM inverter 12, and a lower semiconductor of the arms 27 and 28 of the multilevel PWM inverter 12 And a first gate signal generation circuit 42 for generating a gate signal of the switch 24.

  In the first gate signal generation circuit 42, the triangular wave carrier signal Carrier A shown in FIG. 6 (a) generated by the triangular wave generation unit 40 is input to the comparison unit 42b, and this Carrier A is input to the second phase shift unit 42a. The delayed signal Carrier B (FIG. 6 (a)) is input to the comparison unit 42c.

  These Carrier A and Carrier B are compared with the voltage command signal (Voltage Command in FIG. 6 (a)) output from the current control unit 41 by the comparison units 42b and 42c, and the voltage command signal is the Carrier A 6 (b), the logic signal “High” is set to “1” during a period longer than that, and the logic signal “Low” is set to “0” during a period when the voltage command signal is less than the carrier A. PWM A is output from the comparison unit 42b, the period when the voltage command signal is larger than the Carrier B, the logic signal "High" is "1", the period when the voltage command signal is smaller than the Carrier B, The PWM B shown in FIG. 6 (b) in which the logic signal “Low” is “0” is output from the comparison unit 42c.

As shown in FIG. 5, the PWM A and PWM B signals output from the comparison units 42b and 42c are added by the addition unit 42d, and the addition value, the comparison value 1, and the comparison value 0 are compared with each other in the comparison units 42e and 42f. Compare with.
Then, when the added value is larger than the comparison value 1, the PWM Upper signal shown in FIG. 6 (c) that becomes the logic signal “High” is output from the comparison unit 42e, and the added value is larger than the comparison value 0. When it is larger, the PWM Lower signal shown in FIG. 6 (c), which becomes the logic signal “High”, is output from the comparison unit 42f.
The thus generated PWM Upper signal is inverted by the signal inverting unit 42g, this signal is amplified by the drive circuit 23a, and the semiconductor switch 23 of the arm 27 is switched and driven, and the PWM Upper signal is amplified by the drive circuit 23b as it is. Then, the semiconductor switch 23 of the arm 28 is switched and driven.
On the other hand, the PWM Lower signal is inverted by the signal inverting unit 42h, and this signal is amplified by the drive circuit 24a to drive the semiconductor switch 24 of the arm 27, and the PWM Lower signal that is not inverted is directly amplified by the drive circuit 24b. Then, the semiconductor switch 24 of the arm 28 is driven to be switched.

In this way, by delaying Carrier B by 90 degrees from Carrier A, the minimum pulse width of the PWM Upper signal and PWM Lower signal is reduced by 25% from near zero of the output voltage, as shown by the solid circle in FIG. Can be moved to near (timing when Carrier A ≤ Carrier B first from the timing when the output voltage becomes zero), and around 75% (timing when Carrier A ≥ Carrier B from the timing when the output voltage becomes zero) .
The amount of movement of the minimum pulse width of these PWM Upper and PWM Lower signals in the output voltage direction varies depending on the phase of Carrier B. By adjusting the phase of Carrier B, the timing of the minimum pulse width can be adjusted. The discontinuity of the output voltage near zero can be improved by setting the phase of Carrier B to an appropriate value, and the conduction ratio Duty and output voltage of the semiconductor switch of the multilevel PWM inverter can be adjusted arbitrarily. Is a continuous characteristic with no dead zone.

FIG. 7 is a block configuration diagram showing a gradient magnetic field power supply device of an MRI apparatus as a power supply device according to the second embodiment of the present invention.
This gradient magnetic field power supply device 2 connects two sets of the three-level PWM inverters described in FIG. 2 (multi-level PWM inverters 12 and 13 described later) in parallel, and performs switching control by shifting the operation phase between these parallel inverters. In this way, the current capacity of the current amplifier is increased and the current ripple flowing through the load is reduced. Power is supplied from the three-phase AC power source 3 and connected to the gradient coil 1 as a load to supply current. Connected to the three-phase AC power source 3 to convert the three-phase AC voltage to DC voltage, and connected to the output side of this AC-DC converter 4 to smooth the DC voltage A smoothing capacitor 5 that receives the smoothed DC voltage connected to the smoothing capacitor 5 and supplies current to the X-axis coil 6, the Y-axis coil 7, and the Z-axis coil 8 of the gradient magnetic field coil 1, respectively. With amplifiers 9-11 To have.

  The current amplifier 9 is connected to two multi-level PWM inverters 12 and 13 connected in parallel to the smoothing capacitor 5 that is a DC voltage source of the input, respectively, and connected to the output side of the multi-level PWM inverters 12 and 13, respectively. Current limiting means 14 to 17 connected in parallel to the X-axis coil 6 of the gradient magnetic field coil 1 as a load, current detection means 18 for detecting the output current of the current amplifier 9, and from the sequencer 20 of the MRI apparatus The switching control circuit 19 ′ that inputs the current command value and the current detection value that is the output of the current detection means 18 and drives and controls the multilevel PWM inverters 12 and 13 so that the difference therebetween becomes zero, and this switching control A multiphase carrier system is used for PWM control of two multilevel PWM inverters 12 and 13 connected in parallel provided in the circuit 19 ', and the switching phase between the parallel multilevel PWM inverters Constitute a control means cancel the current ripple by shifting the phase between the majority carrier with shifting.

  The current amplifier 10 has the same configuration, and the Y-axis coil 7 is connected to the output side of two multi-level PWM inverters 12 and 13 connected in parallel via current limiting means 14 to 17, and a current command from the sequencer 20 of the MRI apparatus. A switching control circuit 19 ′ that inputs the value and the current detection value of the current detection means 18 for detecting the output current of the current amplifier 10, and drives and controls the multilevel PWM inverters 12 and 13 so that the difference between the two becomes zero. The multi-phase carrier system is used for PWM control of the two multi-level PWM inverters 12 and 13 connected in parallel provided in the switching control circuit 19 ′, and the switching phase between the parallel multi-level PWM inverters is shifted. And control means for canceling out current ripples by shifting the phase between the multiphase carriers.

  Also, the current amplifier 11 has the same configuration, and the Z-axis coil 8 is connected to the output side of the two multi-level PWM inverters 12 and 13 connected in parallel via the current limiting means 14 to 17, and the current from the sequencer 20 of the MRI apparatus. A switching control circuit 19 ′ that inputs the command value and the current detection value of the current detection means 18 that detects the output current of the current amplifier 10 and controls the multilevel PWM inverters 12 and 13 so that the difference between the two becomes zero. And a multi-phase carrier system for PWM control of the two multi-level PWM inverters 12 and 13 provided in the switching control circuit 19 ′ and connected in parallel, and the switching phase between the parallel multi-level PWM inverters is shifted. And a control means for canceling the current ripple by shifting the phase between the multiphase carriers.

Here, as an example of a PWM control signal generation method when two sets of multi-level carrier type multi-level PWM inverters described in FIG. 3 are connected in parallel, the operation phase between the parallel-connected PWM inverters is 90 degrees. The case of shifting will be described with reference to the operation waveform diagram of FIG.
In FIG. 8, Carrier 1A and Carrier 1B shown in (a) are carrier triangular waves of one multilevel PWM inverter connected in parallel, which have a phase difference of 180 degrees, and Carrier 2A and Carrier 2B are the other connected in parallel. These are the carrier triangular waves of the multilevel PWM inverter, which have a phase difference of 180 degrees, and Carrier 1A and Carrier 2A and Carrier 1B and Carrier 2B each have a phase difference of 90 degrees.

Carrier 1A and 1B and 2A and 2B are obtained by comparing each carrier and voltage command (Voltage Command), and PWM 1A and PWM 1B shown in (b) to PWM 1 Upper (PWM 1A shown in (c). AND PWM 1B), PWM 1 Lower (PWM 1A OR PWM 1B), PWM 2A and PWM 2B shown in (b) to PWM 2 Upper (PWM 2A AND PWM 2B) shown in (c), and PWM 2 Lower (PWM 2A OR PWM 2B) is obtained, and switching control of the semiconductor switch of the three-level PWM inverter is performed by these PWM Upper and PWM Lower signals.
As a result, since two sets of three-level inverters are connected in parallel, the output voltage is expressed as the sum of the output voltages of the respective inverters, and the output voltage waveform is expressed in five ways (+ E, E / 2, 0, -E / 2, -E), but in this case as well as in FIG. 3, the output voltage is zero as shown by the solid circle in FIG. 8 (a). Since the operation PWM signal has a minimum pulse width in the vicinity, the relationship between the conduction ratio Duty of the semiconductor switch of the multilevel inverter and the output voltage becomes discontinuous near the zero voltage.

In this way, using the multiphase carrier method for the triangular wave carrier and shifting the operation phase between the multilevel PWM inverters connected in parallel, as in the case of not connecting in parallel in Fig. 1, the output voltage is discontinuous near zero. Sexual problems arise.
Therefore, in the second embodiment of the present invention, the above problem is solved by shifting the operation phases of the multilevel PWM inverters connected in parallel and also shifting the phases of the multiphase carriers.

FIG. 9 is a configuration diagram of a switching control circuit 19 ′ that is a main part of the present invention in the second embodiment of the present invention in which the operation phases of the three-level PWM inverters connected in parallel are shifted and the phases of the multiphase carriers are also shifted. Thus, among the semiconductor switches of the arms of the two multi-level PWM inverters 12 and 13 (see FIGS. 7 and 2) connected in parallel, the semiconductor switches 23 and 24 of the arms 27 and 28 on the output terminal A side are switching-controlled. A circuit is shown, and the semiconductor switches 23 and 24 of the arms 29 and 30 on the output terminal B side are also omitted because they can be controlled by the same configuration.
Note that 23a, 24a and 23b, 24b of the multi-level PWM inverters 12, 13 are circuits for driving the semiconductor switches 23, 24.

  The operation of the second embodiment of the present invention will be described using the switching control circuit 19 'of FIG. 9 and the waveform diagrams of the respective parts of FIG. However, FIG. 10 shows a waveform diagram of one of the parallel-connected multi-level PWM inverters, and the other multi-level PWM inverter operates just by being 180 degrees out of phase with the one multi-level PWM inverter. Are omitted because they are the same.

  In FIG. 9, a switching control circuit 19 ′ is a circuit that generates a plurality of carrier signals during one cycle of the operating frequency of the multilevel PWM inverter to generate a PWM control signal. The current command value output from the MRI sequencer 20 is input, and control is performed so that the difference between the current command value and the detected value by the current detecting means 18 for detecting the gradient coil current as the load current becomes zero. Current control unit 41 for outputting a current control signal, gates of upper semiconductor switches 23 of arms 27 and 28 of multilevel PWM inverter 12 and lower semiconductor switches 24 of arms 27 and 28 of multilevel PWM inverter 12 A first gate signal generation circuit 42 for generating a signal, an upper semiconductor switch 23 of the arms 27 and 28 of the multilevel PWM inverter 13, and the multilevel PWM inverter 13 A second gate signal generating circuit 43 for generating the gate signal of the lower semiconductor switch 24 and the first phase shift unit for shifting the operation phases of the multilevel PWM inverters 12 and 13 connected in parallel. It consists of 44.

  The first gate signal generation circuit 42 is a circuit that generates a signal for switching driving the semiconductor switch of the three-level PWM inverter 12, and the triangular wave carrier signal Carrier shown in FIG. 1A is input to the comparison unit 42b, the Carrier 1A is input to the second phase shift unit 42a, delayed by 90 degrees from the Carrier 1A, and the delayed signal Carrier 1B is input to the comparison unit 42c.

  These Carrier 1A and Carrier 1B are compared with the voltage command signal (Voltage Command in FIG. 10 (a)) output from the current control unit 41 by the comparison units 42b and 42c, and the voltage command signal is compared with the Carrier 1A. 10 (b), in which the logic signal “High” is set to “1” during a period longer than that, and the logic signal “Low” is set to “0” during a period when the voltage command signal is less than the Carrier 1A. PWM 1A is output from the comparator 42b, the period when the voltage command signal is larger than the Carrier 1B, the logic signal "High" is "1", the period when the voltage command signal is smaller than the Carrier 1B, PWM 1B shown in FIG. 10 (b) in which the logic signal “Low” is “0” is output from the comparator 42c.

As shown in FIG. 9, the PWM 1A and PWM 1B signals output from the comparison units 42b and 42c are added by the addition unit 42d, and the addition value, the comparison value 1, and the comparison value 0 are compared with the comparison units 42e and 42f. Compare with.
Then, when the added value is larger than the comparison value 1, the PWM 1 Upper signal shown in FIG. 10 (c) that becomes the logic signal “High” is output from the comparison unit 42e, and the added value is greater than the comparison value 0. Is larger, the PWM 1 Lower signal shown in FIG. 10 (c), which becomes the logic signal “High”, is output from the comparison unit 42f.
The thus generated PWM 1 Upper signal is inverted by the signal inverting unit 42g, this signal is amplified by the drive circuit 23a, and the semiconductor switch 23 of the arm 27 is switched and driven, and the PWM 1 Upper signal remains as it is in the drive circuit 23b. And the semiconductor switch 23 of the arm 28 is driven to switch.
On the other hand, the PWM 1 Lower signal is inverted by the signal inverting unit 42h, this signal is amplified by the drive circuit 24a, and the semiconductor switch 24 of the arm 27 is switched and driven. Amplifying and switching driving the semiconductor switch 24 of the arm 28.

  The second gate signal generation circuit 43 is a circuit that generates a signal for switching and driving the semiconductor switch of the three-level PWM inverter 13, and the first phase shift unit converts the carrier wave 1A of the triangular wave generated by the triangular wave generation unit 40. This is delayed by 180 degrees at 44, and the delayed carrier 2A shown in FIG. 10 (a) is used to generate a PWM control signal. The carrier 2A is input to the comparison unit 43b, and this carrier 2A is shifted to the third phase. The signal is input to the unit 43a and delayed by 90 degrees from the Carrier 2A, and the delayed signal Carrier 2B shown in FIG. 10 (a) is input to the comparison unit 43c.

  These Carrier 2A and Carrier 2B are compared with the voltage command signal (Voltage Command in FIG. 10A) output from the current control unit 41 by the comparison units 43b and 43c, and the voltage command signal is compared with the Carrier 2A. 10 (b), in which the logic signal “High” is set to “1” during a period longer than that, and the logic signal “Low” is set to “0” during a period when the voltage command signal is less than the Carrier 2A. PWM 2A is output from the comparison unit 43b, the period when the voltage command signal is larger than the Carrier 2B, the logic signal "High" is "1", the period when the voltage command signal is smaller than the Carrier 2B, PWM 2B shown in FIG. 10 (b) in which the logic signal “Low” is “0” is output from the comparison unit 43c.

The PWM 2 A and PWM 2 B signals output from the comparison units 43b and 43c are added by the addition unit 43d as shown in FIG. 9, and the addition value, the comparison value 1, and the comparison value 0 are compared with each other in the comparison unit 43e. Compare with 43f.
Then, when the added value is larger than the comparison value 1, the PWM 2 Upper signal shown in FIG. 10 (c) that becomes the logic signal “High” is output from the comparison unit 43e, and the added value is compared with the comparison value 0. Is larger, the PWM 2 Lower signal shown in FIG. 10 (c), which becomes the logic signal “High”, is output from the comparison unit 43f.
The PWM 2 Upper signal generated in this way is inverted by the signal inverting unit 43g, this signal is amplified by the drive circuit 23a, and the semiconductor switch 23 of the arm 27 is switched and driven, and the PWM 2 Upper signal remains as it is in the drive circuit 23b. And the semiconductor switch 23 of the arm 28 is driven to switch.
On the other hand, the PWM 2 Lower signal is inverted by the signal inverting unit 43h, this signal is amplified by the drive circuit 24a, and the semiconductor switch 24 of the arm 27 is switched and driven. Amplifying and switching driving the semiconductor switch 24 of the arm 28.

Thus, by delaying Carrier 1B by 90 degrees from Carrier 1A and Carrier 2B by 90 degrees from Carrier 2A, PWM 1 Upper, PWM 1 Lower, PWM 2 as shown by the solid circle in FIG. 10 (a). The minimum pulse width of each signal of Upper and PWM 2 Lower can be kept away from the output voltage near zero.
The amount of movement in the output voltage direction of the minimum pulse width of these PWM 1 Upper, PWM 1 Lower, PWM 2 Upper, and PWM 2 Lower signals varies depending on the phase of Carrier 1B and Carrier 2B. By adjusting the phase of Carrier 2B, the timing of the minimum pulse width can be adjusted arbitrarily, and by setting the phases of Carrier 1B and Carrier 2B to appropriate values, the output voltage is discontinuous near zero. As a result, the relationship between the duty ratio of the semiconductor switch of the multilevel PWM inverter and the output voltage is a continuous characteristic with no dead band.

Also, paying attention to the output voltage waveforms in Fig. 8 (d) and Fig. 10 (d), although the operation PWM signals (PWM 1 Upper, PWM 2 Upper and PWM 1 Lower, PWM 2 Lower) are completely different, Exactly the same waveform is obtained.
Furthermore, since the frequency of the operation PWM signal in FIG. 10 is half that in FIG. 8, in the PWM control according to the second embodiment of the present invention, the switching loss of the semiconductor switch is greatly reduced.
As a result, in order to obtain the same output, a semiconductor switch having a smaller current capacity can be used, so that a power supply device using a multilevel PWM inverter circuit can be made small and inexpensive.

Next, an embodiment of the present invention in the case where a 5-level PWM inverter is used as the multi-level PWM inverter will be described.
FIG. 11 is a circuit diagram of a 5-level PWM inverter.
In FIG. 11, the 5-level PWM inverter is configured to connect DC voltage sources E and E0 to its inputs and output arbitrary voltage waveforms to its output terminals A and B. The semiconductor switches 55, 56, 57, and 58 by MOSFETs and the four arms 63 to 66 in which the diodes 59, 60, 61, and 62 are connected in series are connected in a full bridge.
The diodes 67 to 70 are connected between the connection point of the voltage dividing capacitors 51 and 52 (the potential 3E / 4 of the level 4) and the connection point of the semiconductor switch 55 and the semiconductor switch 56 in each arm 63 to 66 of the full bridge configuration. Diodes 71-74 between the connection point of voltage dividing capacitors 52 and 53 (level 3 potential 2E / 4) and the connection point of semiconductor switch 56 and semiconductor switch 57 in each arm 63-66. Similarly, the diode 75 ~ is connected between the connection point of the voltage dividing capacitors 53 and 54 (potential E / 4 of level 2) and the connection point of the semiconductor switch 57 and the semiconductor switch 58 in each arm 63 ~ 66. 78 is connected.

  Here, by making the semiconductor switches 55 to 58 of the arm 63 conductive, a voltage of + E can be output to the output terminal A, and the semiconductor switches 56 to 58 of the arm 63 and the semiconductor switch 55 of the arm 64 are made conductive. Can output a voltage of + 3E / 4 to the output terminal A. By making the semiconductor switches 57 and 58 of the arm 63 and the semiconductor switches 55 and 56 of the arm 64 conductive, + 2E / 4 (= E / 2) can be output, and by making the semiconductor switch 58 of the arm 63 and the semiconductor switches 55 to 57 of the arm 64 conductive, a voltage of + E / 4 can be output to the output terminal A, Further, by making the semiconductor switches 55 to 58 of the arm 63 conductive, a voltage of 0 can be output to the output terminal A, and in this way, a voltage of 5 levels can be output.

The same applies to the output terminal B. As a result, nine voltages from -E to + E (-E, -3E / 4, -2E / 4, -E / 4) , 0, + E / 4, + 2E / 4, + 3E / 4, + E) can be output.
Furthermore, by controlling these, any voltage can be output between -E and + E, where the ripple of the output current is very small.

  In this way, in the 5-level PWM inverter, the DC voltage source E-E0 is equally divided by the voltage dividing capacitors 51 to 54, and the semiconductor switches 55 to 58 of the arms 63 to 66 are divided in the same manner, and each is a diode. By connecting at 67 to 78, only the DC voltage corresponding to the divided DC voltage is applied to each of the semiconductor switches 63 to 66. Therefore, when the DC voltage E-E0 is the same, the withstand voltage is higher than that of the 3-level PWM inverter. Low semiconductor switches can be used.

  When the gradient magnetic field power supply device is configured by using the 5-level PWM inverter in the multi-level PWM inverter 12 of FIG. 1 (first embodiment) and is controlled by the multi-phase carrier method, the 3-level PWM inverter is changed to the multi-phase PWM inverter. Similar to the case of controlling by the carrier method, the problem of discontinuity near zero of the output voltage occurs as follows.

In the case of a 5-level PWM inverter, as shown in FIG. 12, four carriers of carrier 1A, carrier 1B, carrier 1C, and carrier 1D in FIG. The phases between 1B, Carrier 1C, and Carrier 1D are shifted by 90 degrees, and each carrier is compared with a voltage command.
When the voltage command is larger than each carrier signal, the logic signal “High” is set to “1”, and when the voltage command is smaller than each carrier signal, the logic signal “Low” is set to “0”. The PWM 1A, PWM 1B, PWM 1C, and PWM 1D in FIG. 12 (b) are generated.
The added value of PWM 1A, PWM 1B, PWM 1C, and PWM 1D generated in this way is compared with the comparison value, and PWM 1 Upper (PWM 1A + PWM 1B + PWM 1C + PWM 1D> 3), PWM 1 MID Upper (PWM 1A + PWM 1B + PWM 1C + PWM 1D> 2), PWM 1 MID Lower (PWM 1A + PWM 1B + PWM 1C + PWM 1D> 1), PWM 1 Lower (PWM 1A + PWM 1B + PWM 1C + PWM 1D> 0) is used for switching control of the semiconductor switch of the 5-level inverter.
In the case of FIG. 11, the semiconductor switch 55 of the arm 63 is inverted by the signal obtained by inverting the PWM 1 Upper, the semiconductor switch 55 of the arm 64 by the PWM 1 Upper, and the semiconductor of the arm 63 by the signal obtained by inverting the PWM 1 MID Upper. Switch 56, semiconductor switch 56 of arm 64 with PWM 1 MID Upper, semiconductor switch 57 of arm 63 with a signal obtained by inverting PWM 1 MID Lower, semiconductor switch 57 of arm 64 with PWM 1 MID Lower, Then, switching control of the semiconductor switch 58 of the arm 63 is performed by a signal obtained by inverting the PWM 1 Lower, and switching of the semiconductor switch 58 of the arm 64 is performed by the PWM 1 Lower.

Using this method, PWM 1 Upper, PWM 1 MID Upper, PWM 1 MID Lower, and PWM 1 Lower are limited to the minimum pulse width near the output voltage near zero as shown by the solid circle in Fig. 12 (a). Therefore, the relationship between the conduction ratio Duty of the semiconductor switch of the multilevel inverter and the output voltage becomes discontinuous near zero voltage.
Thus, the problem of discontinuity near zero of the output voltage remains only by using the multiphase carrier method for the 5-level PWM inverter.
Therefore, in the third embodiment of the present invention, a gradient magnetic field power supply device is configured by using the 5-level PWM inverter for the multi-level PWM inverter 12 in FIG. 1 (first embodiment), and this is configured as a multiphase carrier. The above problem is solved by performing PWM control in a system and controlling the phase between the multiphase carriers by shifting.

FIG. 13 is a configuration diagram of the switching control circuit 80 which is the main part of the present invention in the third embodiment of the present invention, and shows the semiconductor switch of each arm of the 5-level PWM inverter circuit 12 (see FIGS. 1 and 11). Among them, a circuit for switching control of the semiconductor switches 55 to 58 of the arms 63 and 64 on the output terminal A side is shown, and the semiconductor switches 55 to 58 of the arms 65 and 66 on the output terminal B side can also be switched with the same configuration. So it is omitted.
Note that 55a, 56a, 57a, 58a and 55b, 56b, 57b, 58b of the 5-level PWM inverter 12 are circuits for driving the semiconductor switches 55-58.

Hereinafter, the operation of the third embodiment according to the present invention will be described with reference to the switching control circuit 80 of FIG. 13 and the waveform diagrams of the respective parts of FIG.
In FIG. 13, the switching control circuit 80 is a circuit that generates a plurality of carrier signals during one cycle of the operating frequency of the multilevel PWM inverter to generate a PWM control signal, and a triangular wave generator 81 that generates a carrier signal; In order to control so that the difference between the current command value output from the MRI sequencer 20 and the detected value by the current detection means 18 for detecting the gradient coil current that is the load current becomes zero. Current control unit 82 for outputting the current control signal, and a first gate signal generation circuit 83 for generating gate signals of semiconductor switches 55 to 58 of multilevel PWM inverter 12.

The first gate signal generation circuit 83 is a circuit that generates a signal for switching and driving the semiconductor switch of the 5-level PWM inverter 12, and the triangular wave carrier signal Carrier shown in FIG. 1A is input to the comparison unit 83a, this Carrier 1A is input to the second phase shift unit 83b, delayed by 90 degrees from the Carrier 1A, and this delayed signal Carrier 1B is input to the comparison unit 83c.
Further, the carrier 1B is input to the third phase shift unit 83d, the signal Carrier 1C delayed by 45 degrees from the carrier 1B is input to the comparison unit 83e, and the carrier 1C is input to the fourth phase shift unit 83f. The signal Carrier 1D input and delayed by 90 degrees from the Carrier 1C is input to the comparison unit 83g.

  These Carrier 1A, Carrier 1B, Carrier 1C, and Carrier 1D are compared with the voltage command signal (Voltage Command in FIG. 14 (a)) output from the current control unit 82 by the comparison units 83a, 83c, 83e, and 83g. When the voltage command signal is larger than Carrier 1A, the logic signal “High” is set to “1”. When the voltage command signal is smaller than Carrier 1A, the logic signal “Low” is set to “0”. 14 (b) is output from the comparison unit 83a. Similarly, during a period when the voltage command signal is larger than the Carrier 1B, the logic signal “High” is set to “1”, and the voltage During the period when the command signal is smaller than the Carrier 1B, the PWM 1B with the logic signal “Low” set to “0” is output from the comparator 83c, and during the period when the voltage command signal is larger than the Carrier 1C, the logic signal When “High” is set to “1” and the voltage command signal is smaller than the carrier 1C, the logic signal “Low” is set to “0”. PWM 1C to be output from the comparison unit 83e, and the period in which the voltage command signal is larger than the Carrier 1D, the logic signal “High” is set to “1”, and the voltage command signal is smaller than the Carrier 1D Outputs from the comparator 83g PWM 1D with the logic signal “Low” set to “0”.

As shown in FIG. 13, the PWM 1A to PWM 1D signals output from the comparison units 83a, 83c, 83e, and 83g are added by the addition unit 83h, and the addition value and the comparison value 3, the comparison value 2 and the comparison value 1 The comparison value 0 is compared by the comparison units 83i, 83j, 83k, and 83l.
Then, when the added value is larger than the comparison value 3, the PWM 1 Upper signal shown in FIG. 14 (c) that becomes the logic signal “High” is output from the comparison unit 83i, and the added value is greater than the comparison value 2. Is greater than the comparison value 1, the PWM 1 MID Lower signal that is the logic signal “High” is output from the comparator 83j. A signal is output from the comparison unit 83k, and when the added value is larger than the comparison value 0, a PWM 1 Lower signal that is a logic signal “High” is output from the comparison unit 83l.

The thus generated PWM 1 Upper signal is inverted by the signal inverting unit 83m, this signal is amplified by the drive circuit 55a, and the semiconductor switch 55 of the arm 63 is switched and driven, and the PWM 1 Upper signal remains as it is as the drive circuit 55b. The semiconductor switch 55 of the arm 64 is switched and amplified.
The PWM 1 MID Upper signal is inverted by the signal inverting unit 83n, and this signal is amplified by the drive circuit 56a to switch the semiconductor switch 56 of the arm 63, and the PWM 1 MID Upper signal is amplified by the drive circuit 56b as it is. Then, the semiconductor switch 56 of the arm 64 is driven to be switched.
Similarly, the PWM 1 MID Lower signal is inverted by the signal inverting unit 83o, and this signal is amplified by the drive circuit 57a to drive the semiconductor switch 57 of the arm 63, and the PWM 1 MID Lower signal remains as it is as the drive circuit 57b. The semiconductor switch 57 of the arm 64 is switched and amplified.
The PWM 1 Lower signal is inverted by the signal inverting unit 83p, and this signal is amplified by the drive circuit 58a to drive the semiconductor switch 58 of the arm 63, and the PWM 1 Lower signal is amplified by the drive circuit 58b as it is. Then, the semiconductor switch 58 of the arm 64 is switched and driven.

In this way, by delaying Carrier 1B by 90 degrees from Carrier 1A, Carrier 1C by 45 degrees from Carrier 1B, and Carrier 1D by 90 degrees from Carrier 1C, PWM 1 Upper, PWM 1 MID Upper, PWM 1 MID Lower The minimum pulse width of the PWM 1 Lower signal can be kept away from near zero of the output voltage.
The amount of movement in the output voltage direction of the minimum pulse width of these PWM 1 Upper, PWM 1 MID Upper, PWM 1 MID Lower, and PWM 1 Lower signals varies depending on the phase of Carrier 1B, Carrier 1C, and Carrier 1D. The timing of the minimum pulse width can be arbitrarily adjusted by adjusting the phase of these carrier signals.
Therefore, the discontinuity of the output voltage near zero is improved by setting the phase of the Carrier signal to an appropriate value, and the relationship between the conduction ratio Duty of the semiconductor switch of the multilevel PWM inverter and the output voltage is a dead band. There will be no continuous characteristics.
FIG. 15 and FIG. 16 are block diagrams of a 5-level PWM inverter connected in parallel in both, and are connected by (a), (b), and (c).

Next, a 5-level PWM inverter is used for the multi-level PWM inverters 12 and 13 of the second embodiment of the present invention shown in FIG. 7, and the operation phases of the multi-level PWM inverters connected in parallel are shifted and the multi-phase carrier A fourth embodiment of the present invention that also shifts the phase will be described.
FIGS. 15 and 16 are configuration diagrams of a switching control circuit 80 ′ which is a main part of the present invention in the fourth embodiment of the present invention, and show the five-level PWM inverter circuits 12 and 13 (see FIGS. 7 and 11). Of the semiconductor switches of each arm, a circuit for switching control of the semiconductor switches 55 to 58 of the arms 63 and 64 on the output terminal A side is shown, and the semiconductor switches 55 to 58 of the arms 65 and 66 on the output terminal B side are the same. Since switching control is possible with this configuration, it is omitted.
Note that 55a, 56a, 57a, 58a and 55b, 56b, 57b, 58b of the 5-level PWM inverters 12, 13 are circuits for driving the semiconductor switches 55-58.

  15 and 16, the switching control circuit 80 ′ is a circuit that generates a plurality of carrier signals in one cycle of the operating frequency of the multilevel PWM inverter to generate a PWM control signal, and generates a triangular wave that generates a carrier signal. The difference between the current command value and the detection value by the current detection means 18 for detecting the gradient magnetic field coil current that is the load current is zeroed by inputting the current command value output from the unit 81 and the sequencer 20 of the MRI apparatus. A current control unit 82 that outputs a current control signal for controlling to be, a first gate signal generation circuit 83 that generates gate signals of the semiconductor switch MOSFETs 55 to 58 of the arms 63 and 64 of the 5-level PWM inverter 12, and The second gate signal generation circuit 84 for generating the gate signals of the semiconductor switches MOSFET 55 to 58 of the arms 63 and 64 of the 5-level PWM inverter 13 and the operations of the parallel-connected 5-level PWM inverters 12 and 13 Constituted by the first phase shifter 85 for shifting the phase.

  The first gate signal generation circuit 83 is a circuit that generates a signal for switching and driving the semiconductor switch of the 5-level PWM inverter 12, and the triangular wave carrier signal 1A ′ generated by the triangular wave generation unit 81 (FIG. 14 (a)). The same carrier signal 1A) is input to the comparison unit 83a, and this carrier signal 1A ′ is input to the second phase shift unit 83b and delayed by 90 degrees from the carrier signal 1A ′, and this delayed carrier signal 1B ′ ( The same as the carrier signal 1B in FIG. 14 (a) is input to the comparison unit 83c, and the carrier signal 1B ′ is input to the third phase shift unit 83d to be delayed by 45 degrees from the carrier signal 1B ′. The carrier signal 1C ′ (same as the carrier signal 1C in FIG. 14 (a)) is input to the comparison unit 83e, and the carrier signal 1C ′ is input to the fourth phase shift unit 83f to input the carrier signal 1C ′ to 90C. This carrier signal 1D ′ (see FIG. To enter the same) and the signal 1D to the comparison unit 83 g.

  These carrier signals 1A ′, 1B ′, 1C ′, 1D ′ are compared with the voltage command signal output from the current control unit 82 by the comparison units 83a, 83c, 83e, 83g, and the voltage command signal is PWM 1A in which the logic signal “High” is set to “1” during a period longer than the carrier 1A ′, and the logic signal “Low” is set to “0” during a period in which the voltage command signal is less than the carrier signal 1A ′. 'Signal (same as PWM 1A in Fig. 14 (b)) is output from the comparison unit 83a, and during the period when the voltage command signal is larger than the carrier signal 1B', the logic signal "High" is set to "1", During the period when the voltage command signal is smaller than the carrier signal 1B ′, the PWM 1B ′ signal (same as PWM 1B in FIG. 14 (b)) that sets the logic signal “Low” to “0” is output from the comparator 83c. In the period when the voltage command signal is larger than the carrier signal 1C ′, the logic signal “High” is set to “1”, and the voltage command signal is During a period smaller than the carrier signal 1C ′, the PWM 1C ′ signal (same as PWM 1C in FIG. 14 (b)) with the logic signal “Low” being “0” is output from the comparison unit 83e, and the voltage command When the signal is larger than the carrier signal 1D ′, the logic signal “High” is set to “1”. When the voltage command signal is smaller than the carrier signal 1D ′, the logic signal “Low” is set to “0”. The PWM 1D ′ signal (same as PWM 1D in FIG. 14B) is output from the comparison unit 83g.

The PWM 1A ′, PWM 1B ′, PWM 1C ′, and PWM 1D ′ output from the comparison units 83a, 83c, 83e, and 83f are added by the addition unit 83h, as shown in FIGS. The comparison unit 83i, 83j, 83k, 83l compares the addition value with the comparison value 3, the comparison value 2, the comparison value 1, and the comparison value 0.
When the added value is larger than the comparison value 3, the PWM 1 Upper 'signal that is the logic signal “High” (same as PWM 1 Upper in FIG. 14 (c)) is output from the comparator 83i, and When the addition value is larger than the comparison value 2, the PWM 1 MID Upper 'signal (same as PWM 1 MID Upper in FIG. 14 (c)) that becomes the logic signal “High” is output from the comparison unit 83j, and the addition When the value is larger than the comparison value 1, a PWM 1 MID Lower 'signal (same as PWM 1 MID Lower in FIG. 14 (c)) that becomes the logic signal “High” is output from the comparison unit 83k, and the added value Is greater than the comparison value 0, the PWM 1 Lower ′ signal (same as PWM 1 Lower in FIG. 14C) that is the logic signal “High” is output from the comparison unit 83l.

The thus generated PWM 1 Upper 'signal is inverted by the signal inverting unit 83m, this signal is amplified by the drive circuit 55a, and the semiconductor switch 55 of the arm 63 is switched and the PWM 1 Upper' signal is driven as it is. The semiconductor switch 55 of the arm 64 is switched and amplified by the circuit 55b.
The PWM 1 MID Upper 'signal is inverted by the signal inverting unit 83n, and this signal is amplified by the drive circuit 56a to switch the semiconductor switch 56 of the arm 63. The PWM 1 MID Upper' signal is directly output by the drive circuit 56b. The semiconductor switch 56 of the arm 64 is amplified and switched.
Similarly, the PWM 1 MID Lower 'signal is inverted by the signal inverting unit 83o, this signal is amplified by the drive circuit 57a, and the semiconductor switch 57 of the arm 63 is switched and the PWM 1 MID Lower' signal is driven as it is. Amplifying by the circuit 57b, the semiconductor switch 57 of the arm 64 is driven to be switched.
Then, the PWM 1 Lower 'signal is inverted by the signal inverting unit 83p, and this signal is amplified by the drive circuit 58a to drive the semiconductor switch 58 of the arm 63, and the PWM 1 Lower' signal is directly used by the drive circuit 58b. The semiconductor switch 58 of the arm 64 is switched and driven to be amplified.

The second gate signal generation circuit 84 for generating the gate signals of the semiconductor switch MOSFETs 55 to 58 of the arms 63 and 64 of the five-level PWM inverter 13 has an operation phase difference between the multi-level PWM inverters 12 and 13 connected in parallel. In order to obtain 180 degrees, a carrier signal 2A ′ delayed by 180 degrees from the carrier signal 1A ′ output from the triangular wave generation unit 81 is generated by the first phase shift unit 85, and the carrier signal 2A ′ is generated as a comparison unit. Enter in 84a.
Then, the carrier signal 2A ′ is input to the fifth phase shift unit 84b and delayed by 90 degrees from the carrier signal 2A ′, and this delayed carrier signal 2B ′ (not shown) is input to the comparison unit 84c, and the carrier signal The signal 2B ′ is input to the sixth phase shift unit 84d and delayed by 45 degrees from the carrier signal 2B ′, the delayed carrier signal 2C ′ (not shown) is input to the comparison unit 84e, and the carrier signal 2C ′ Is input to the seventh phase shift unit 84f and delayed by 90 degrees from the carrier signal 2C ′, and this delayed carrier signal 2D ′ (not shown) is input to the comparison unit 84g.

  These carrier signals 2A ′, 2B ′, 2C ′, 2D ′ are compared with the voltage command signal output from the current control unit 82 by the comparison units 84a, 84c, 84e, 84g, and the voltage command signal is PWM 2A in which the logical signal “High” is set to “1” during a period longer than the carrier 2A ′, and the logical signal “Low” is set to “0” during the period in which the voltage command signal is smaller than the carrier signal 2A ′. 'A signal (not shown) is output from the comparison unit 84a, and during a period when the voltage command signal is larger than the carrier signal 2B', the logic signal “High” is set to “1”, and the voltage command signal is set to the carrier signal 1B. The period smaller than 'is output from the comparator 84c a PWM 2B' signal (not shown) that sets the logic signal "Low" to "0", and the period when the voltage command signal is larger than the carrier 2C ' The logic signal “High” is set to “1”, and the voltage command signal is more than the carrier signal 2C ′. During the period, a PWM 2C ′ signal (not shown) in which the logic signal “Low” is set to “0” is output from the comparator 84e, and a period in which the voltage command signal is greater than the carrier signal 2D ′ During the period when the signal “High” is “1” and the voltage command signal is smaller than the carrier signal 2D ′, the PWM 2D ′ signal (not shown) whose logic signal “Low” is “0” is compared with the comparator 84g Output more.

The PWM 2A ′, PWM 2B ′, PWM 2C ′, and PWM 2D ′ output from the comparison units 84a, 84c, 84e, and 84f are added by the addition unit 84h, as shown in FIGS. The comparison unit 84i, 84j, 84k, 84l compares the addition value with the comparison value 3, the comparison value 2, the comparison value 1, and the comparison value 0.
When the added value is larger than the comparison value 3, a PWM 2 Upper 'signal (not shown) that becomes a logic signal “High” is output from the comparison unit 84i, and the added value is larger than the comparison value 2. Output a PWM 2 MID Upper 'signal (not shown) that becomes a logic signal “High” from the comparator 84j, and when the added value is larger than the comparison value 1, the PWM that becomes a logic signal “High” 2 MID Lower 'signal (not shown) is output from the comparison unit 84k, and when the added value is larger than the comparison value 0, the PWM 2 Lower' signal (not shown) that becomes the logic signal "High" Output from the unit 84l.

The thus generated PWM 2 Upper 'signal is inverted by the signal inverting unit 84m, this signal is amplified by the drive circuit 55a, and the semiconductor switch 55 of the arm 63 is switched and the PWM 2 Upper' signal is driven as it is. The semiconductor switch 55 of the arm 64 is switched and amplified by the circuit 55b.
The PWM 2 MID Upper 'signal is inverted by the signal inverting unit 84n, and this signal is amplified by the drive circuit 56a to drive the semiconductor switch 56 of the arm 63, and the PWM 2 MID Upper' signal is directly applied to the drive circuit 56b. The semiconductor switch 56 of the arm 64 is amplified and switched.
Similarly, the PWM 2 MID Lower 'signal is inverted by the signal inverting unit 84o, and this signal is amplified by the drive circuit 57a to drive the semiconductor switch 57 of the arm 63, and the PWM 2 MID Lower' signal is driven as it is. Amplifying by the circuit 57b, the semiconductor switch 57 of the arm 64 is driven to be switched.
Then, the PWM 2 Lower 'signal is inverted by the signal inverting unit 84p, and this signal is amplified by the drive circuit 58a to drive the semiconductor switch 58 of the arm 63, and the PWM 2 Lower' signal is directly applied to the drive circuit 58b. The semiconductor switch 58 of the arm 64 is switched and driven to be amplified.

In this way, by shifting the operation phase of the 5-level PWM inverters connected in parallel by 180 degrees and controlling the phase of the majority carrier signals of the respective 5-level PWM inverters, In addition to the ripple reduction effect of the current flowing through the load due to the cancellation of the output current ripple, the operation PWM control signals (PWM 1 Upper ', PWM 1 MID Upper', PWM 1 MID Lower ', PWM 1 Lower 'and PWM 2 Upper', PWM 2 MID Upper ', PWM 2 MID Lower', and PWM 2 Lower 'signals) can be kept away from the output voltage near zero. Discontinuity is improved, and the relationship between the conduction ratio Duty of the semiconductor switch of the multilevel inverter and the output voltage is a continuous characteristic with no dead band.
Also, since the frequency of the operating PWM signal is lowered, the switching loss of the semiconductor switch is greatly reduced, and a semiconductor switch with a smaller current capacity can be used to obtain the same output, so a multi-level PWM inverter circuit was used. The power supply device can be made small and inexpensive.

In the above-described embodiment, the MOSFET is used for the semiconductor switch. However, the present invention is not limited to this, and if a semiconductor switch such as an IGBT (Insulated Gate Bipolar Transistor) or a bipolar transistor is used depending on the application. good.
Further, a triangular wave serving as a reference is generated from a triangular wave generating unit in the multiphase carrier generating means for generating a multiphase carrier in the above-described embodiment and the carrier phase shift means for shifting the phase of the multiphase carrier, and the triangular wave and the triangular wave Although the configuration example using the means for shifting the phase of the triangular wave is used, the present invention is not limited to this, and a configuration in which a multiphase carrier wave is generated from the triangular wave generator and the phase of these multiphase carrier waves is shifted. But it ’s okay.
Furthermore, although examples of 3 level and 5 level multi-level PWM inverter circuits have been given, the present invention is not limited thereto, and the multi-level PWM inverter is an n-level PWM inverter, and the phase shift electrical angle of the multi-phase carrier If it is set appropriately, it can be applied to multi-level PWM inverters with 5 levels or more.
Furthermore, although an MRI apparatus in which a gradient magnetic field coil is connected as a load has been described, a coil that generates a static magnetic field or a high-frequency magnetic field can be connected and used as a load.
Furthermore, although an example in which the switching control circuits 19, 19 ′, 80, and 80 ′ for generating the operation PWM control signal are configured by hardware is used, this is a hardware configuration such as a combination of a digital signal processor and a microcomputer. It is also possible to use a method of generating an operation PWM control signal by software using hardware.

1 is a block diagram showing a gradient magnetic field power supply device of an MRI apparatus using a power supply device using a three-level PWM inverter according to a first embodiment of the present invention. A circuit diagram of a 3-level PWM inverter. The operation explanatory diagram of the three-level PWM inverter by the polyphase carrier system. The figure which shows the relationship between the conduction ratio of the semiconductor switch in a 3 level PWM inverter, and an output voltage. FIG. 2 is a configuration diagram of a switching control circuit in the first embodiment of the present invention in which the phases of the multiphase carriers of the three-level PWM inverter are shifted. FIG. 6 is a waveform diagram of each part of the switching control circuit of FIG. The block block diagram which shows the gradient magnetic field power supply device of the MRI apparatus using the power supply device by the parallel connection 3 level PWM inverter which is the 2nd Embodiment of this invention. Explanatory drawing of the PWM control signal generation method at the time of connecting two sets of 3 phase PWM inverters of a polyphase carrier system in parallel. The switching control circuit block diagram in the 2nd Embodiment of this invention which shifted the operation | movement phase of 3 level PWM inverters connected in parallel, and shifted the phase of the multiphase carrier. FIG. 10 is a waveform diagram of each part of the switching control circuit of FIG. A circuit diagram of a 5-level PWM inverter. Operation diagram when using multi-phase carrier method for 5-level PWM inverter. The switching control circuit block diagram in the 3rd Embodiment of this invention which shifted the phase of the multiphase carrier of a 5-level PWM inverter. FIG. 14 is a waveform diagram of each part of the switching control circuit of FIG. The switching control circuit block diagram in the 4th Embodiment of this invention which shifted the operation | movement phase of 5-level PWM inverters connected in parallel, and also shifted the phase of the multiphase carrier. The switching control circuit block diagram in the 4th Embodiment of this invention which shifted the operation | movement phase of 5-level PWM inverters connected in parallel, and also shifted the phase of the multiphase carrier.

Explanation of symbols

  1 Gradient magnetic field coil, 2 Gradient magnetic field power supply, 6 X-axis coil, 7 Y-axis coil, 8 Z-axis coil, 9-11 Current amplifier, 12, 13 Multi-level PWM inverter, 18 Current detection means, 19, 19 '3 Level PWM inverter switching control circuit, 20 MRI device sequencer, 23, 24 3-level PWM inverter semiconductor switch, 40 triangular wave generator, 41 current controller, 42 3-level PWM inverter first gate signal generator, 42a 2nd phase shift unit, 42b, 42c comparison unit, 42d addition unit, 42e, 42f comparison unit, 43 3rd level PWM inverter second gate signal generation circuit, 43a 3rd phase shift unit, 43b, 43c comparison unit , 43d addition unit, 43e, 43f comparison unit, 44 first phase shift unit, 55-58 5 level PWM inverter semiconductor switch, 80, 80 '5 level PWM inverter switching control circuit, 81 triangular wave generation unit, 82 current Control unit, 83 5 level The first gate signal generation circuit of the PWM inverter, the second gate signal generation circuit of the 84 5-level PWM inverter, the first phase shift unit of the 85 second gate signal generation circuit

Claims (5)

  Pulse width modulation control multi-level inverter, current detection means for detecting the output current to the load of this multi-level inverter, and control for controlling the difference between the value detected by this current detection means and the current command value to be zero And a switching control unit that drives and controls the multilevel inverter by a signal. The switching control unit shifts the phase of the multiphase carrier wave from the multiphase carrier wave generation unit that generates a multiphase carrier wave. A carrier phase shift means; and a drive signal generation means for driving and controlling the multilevel inverter based on the carrier wave generated by the multiphase carrier wave generation means and the carrier wave phase shift means and the control signal. Power supply.   2. The multiphase carrier generation means and the carrier phase shift means according to claim 1, wherein the multiphase carrier generation means and the carrier phase shift means are means for generating a reference carrier and a carrier having a predetermined phase shifted from the carrier. A first comparison means for comparing the control signal with a reference carrier wave and the carrier wave whose phase is shifted; an output means for adding the output of the first comparison means; an output of the addition means; and a plurality of reference comparison values; And a second comparison means for comparing the two.   3. The parallel inverter phase according to claim 1, wherein the multi-level inverter is a plurality of parallel-connected pulse-width modulation control multi-level inverters of the same level number, wherein the switching phase between the plurality of multi-level inverters is shifted. A power supply apparatus further comprising shift means.   Width modulation control multi-level inverter, current detection means for detecting the output current to the load of this multi-level inverter, and control signal for controlling the difference between the detected value by this current detection means and the current command value to be zero 3. A magnetic resonance imaging apparatus having a power supply device including a switching control unit that drives and controls the multi-level inverter according to claim 1, wherein the load is a magnetic field generating coil, and the power supply device has any one of claims 1 and 2. A magnetic resonance imaging apparatus using the power supply device according to the item.   A plurality of parallel-connected pulse width modulation control multilevel inverters of the same level number, current detection means for detecting an output current to the load of the multilevel inverter, and a detection value and a current command value by the current detection means A magnetic resonance imaging apparatus having a power supply device including a switching control means for driving and controlling the multilevel inverter by a control signal for controlling the difference to be zero, wherein the load is a magnetic field generating coil, and the power supply A magnetic resonance imaging apparatus using the power supply apparatus according to claim 3 as the apparatus.

Images