JP2007004338A - Data processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve accessibility to a data memory. <P>SOLUTION: A computing part 20 is provided with a plurality of computing cells 26 performing operation, and their logic functions are defined based on configuration information. A data memory 21 having a plurality of access ports performing parallel operation holds computing data. In a memory control circuit 22 controlling access by a corresponding data memory, a control form is defined according to the configuration information. An external interface part 23 is connected to the memory control circuit. A crossbar switch part 24 connects the computing part and the memory control circuit together, and the connection form is defined according to the configuration information. The memory control circuit receives a first access request from the external interface part to the data memory and a second access request from the computing cell to the data memory, and an access response control procedure for answering to the first and second access requests is varied according to the configuration information. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a data processing device, and more particularly, to a data processing device in which the logic function of a plurality of operation cells and the connection to a data memory can be switched in a programmable manner, for example, a technique effective when applied to a flexible processor. .

  Mobile information devices with built-in multimedia processing functions such as images and audio, and wired and wireless communication functions have come to be widely used, and in order to provide these devices in a small and inexpensive manner, There is a demand for higher performance, higher functionality, and lower power consumption. On the other hand, the rapid response to various standards and standards established along with the advancement of technology development greatly affects the product value. Therefore, it is possible to easily change or add functions by software after device manufacture. In addition to shortening the development period, it is necessary to extend the product life.

  As a first means to realize the above data processing device, a dedicated logic circuit capable of only limited function changes prepared in advance such as a plurality of operation modes is designed, and a dedicated LSI combining them is mounted. There is a way to do it. This dedicated LSI is generally considered to be the best implementation method in terms of achieving high performance and low power consumption, but not only can the functions be changed and added without redesign of the dedicated LSI. Because of the long development period required for design, it is difficult to select it as an implementation means.

  As a second means, there is a method in which a general-purpose microprocessor is mounted and various processes are realized by software comprising a series of instruction sequences executed on the processor. In this case, by modifying or adding software, it is possible to realize high functionality and change and add functions without changing the hardware of the data processing device. However, even a state-of-the-art microprocessor can execute at most several instructions at the same time, and a data processing device based on sequential processing of instructions operates at an extremely high clock frequency. A processor must be installed, and power consumption increases. Furthermore, in order to extract the processing performance of the processor, control logic other than computation such as branch prediction is required, and the logic scale of the arithmetic unit main body is relatively reduced, so that the processing efficiency with respect to the hardware scale is reduced. It is done.

  In recent years, a reconfigurable LSI called Field Programmable Gate Array (FPGA) has attracted attention as a practical means equivalent to the middle of these two means, and its application range is gradually expanding. The FPGA has an internal configuration in which a number of Lookup Tables (LUTs) are connected by a bus that can be rerouted, and reads configuration information that defines the operation contents of the LUT and the connection between the LUTs from a memory externally attached to the LSI. As a result, an arbitrary function can be realized in the LSI. Basically, the operation contents of LUTs and the connection between LUTs can be set in 1-bit units, so it is highly flexible when implementing predetermined functions on LSIs, but multi-bit operations such as image / sound processing There is a problem that the area overhead is large in the application field mainly composed of.

  In view of such a technical background, a flexible processor technology that includes an arithmetic unit having a coarse-grained arithmetic unit of about 8 to 32 bits in width and aims at balancing arithmetic performance and flexibility at a high level is known. For example, it is described in the following Patent Documents 1 and 2. The above-mentioned FPGA arranges logic gates such as NAND and NOR circuits in an array and switches the connection wiring. On the other hand, this flexible processor technology arranges arithmetic units instead of logic gates in an array. Therefore, the function of the arithmetic unit and the wiring between the arithmetic units are switched.

JP 2001-314881 A JP 2004-40188 A

  The inventor examined data processing performance using a flexible processor. According to this, in order to operate a plurality of arithmetic units in parallel, the number of operands required at one time increases, and the plurality of arithmetic units must frequently perform load / store processing with the data memory. I must. At the same time, it is necessary to frequently perform a transfer process for storing calculation target data from the outside in the data memory and a process for transferring calculation result data from the data memory to the outside. It is effective to use a plurality of multi-port data memories for such a request. However, the chip area occupied by the data memory doubles in proportion to the number of ports that can be accessed in parallel. For this reason, the number of ports of the multi-port data memory is naturally limited.

  An object of the present invention is to provide a data processing apparatus that can alleviate the influence of the limitation on the number of ports for a data memory having multiple ports on the data processing performance.

  Another object of the present invention is to provide a data processing semiconductor device having a data memory having a multiport and having a high index of area versus processing performance.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  [1] A data processing device (11) according to the present invention includes an arithmetic unit (20), a plurality of data memories (21), a plurality of memory control circuits (22), an external interface unit (23), and a crossbar switch unit (24 ) And a control unit (25). The calculation unit includes a plurality of calculation cells (26) for executing calculations, and their logical functions are defined based on the configuration information. The data memory has a plurality of access ports (RAMPRT0, RAMPRT1) that can operate in parallel, and holds operation data. The memory control circuit controls access to the corresponding data memory, and the control form is defined based on the configuration information. The external interface unit is connected to the memory control circuit. The crossbar switch unit connects the arithmetic unit and the memory control circuit, and the connection form is defined based on configuration information (FECFG). The control unit performs control to transfer the configuration information to the arithmetic cell, the memory control circuit, and the crossbar switch unit, and controls the state transition thereof. The memory control circuit is capable of accepting a first access request from the external interface unit to the data memory and a second access request from the operation cell to the data memory. The access response control procedure for responding to the access request can be changed based on the configuration information.

  The arithmetic unit can reconfigure the logic function dynamically according to the configuration information. When performing necessary data transfer before and after the arithmetic processing by the reconfigured logic function, the memory control circuit stores the arithmetic data from the outside in the data memory, supplies the arithmetic data to the arithmetic unit, and the arithmetic result by the arithmetic unit Is stored in the data memory, and the stored calculation result is output to the outside. Thereby, highly flexible data transfer is realized in a data processing device such as a flexible processor.

  As described above, a plurality of data memories having multi-ports can be accessed from the external interface unit or the arithmetic cell through the memory control circuit. It is not necessary to assign a dedicated port to connect the data memory to the external interface unit. The multiport of the data memory can be used for both the first access from the external interface unit and the second access from the operation cell. Thereby, it is possible to allocate an empty port in the load / store processing between the arithmetic unit and the data memory to transfer between the outside and the data memory. Similarly, it is possible to allocate free ports in the transfer process for storing operation target data to the data memory from the outside and the process for transferring operation result data from the data memory to the outside for the transfer between the arithmetic unit and the data memory. Become. Therefore, it is possible to improve the data transfer performance between the arithmetic unit, the data memory, and the external interface unit without increasing the number of data memory ports.

  Furthermore, since the access response control procedure for responding to the first access request and the second access request can be dynamically changed based on the configuration information, depending on the calculation processing contents and calculation processing status in the calculation unit In order to maximize the data transfer rate to and from the data memory, the degree of freedom to prioritize the access of the data memory to specific processing is further increased, thereby improving the data processing performance in the arithmetic unit. Is possible.

  As one specific form of the present invention, the memory control circuit can perform first to fourth control as the variable access response control procedure. The first control is control that accepts a first access request and uses one access port of the data memory. The second control is a control that accepts a second access request and uses one access port of the data memory. The third control is a control that accepts different second access requests in parallel and uses different access ports. The fourth control is a control that accepts the first access request and uses one access port of the data memory, and accepts the second access request and uses the other access port of the data memory.

  As a more specific form of the present invention, the memory control circuit may employ the following control in addition to the above.

  First, the memory control circuit may use the first access when all access ports are used in response to the second access request as the variable access response control procedure for the corresponding data memory. It is possible to control to return a busy state to the external interface unit in response to the request. By returning a busy state, the recipient recognizes that the first access request has been rejected. As a result, the receiving side in the busy state can respond immediately by inserting a wait or changing processing scheduling.

  Second, the memory control circuit may use the first access when all access ports are used in response to the second access request as the variable access response control procedure for the corresponding data memory. It is possible to control to return a busy state to the request source of one second access request in response to the request. By returning the busy state, the computation cell which is the receiving side recognizes that the second access request has been rejected. As a result, the busy side can respond by inserting waits or changing processing scheduling.

  At this time, the memory control circuit selects a second access request source that returns a busy state according to the priority of the access port, and is busy with an access request source connected to an access port with a lower priority. You may control to return. As a result, the configuration information can be defined to use an access port with a high priority for data processing with a high priority, so that the data processing with a high priority is obstructed by the first access request. Can be suppressed.

  Further, at this time, the priority of the access port in the memory control circuit may be made variable according to the configuration information. The degree of freedom of control increases.

  Thirdly, when the first access request and the second access request compete, the memory control circuit performs control to preferentially accept the access request having a higher priority. Depending on the content of the data processing by the computation cell and the progress of the computation, it may be more convenient to prioritize the first access request, or vice versa. Considering this, it is possible to contribute to the improvement of the data processing performance depending on the setting of the priority.

  At this time, the priority of the first access request and the second access request may be set separately for each access port in the memory control circuit. Furthermore, finer priority control can be performed.

  Further, at this time, the priority of the first access request and the second access request in the memory control circuit may be made variable according to the configuration information.

  [2] The data processor (2) according to the present invention includes a flexible processor (11), a CPU (12), and a RAM (13) connected to the internal bus (10). The flexible processor includes an arithmetic unit, a plurality of data memories, a plurality of memory control circuits, an external interface unit, a crossbar switch unit, and a control unit. The calculation unit includes a plurality of calculation cells for executing calculations, and their logical functions are defined based on the configuration information. The data memory has a plurality of access ports capable of operating in parallel and holds operation data. The memory control circuit controls access to the corresponding data memory, and the control form is defined based on the configuration information. The external interface unit is connected to the memory control circuit. The crossbar switch unit connects the arithmetic unit and the memory control circuit, and the connection form is defined based on the configuration information. The control unit controls to transfer the configuration information to the arithmetic cell, the memory control circuit, and the crossbar switch unit, and controls the state transition thereof. The memory control circuit is capable of accepting a first access request from the external interface unit to the data memory and a second access request from the operation cell to the data memory. The access response control procedure for responding to the access request can be changed based on the configuration information. The external interface unit is connected to the internal bus. The CPU can execute a program stored in the RAM and transfer data held in the RAM from the external interface unit to the data memory. The CPU can transfer operation result data by the flexible processor held in the data memory from the external interface unit to the RAM.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the accompanying drawings. Although not particularly limited, a circuit element constituting a flexible data processor shown as one embodiment is a single element such as single crystal silicon by a known semiconductor integrated circuit technology such as a CMOS (complementary MOS transistor) or a bipolar transistor. It is formed on a single semiconductor substrate.

  FIG. 2 shows an example of a data processing system. The data processing system includes a flexible data processor (FDP) 2, a host processor (HCPU) 3, a main memory (MMRY) 4, and a main ROM (MROM) 5 connected to the system bus 1. A local ROM (LROM) 6 is connected to the flexible data processor (FDP) 2.

  The flexible data processor (FDP) 2 includes a flexible processor kernel (FPK) 11, a sub CPU (SCPU) 12, an internal RAM (IRAM) 13, and a shared buffer (SBUF) 14 that are commonly connected to the internal bus 10. The flexible data processor 2 is positioned as an accelerator with respect to the host processor 3. In the flexible processor 2, logical functions specialized for specific processing such as sound processing, image processing, protocol processing, and the like are set programmably by the configuration information (FECFG). The processing order for the set logical functions is controlled by sequence information (FESQC). The configuration information (FECFG) and sequence information (FESQC) are held in the local ROM 6. Access control to the local ROM 6 is performed by the sub CPU 12. The sub CPU 12 acquires the configuration information (FECFG) and sequence information (FESQC) from the local ROM 6 according to the control program loaded in the internal RAM 13, and supplies the acquired information to the flexible processor kernel 11 according to a predetermined timing. As a result, the flexible processor kernel 11 performs data processing based on the logical function specified by the configuration information (FECFG). Arithmetic data necessary for data processing is internally transferred from the internal RAM 13 or the shared buffer 14 to the flexible processor kernel 11 by the sub CPU 12. The flexible processor kernel 11 performs data processing using the calculation data. The sub CPU 12 extracts the data processing result from the flexible processor kernel 11 at a predetermined timing and transfers it to the internal RAM 13 or the shared buffer 14. The flexible processor kernel 11 can also input / output operation data via an external input / output circuit (EXTIO). The sub CPU 12 can directly interface with the system bus 1 via a port or the like.

  A flexible data processor (FDP) 2 interfaces with the system bus 1 via a shared buffer 14 having dual ports. The shared buffer 14 is shared by the sub CPU 12 and the host processor 3, and the sub CPU 12 and the host processor 3 exchange data, programs, and the like via the shared buffer 14.

  The host processor 3 initially loads the operation program of the sub CPU 12 from the main memory 4 to the shared buffer 14 according to the host program of the main ROM 5. Although not particularly limited, the sub CPU 12 can start the control operation by fetching and executing the initially loaded control program directly from a specific address of the shared buffer 14, for example. As a result, the sub CPU 12 internally transfers other necessary programs from the shared buffer 14 to the program area of the internal RAM 13. The sub CPU 12 internally transfers the operation data transferred to the shared buffer 14 by the main processor 3 to the flexible processor kernel 11 and supplies it to the operation of the flexible data processor (FDP) 2. The sub CPU 12 can internally transfer the operation result data from the flexible data processor (FDP) 2 to the shared buffer 14, and the host CPU 3 can extract the transferred operation data from the shared buffer 14 for further processing.

  FIG. 1 shows an example of the flexible processor kernel 2. The flexible processor kernel 2 includes an arithmetic unit (PEARY) 20, a plurality of data memories (DTRAM) 21, a plurality of memory control circuits (LS) 22, a bus interface unit (BI) 23 as an external interface unit, and a crossbar switch unit (XB). ) 24 and a control unit (AM) 25. The arithmetic unit 20 includes a plurality of arithmetic cells (PE) 26 that execute arithmetic operations, and their logical functions are defined based on configuration information (FECFG). The data memory 21 has a plurality of access ports that can operate in parallel, for example, dual ports, and holds operation data. Individual memory addresses are assigned to the plurality of data memories 21. The memory control circuit 22 recognizes the memory address assigned to the corresponding data memory 21 and controls access to the data memory 21, and the control form is defined based on the configuration information (FECFG). The bus interface unit 23 is commonly connected to each memory control circuit 22 via a kernel bus (KBUS) 30. The crossbar switch unit 24 connects the calculation unit 20 and the memory control circuit 22, and the connection form is defined based on configuration information (FECFG). The control unit 25 transfers the configuration information (FECFG) to the arithmetic cell 26, the memory control circuit 22, and the crossbar switch unit 24, and sequentially supplies sequence information (FECQC) thereto according to a predetermined timing. Thus, the state transition of the arithmetic cell 26, the memory control circuit 22 and the crossbar switch unit 24 is controlled to control the operation thereof. Reference numeral 27 denotes a transfer bus for transferring configuration information (FECFG) and sequence information (FESQC) to the arithmetic cell 26. Reference numeral 28 denotes a transfer bus for transferring configuration information (FECFG) and sequence information (FESQC) to the crossbar switch unit 24. Reference numeral 29 denotes a transfer bus that transfers configuration information (FECFG) and sequence information (FESQC) to the memory control unit 22. Although not particularly limited, the control unit 25 performs serial transfer control of the configuration information (FECFG) and the sequence information (FESQC) in accordance with the operation order with respect to the transfer buses 27, 28, and 29.

  The memory control circuit 22 can accept a first access request from the bus interface unit 23 to the data memory 21 and a second access request from the arithmetic unit 20 to the data memory 21. In short, a plurality of data memories 21 having dual ports can be accessed from the bus interface unit 23 or the arithmetic unit 20 through the memory control circuit 22. It is not necessary to secure a dedicated port in the data memory 21 in order to connect the data memory 21 to the bus interface unit 23. Therefore, the dual port of the data memory 21 can be used for both access from the bus interface unit 23 and access from the arithmetic unit 20. As a result, it is possible to allocate the free port in the load / store process between the arithmetic unit 20 and the data memory 21 to the transfer between the bus interface unit 23 and the data memory 21. Similarly, an empty port in a transfer process for storing operation target data in the data memory 21 via the bus interface unit 23 and a process for transferring operation result data from the data memory 21 via the bus interface 23 is used as an empty port and data. It is possible to distribute the transfer to and from the memory 21. As described above, the bus interface unit 23 is connected to the memory control circuit 21 arranged between the data memory 21 and the crossbar switch unit 24. Therefore, the bus interface unit 23 is not increased without increasing the number of ports of the data memory 21. The data transfer performance between the data memory 21 and the arithmetic unit 20 can be improved. Further, the memory control circuit 22 can change an access response control procedure for responding to the first access request and the second access request based on the configuration information. Since the access response control procedure for responding to the first access request and the second access request can be dynamically changed based on the configuration information, according to the arithmetic processing content and arithmetic processing status in the arithmetic unit 20, In order to maximize the data transfer rate to and from the data memory 21, the degree of freedom of giving priority to access of the data memory 21 to specific processing is increased, thereby improving the data processing performance in the arithmetic unit 20. It becomes possible to make it.

  The arithmetic cell 26 has the same level of arithmetic performance as an arithmetic logic unit in a general processor, and is not particularly limited. However, the arithmetic cell 26 is interconnected only with four cells adjacent in four directions, up, down, left, and right. Data transfer at a high operating frequency limited between adjacent cells is possible. Here, if only the input / output interface of each calculation cell is unified, the function does not need to be a single function. For example, according to the calculation characteristics of the task to be executed, for example, calculation cells that can only perform addition and subtraction and only cumulative calculation are executed. What is necessary is just to arrange the possible calculation cells in an optimal pattern. This makes it possible to reduce the area on the semiconductor chip and realize an arithmetic array with high arithmetic performance per area, compared to the case where a single type of arithmetic cell capable of executing all arithmetic operations is arranged. Furthermore, it goes without saying that the number of calculation cells in the vertical and horizontal directions can be arbitrarily set depending on the required cost and calculation performance.

  FIG. 3 shows an example of the crossbar switch unit 24. Here, the cross bus switch unit 24 has two ports XBPRT0 and XBPRT1 corresponding to one memory control circuit 22. An input signal line XIND0 and an output signal line XOUTD0 are laid in the horizontal direction at the ports XBPRT0 and XBPRT1. In the vertical direction, signal lines are laid in the vertical direction so as to intersect the respective input signal edges XIND0 and output signal lines XOUTD0. The vertical signal line is connected to the arithmetic cell 26 adjacent to the crossbar switch unit 24. Some signal lines in the vertical direction are signal lines connected to EXTIO. A selection switch 24A that selectively turns on / off the corresponding vertical and horizontal signal lines is disposed at the intersection of the vertical signal line and the horizontal signal line. Which selection switch 24A is turned on or off is determined by the configuration information (FECFG).

  Commands and data are supplied to the input signal lines XIND0 and XIND1 from the operation cell (PE) 26 in a predetermined request format. For example, the store request format for the data memory 21 includes a predetermined instruction code, a store memory address, and store data. The load request includes a predetermined instruction code and load data. A response header and load data in a response format to the request format are returned from the memory control circuit 22 to the output signal lines XOUTD0 and XOUTD1.

  FIG. 4 shows an example of the memory control circuit 22. The memory control circuit 22 includes two memory port interface circuits (MIF0, MIF1) 33 and 34 provided corresponding to the access ports RAMPRT0 and RAMPRT1 of the data memory 21 and a kernel bus connected to the kernel bus (KBUS) 30. And an interface circuit (KBIF) 35.

  The access port RAMPRT0 of the data memory 21 has an interface terminal for an output signal of a memory address MAD0, 16-bit write data MWD0, a write enable signal MWE0 and a read enable signal MRE0, and an input signal of 16-bit read data MRD0. . Similarly, the other access port RAMPRT1 of the data memory 21 is an interface between the memory address MAD1, output signals of 16-bit write data MWD1, write enable signal MWE1, and read enable signal MRE1, and input signals of 16-bit read data MRD1. It has a terminal. The kernel bus (KBUS) 30 is a bus signal including memory signal BAD, 16-bit write data BWD, write enable signal BWE, and read enable signal BRE as input signals, and 16-bit read data BRD and acknowledge signal ACK as output signals. With lines. The number of parallel bits of the read data and the write data is not limited to the above and can be changed as appropriate. As is clear from FIG. 1, the plurality of memory control circuits 22 are commonly connected to the kernel bus 30. The acknowledge signal ACK is asserted when an access request for the data memory 21 is accepted, and is maintained in a negated state when an access request is not accepted.

  The kernel bus interface circuit 35 detects the presence / absence of an access request from the kernel bus 30 to the data memory 21. For the detection, for example, the decoding result of the memory address BAD is used. If the decoding result is the mapping address of the corresponding data memory 21, it is determined that there is an access request. When the kernel bus interface circuit 35 detects an access request from the kernel bus 30, the memory bus interface circuit (MIF0) 33 or the other memory port interface circuit sends an access request from the kernel bus 30 in accordance with an instruction by the configuration information (FECFG). (MIF1) 34 is transmitted, or transmission to both is rejected.

  The memory port interface circuit 33 is connected to one access port RAMPRT 0 of the data memory 21, one port XBPRT 0 of the crossbar switch unit 24, and the kernel bus interface circuit 35. The memory port interface circuit 33 detects the presence / absence of an access request from the kernel bus 30 to the access port RAMPRT0 and the presence / absence of an access request from one port XBPRT0 of the crossbar switch unit 24. Detection of the former is performed depending on whether the read enable signal RE or the write enable signal WE transmitted from the kernel bus interface circuit 35 is activated. For the detection of the latter, for example, an analysis result for an instruction of a predetermined request format supplied from the input signal line XIND0 is used. When detecting an access request, the memory port interface circuit 33 performs interface control according to a predetermined procedure determined by the configuration information (FECFG). According to the interface control, the kernel bus (KBUS) 30 or the corresponding port XBPRT0 is connected to the corresponding port RAMPRT0 of the data memory 21, or the access request is rejected. When the memory port interface circuit 33 connects the kernel bus to the corresponding port RAMPRT0 of the data memory 21 in response to an access request from the kernel bus 30 and permits access to the data memory 21, the memory port interface circuit 33 asserts the acknowledge signal ACK and asserts the kernel. Return to the bus. When not responding to the access request from the kernel bus 30, the acknowledge signal ACK is maintained in a negated state. When the memory port interface circuit 33 accesses the data memory 21 from the port RAMPRT0 in response to an access request from the port XBPRT0, the read cell response format is used for read access, and the write completion response format is used for operation from XOUT0. Return to 26. Note that, since the bus control protocol is different between the ports XBPRT0 and RAMPRT0, protocol conversion is performed.

  The memory port interface circuit 34 is connected to the other access port RAMPRT 1 of the data memory 21, another port XBPRT 1 of the crossbar switch unit 24, and the kernel bus interface circuit 35. The memory port interface circuit 33 detects the presence / absence of an access request from the kernel bus 30 to the access port RAMPRT1 and the presence / absence of an access request from the port XBPRT1 of the crossbar switch unit 24. In the same manner as described above, the former is detected depending on whether the read enable signal RE or the write enable signal WE transmitted from the kernel bus interface circuit 35 is activated. The latter is detected by using an analysis result for an instruction of a predetermined request format supplied from the input signal line XIND1. When the memory port interface circuit 34 detects an access request, it performs interface control according to a predetermined procedure determined by the configuration information (FECFG). According to the interface control, the kernel bus (KBUS) 30 or the corresponding port XBPRT1 is connected to the corresponding port RAMPRT1 of the data memory 21, or the access request is rejected. When the memory port interface circuit 34 connects the kernel bus to the corresponding port RAMPRT1 of the data memory 21 in response to an access request from the kernel bus 30 and permits the data memory 21 to be accessed, the memory port interface circuit 34 asserts an acknowledge signal ACK to Return to the bus. When the memory port interface circuit 34 does not respond to the access request from the kernel bus 30, the acknowledge signal ACK is maintained in the negated state. When accessing the data memory 21 from the port RAMPRT1 in response to an access request from the port XBPRT1, the read data response format is returned to the arithmetic cell 26 from XOUT1 in read access and the write completion response format in write access. Note that the protocol conversion is the same as described above.

  The interface sequence control circuit (SC) 38 outputs a control signal CS for determining an interface control mode for the memory port interface circuits 33 and 34 and the kernel bus interface circuit 35. The interface control sequence of the interface sequence control circuit (SC) 38 is controlled by sequence control information (FESQC) supplied from the control unit 25 to the sequence control bus (SCB) 40. Configuration information (FECFG) necessary for interface control is fetched from the configuration information register (CR) 37. The configuration control circuit (CC) 36 performs control to prefetch the configuration information (FECFG) supplied from the control unit 25 to the configuration control bus (CCB) 41 to the configuration information register 37. When the interface sequence control circuit (SC) 38 changes the control state, it fetches prefetched configuration information (FECFG) from the configuration information register 37 in synchronization with the timing. Note that the sequence control bus (SCB) 40 and the configuration control bus (CCB) 41 correspond to the signal bus 29 in FIG. 1 and are commonly connected to the memory control circuit 22.

  The interface control modes for the memory port interface circuits 33 and 34 and the kernel bus interface circuit 35 include first to fourth control modes. The first control mode is a control mode for accepting an access request from the kernel bus 30 as a first access request and making one access port of the data memory 21 available. The second control mode is a control mode for accepting an access request from the port XBPRT0 or the port XBPRT1 as a second access request and making one access port of the data memory 21 available. The third control mode is a control mode in which an access request from the port XBPRT0 and an access request from the port XBPRT1 are received and different access ports of the data memory 21 can be used. In the fourth control mode, the first access request is accepted and one access port of the data memory 21 is made available, and the second access request is accepted and another access port of the data memory 21 is made available. It is a control form.

  In the first to fourth control modes described above, several control modes are selected for arbitration for arbitrating access requests from the kernel bus 30 and access requests from the ports XBPRT0 and XBPRT1 of the crossbar switch unit 24. This mode of arbitration control will be described.

  In the first arbitration control mode, when all the access ports of the data memory 21 are used in response to the second access request, the bus interface unit 23 is busy in response to the first access request. Is a control that returns. The busy state is notified by maintaining an acknowledge signal ACK in a negated state with respect to the first access request. That is, in the first arbitration control mode, when the kernel bus interface circuit 35 transmits an access request from the kernel bus 30 to the memory port interface circuit 33 or 34, it responds to the access requests from the ports XBPRT0 and XBPRT1, respectively. The memory port interface circuit 33 or 34 that is being held rejects the access request and maintains the acknowledge signal ACK in the negated state. Alternatively, the kernel bus interface circuit 35 rejects the access request without transmitting the access request from the kernel bus 30 to any of the memory port interface circuits 33 or 34, and as a result, the acknowledge signal ACK is maintained in the negated state. By returning a busy state, the recipient recognizes that the first access request has been rejected. As a result, the receiving side in the busy state can respond immediately by inserting a wait or changing processing scheduling.

  In the second arbitration control mode, when all access ports are used in response to the second access request, a request source of one second access request responds to the first access request. This control returns the busy state. The busy state is notified, for example, by outputting a predetermined response format notifying access stop from the port XBPRT0 or XBPRT1. That is, in the second arbitration control mode, when the kernel bus interface circuit 35 transmits an access request from the kernel bus 30 to the memory port interface circuit 33 or 34, the memory port interface circuit 33 or 34 that has received the access request. Actually cancels the activation of a new access cycle of the data memory 21 in response to an access request from the port XBPRT0 or XBPRT1, and outputs a predetermined response format for notifying the access stop from the port XBPRT0 or XBPRT1. This response format may be accompanied by write data that is the target of write stop. By returning the busy state, the computation cell 26 which is the receiving side recognizes that the second access request has been rejected. As a result, the busy side can respond by inserting waits or changing processing scheduling.

  In the second arbitration control mode, the kernel bus interface circuit 35 returns the busy state to the access request source connected to the lower priority memory port RAMPRT0 or RAMPRT1 according to the priority of the memory ports RAMPRT0 and RAMPRT1. I do. As a result, the configuration information (FECFG) can be defined so that the memory port RAMPRT0 or RAMPRT1 having a high priority is used for data processing having a high priority. It is possible to suppress being disturbed by requests.

  Furthermore, the priority of the memory ports RAMPRT0 and RAMPRT1 recognized by the kernel bus interface circuit 35 may be made variable according to the configuration information (FECFG). The degree of freedom of control increases.

  In the third arbitration control mode, when the first access request and the second access request compete, the access request with the higher priority is preferentially received. That is, the memory interface circuits 33 and 34 recognize the difference in priority between the first access request from the kernel bus 30 and the second access request from the operation cell 26. Accordingly, when the first access request and the second access request compete with each other, the memory interface circuits 33 and 34 preferentially accept the access request having the higher priority. Thereby, it may be more convenient to prioritize the first access request according to the contents of the data processing by the computation cell 26 or the progress of the computation, and it is better to prioritize the second access request. In some cases. Depending on the setting of the priority, it can contribute to the improvement of the data processing performance.

  In the third arbitration control mode, it is preferable to set priorities of the first access request and the second access request separately for each of the memory ports RAMPRT0 and RAMPRT1. Furthermore, finer priority control can be performed. Conveniently, the priorities of the first access request and the second access request are made variable according to the configuration information (FECFG).

  FIG. 5 shows an example of the memory port interface circuit 33. The memory port interface circuit 33 includes an access controller (AC) 45, an address generator (AG) 46, a store data generator (SDG) 47, and a load data generator (LDG) 48. The access controller 45 detects an access request from the kernel bus 3 by the read enable signal RE or the write enable signal WE. The access controller 45 detects the access request from the port XBPRT0 from the request format code. The access controller 45 asserts and returns an acknowledge signal ACK when accepting an access request from the kernel bus, and maintains the acknowledge signal ACK in a negated state when not accepted. When the access controller 45 accepts an access request from the port XBPRT0, the access controller 45 returns a response format of acceptance for write access and returns a response format of read data for read access. When the access controller 45 does not accept an access request from the port XBPRT0, it returns an acceptance rejection response format. RDV is a code added to the response format.

  The access controller 45 performs control for the arbitration. The access controller 45 recognizes the difference in priority between the first access request from the kernel bus 30 and the second access request from the arithmetic cell 26 by the control signal SC. When the first access request and the second access request conflict, the access request with the higher priority is preferentially accepted. In this case, when an access request with a low priority is received first, whether or not to wait for the end of an access cycle responding to the access request with a low priority is determined by the control signal SC. When not waiting, the access controller 45 performs the control operation described in the first arbitration control mode or the second arbitration control mode. The control signal ACFR is a connection selection control signal of the access request source for connecting the accepted access request source to the memory port RAMPRT0.

  The address generator 46 presets the address supplied from BAD or XIN0, and outputs this to MAD0, or outputs the incremented address to MAD0 as an initial value. The control signal IN is an increment instruction signal.

  The store data generator (SDG) 47 switches data from XIN0 or data BWD, and performs data alignment in accordance with the bus width of the memory write data as necessary.

  A load data generator (LDG) 48 switches the memory read data MRD0 to XOUT0 or the bus BRD, and performs data alignment of output data as necessary.

  Although not shown, the memory port interface circuit 34 is configured in the same manner as in FIG.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof. For example, recognition of memory access from the kernel bus by the memory control circuit is not limited to a method based on an access address, a read enable signal, and a write enable signal. Further, the present invention is not limited to the configuration using the acknowledge signal as a response to the access request, and a valid signal may be used or another response code may be used. The interface with the calculation cell is not limited to the configuration using the response format. The response format can be understood as a packet in which a predetermined format is defined. Data memory is not limited to dual ports. A multi-port such as a triple port may be used. The kernel bus may employ a bus protocol that multiplexes and transfers addresses, data, and control signals. It goes without saying that the flexible processor kernel can be realized as a single semiconductor integrated circuit by itself.

It is a block diagram which shows an example of a flexible processor kernel. It is a block diagram which shows an example of a data processing system. It is a block diagram which shows an example of a crossbar switch part. It is a block diagram which shows an example of a memory control circuit. It is a block diagram which shows an example of a memory port interface circuit.

Explanation of symbols

1 system bus 2 flexible data processor 3 host processor (HCPU)
4 Main memory (MMRY)
5 Main ROM (MROM)
6 Local ROM (LROM)
10 Internal bus 11 Flexible processor kernel (FPK)
12 Sub CPU (SCPU)
13 Internal RAM (IRAM)
14 Shared buffer (SBUF)
20 Arithmetic unit (PEARY)
21 Multiple data memories (DTRAM)
22 Memory control circuit (LS)
23 Bus Interface (BI)
24 Crossbar switch (XB)
25 Control unit (AM)
26 Computing cell (PE)
30 Kernel Bus (KBUS)
FECFG configuration information FESQC sequence information 33, 34 Report interface circuit (MIF0, MIF1)
35 Kernel Bus Interface Circuit (KBIF)

Claims (10)

An arithmetic unit that includes a plurality of arithmetic cells that perform arithmetic operations and whose logical functions are defined based on configuration information;
A plurality of data memories having a plurality of access ports operable in parallel and holding operation data;
A plurality of memory control circuits that control access to the corresponding data memory and whose control form is defined based on configuration information;
An external interface connected to the memory control circuit;
A crossbar switch unit that connects the arithmetic unit and the memory control circuit, the connection form of which is defined based on configuration information;
A control unit that performs control to transfer the configuration information to the arithmetic cell, the memory control circuit, and the crossbar switch unit and controls state transition thereof, and
The memory control circuit is capable of accepting a first access request from the external interface unit to the data memory and a second access request from the operation cell to the data memory. An access response control procedure for responding to an access request is a data processing device that can be varied based on the configuration information.   As the variable access response control procedure, the memory control circuit accepts a first access request and uses one access port of the data memory, and accepts a second access request and accesses one data memory. Control using a port, control using a different second access request in parallel and using a different access port, and receiving a first access request and using one access port of the data memory and 2. The data processing apparatus according to claim 1, wherein control for accepting two access requests and using another access port of the data memory is possible.   The memory control circuit responds to the first access request when all access ports are used in response to the second access request as the variable access response control procedure for the corresponding data memory. The data processing apparatus according to claim 2, wherein control for returning a busy state to the external interface unit is possible.   The memory control circuit responds to the first access request when all access ports are used in response to the second access request as the variable access response control procedure for the corresponding data memory. 4. The data processing apparatus according to claim 2, wherein control for returning a busy state to a request source of one second access request is possible.   The memory control circuit returns a busy state to an access request source connected to an access port having a low priority according to the priority of the access port in order to select a request source of one second access request that returns the busy state. The data processing apparatus according to claim 4.   6. The data processing apparatus according to claim 5, wherein the priority of the access port is made variable in the memory control circuit according to the configuration information.   3. The data processing apparatus according to claim 2, wherein when the first access request and the second access request compete with each other, the memory control circuit preferentially receives an access request having a higher priority.   8. The data processing apparatus according to claim 7, wherein priorities of the first access request and the second access request can be set separately for each access port in the memory control circuit.   9. The data processing apparatus according to claim 8, wherein the priority of the first access request and the second access request is made variable according to the configuration information in the memory control circuit. A data processor having a flexible processor, CPU and RAM connected to an internal bus,
The flexible processor includes a plurality of calculation cells that perform calculations, and a calculation unit whose logical functions are defined based on configuration information;
A plurality of data memories having a plurality of access ports operable in parallel and holding operation data;
A plurality of memory control circuits that control access to the corresponding data memory and whose control form is defined based on configuration information;
An external interface connected to the memory control circuit;
A crossbar switch unit that connects the arithmetic unit and the memory control circuit, the connection form of which is defined based on configuration information;
A control unit that performs control to transfer the configuration information to the arithmetic cell, the memory control circuit, and the crossbar switch unit, and controls state transition thereof, and
The memory control circuit is capable of accepting a first access request from the external interface unit to the data memory and a second access request from the operation cell to the data memory. The access response control procedure for responding to the access request is made variable based on the configuration information,
The external interface unit is connected to the internal bus,
The CPU executes a program stored in the RAM, and can transfer data held in the RAM from the external interface unit to the data memory;
The CPU is a data processor capable of transferring operation result data by a flexible processor held in the data memory from an external interface unit to the RAM.

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