JP2006343892A - Circuit for monitoring operation of cpu - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To attain space saving and cost reduction by reducing the necessary number of capacitors for a timer by half and reducing the capacity. <P>SOLUTION: A CPU 3 periodically outputs a re-trigger signal in a normal time by using a power source 7 for the CPU as a power source. A watch dog timer circuit 1 fetches the re-trigger signal by a capacitor coupling circuit 9 by using a power source 8 for an abnormal output as a power source, and decides that the CPU is abnormal, and obtains an abnormality output when the re-trigger signal is not inputted within the time limit of abnormality decision set in a capacitor 2 for a timer. An insulating circuit is installed between the CPU and a capacitor coupling circuit. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an operation monitoring circuit of a CPU, and more particularly to an abnormality detection circuit using a watch dog timer (WDT) system.

  An apparatus that implements various digital processing functions using a control computer as a central part, such as a digital protective relay, has a watchdog timer system as a system for monitoring normal operation of a CPU (see, for example, Patent Document 1). In this method, when the CPU is normal, a reset signal is output within the timer time-up time, and the timer is re-triggered by this reset signal to suppress the timer time-up. When an abnormality occurs in which the CPU cannot output a reset signal, the timer times out, and this time up is obtained as an abnormal operation output of the CPU.

  FIG. 4 shows a conventional operation monitoring circuit. The watchdog timer circuit 1 sets the time for which the timer capacitor 2 is charged to a certain level as a time limit. When the retrigger signal is given from the CPU 3 within this time, the capacitor 2 is reset, and the retrigger signal is given within the time. When not, an abnormality detection signal of the CPU 3 is obtained. The abnormality detection signal is converted into a trigger signal for the abnormality output circuit 5 through the optical isolation circuit 4 such as a photocoupler, and the abnormality output circuit 5 suppresses the operation for a time limit by the timer capacitor 6 to obtain an abnormality output.

  Here, the CPU power source 7 is a DC power source on the CPU 3 side, the abnormal output power source 8 is a DC power source on the abnormal output circuit 5 side, and even when the CPU 3 cannot generate a retrigger signal due to the power supply voltage drop. The abnormal output circuit 5 can generate an abnormal output. In this power source separation configuration, when the device is operated / stopped, an abnormality is caused by the timer capacitor 6 so that an abnormal output is not mistakenly caused by a difference in rising / falling timing of the CPU power supply 7 and the abnormal output power supply 8. The operation of the output circuit 5 is suppressed. That is, the timer capacitor 6 serves as a malfunction prevention timer when an abnormality detection signal is erroneously generated.

FIG. 5 shows a specific circuit configuration of FIG. 4, and equivalent parts are shown by being associated with the same reference numerals. The watchdog timer circuit 1 charges the timer capacitor 2 while the transistor Q1 is off during a period when the retrigger signal is not supplied from the CPU 3, and this charge voltage is monitored by the comparator COM via the buffer amplifier BUF. Is reached, that is, when the retrigger signal is not given from the CPU 3, an abnormality detection signal is generated from the comparator COM. The abnormal output circuit 5 obtains an abnormal output from the photo MOS when the transistor Q2 is turned on. A timer capacitor 6 is provided at the base of the transistor Q2, and malfunction is prevented by an abnormality detection signal passing through the insulating circuit 4 until the capacitor 6 is completely charged. For example, even when the voltage of the power supply 8 is established before the power supply 7 at the start of the operation of the apparatus, an abnormal output is prevented from being erroneously generated until the capacitor 6 is completely charged.
JP-A-5-20289

  As described above, when the device is operated / stopped, the timer capacitor 6 has a large capacity so that an abnormal output is not mistakenly caused by a difference in the rise / fall timing of the CPU power supply 7 and the abnormal output power supply 8. An electrolytic capacitor is provided, and the time limit is made sufficiently long to prevent malfunction.

  For this reason, timer capacitors 2 and 6 are required on both the CPU side and the abnormal output circuit side. In particular, there is a problem that the large-capacitance capacitor of the timer capacitor 6 increases the mounting space and costs.

  An object of the present invention is to provide a CPU operation monitoring circuit that saves space and reduces costs by halving the required number of timer capacitors and reducing the capacity in the watchdog timer system.

  In order to solve the above-mentioned problems, the present invention provides a watchdog timer circuit on the power supply side for abnormal output, and the watchdog timer circuit uses one small capacitor for the watchdog timer and the malfunction prevention timer. It can be used in combination, and has the following configuration.

(1) A CPU operation monitoring circuit that determines that the watchdog timer circuit determines that the CPU is abnormal when a retrigger signal is not output from the CPU within a certain period of time,
The CPU is configured to use a power source for CPU as a power source, and periodically output the retrigger signal when normal.
The watchdog timer circuit is configured to use a power supply for abnormal output as a power source, and to determine that the CPU is abnormal and obtain an abnormal output when the retrigger signal is not input within the time limit for abnormality determination set by the timer capacitor. It is characterized by.

  (2) The retrigger signal from the CPU is provided with an insulating circuit that is optically or electrically insulated and input to the watchdog timer circuit side.

  As described above, according to the present invention, the watchdog timer circuit is provided on the power supply side for abnormal output, and the watchdog timer circuit can be used for both the watchdog timer and the malfunction prevention timer by using one small capacitor. The configuration has the following effects.

  (1) It is only necessary to provide one timer capacitor that serves both as a watchdog timer and a malfunction prevention timer, and the required number of capacitors can be halved.

  (2) Since the watchdog timer circuit is provided on the power supply side for abnormal output, abnormality detection is possible even when the power supply is not established.

(Embodiment 1)
FIG. 1 is an operation monitoring circuit diagram of a CPU showing the present embodiment, and the same components as those in FIG. 4 are denoted by the same reference numerals. The CPU 3 uses the CPU power source (+ 5V) 7 as a power source, starts operation when the power source is established, and periodically outputs a retrigger signal. On the other hand, the watchdog timer circuit 1 uses the abnormal output power supply (+ 12V) 8 as a power supply, and starts its operation when the power supply is established. Determine if there is an abnormality.

  The capacitor coupling circuit 9 absorbs the difference between the signal level of the retrigger signal output from the CPU 3 and the signal level of the retrigger signal input to the watchdog timer circuit 1, that is, a signal due to the difference in DC voltage between the power supplies 7 and 8. A level shift circuit for absorbing the difference in level is realized, and is realized by a small-capacitance capacitor and a resistor circuit.

  The watchdog timer circuit 1 resets the timer capacitor 2 every time a retrigger signal is input from the CPU side within the timer time of the timer capacitor 2, and an abnormality occurs when the retrigger signal is not input within this time. judge.

  It is a concrete circuit configuration of FIG. 2 and FIG. 1, and an equivalent part is matched and shown with the same code | symbol. The capacitor coupling circuit 9 includes a small-capacitance capacitor and a resistor R that can pass a retrigger signal from the CPU 3. The watchdog timer circuit 1 starts its operation when the power source 8 is established, starts charging the timer capacitor 2 at the start of this operation, and the transistor Q1 is turned on each time a retrigger signal is output from the CPU 3 side. The capacitor 2 is reset. The charging voltage of the timer capacitor 2 is monitored by the comparator COM through the buffer amplifier BUF, and an abnormal output is generated from the photo MOS or photo coupler when charged to a certain voltage.

  Therefore, according to the present embodiment, only the retrigger signal output of the watchdog timer is output on the CPU 3 side, and the watchdog timer circuit 1 is provided with one timer capacitor 2 that functions as both a watchdog timer and a malfunction prevention timer. That's it.

(Embodiment 2)
FIG. 3 is an operation monitoring circuit diagram of the CPU showing the present embodiment. The difference from FIG. 1 is that an insulating circuit is interposed between the CPU side and the watchdog timer circuit side, and the CPU side and the watchdog timer circuit side. It is in the point of ensuring the insulation of.

  As the insulating circuit, an optical insulating circuit 4 is provided as in FIG. 4, and a retrigger signal from the CPU 3 is input to the capacitor coupling circuit 9 through the optical insulating circuit 4.

  The optical isolation circuit 4 is realized by a photocoupler or a photo MOS, but may be an electrical isolation circuit using an insulating pulse transformer.

FIG. 2 is an operation monitoring circuit diagram of the CPU showing the first embodiment of the present invention. FIG. 3 is a specific circuit configuration diagram of the first embodiment. The operation | movement monitoring circuit diagram of CPU which shows Embodiment 2 of this invention. FIG. 6 is a circuit diagram of a conventional CPU operation monitoring circuit. The conventional concrete circuit block diagram.

Explanation of symbols

1 Watchdog timer circuit 2 Capacitor for timer 3 CPU
4 Optical Isolation Circuit 5 Abnormal Output Circuit 6 Timer Capacitor 7 CPU Power Supply 8 Abnormal Output Power Supply 9 Capacitor Coupling Circuit

Claims (2)

An operation monitoring circuit for a CPU that determines that a watchdog timer circuit is abnormal in a CPU when a retrigger signal is not output from the CPU within a predetermined time;
The CPU is configured to use a power source for CPU as a power source, and periodically output the retrigger signal when normal.
The watchdog timer circuit is configured to use a power supply for abnormal output as a power source, and to determine that the CPU is abnormal and obtain an abnormal output when the retrigger signal is not input within the time limit for abnormality determination set by the timer capacitor. CPU operation monitoring circuit characterized by the above. 2. The operation monitoring circuit for a CPU according to claim 1, further comprising an insulating circuit that inputs the retrigger signal from the CPU to the watchdog timer circuit side after being optically or electrically insulated.

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