JP2006195910A - Microcomputer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a microcomputer capable of realizing various peripheral functions by software while suppressing increase of program size to the utmost. <P>SOLUTION: In this microcomputer 10, a CPU 11 can execute and process a peripheral function instruction described in an L task as one instruction. The CPU 11 acquires information required for the execution of the peripheral function instruction from a general-purpose register 30 designated by an operand, and stores information related to an execution result of the instruction in the general-purpose register 30. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  In the present invention, a plurality of tasks can be processed in a time-sharing parallel manner, and at least one of these tasks is a specific task in which a program that loops so that the increment of the instruction address is constant is described. It relates to a microcomputer.

When a microcomputer configured by adding ROM, RAM, and other peripheral functions to a CPU is applied to various user applications, it is generally necessary to change the hardware according to the functions required for each application. There is a problem that the variation of the product increases.
Therefore, a configuration has been considered in which operations as peripheral functions are realized by software. For example, in Patent Document 1, two tasks (A, L) are processed in a time-sharing manner in a single CPU, and execution of a branch instruction is prohibited in the L task to form a fixed loop. There is disclosed a microcomputer in which a value is used as a timer or a runaway monitoring process of an A task is performed.

However, in the microcomputer of Patent Document 1, for example, a more complicated peripheral function such as a so-called “input capture” function that acquires a timer value according to a level change of a specific input terminal or serial communication is realized. There is a problem that the program size becomes very large.
Further, in Patent Document 2, in order to extend the instruction function executed by the microcomputer, a prefix instruction is arranged immediately before the target instruction described in the program, and the flag state set in the prefix instruction is set. Accordingly, a configuration is disclosed in which the function of the target instruction is expanded.
JP-A-6-250857 JP 2004-38521 A

However, in the technique of Patent Document 2, since it is necessary to always insert a prefix instruction in order to expand the instruction function, the program size also increases.
The present invention has been made in view of the above circumstances, and an object thereof is to provide a microcomputer capable of realizing various peripheral functions by software while suppressing an increase in program size as much as possible. .

  According to the microcomputer of the first aspect, the CPU is configured to be capable of executing the peripheral function instruction described in the specific task as one instruction. Then, information necessary for executing the peripheral function instruction is acquired from the general-purpose register specified by the operand, and information related to the execution result of the instruction is stored in the general-purpose register. Therefore, the description of the program for realizing the peripheral function by software becomes extremely simple, and the program size can be reduced. Further, since the bits of the general-purpose register can be manipulated by instructions normally prepared in the CPU, it is not necessary to separately prepare special instructions such as prefix instructions in order to execute peripheral function instructions. Here, “peripheral function is realized by software” means that the peripheral function is realized by the cooperation of the hardware of the CPU in the microcomputer of the present invention and the program executed by the CPU. It shows that.

  According to the microcomputer of the second aspect, when executing the input capture instruction, the CPU acquires edge designation information of the input terminal which is a condition for acquiring the timer value from the general-purpose register. Then, by comparing the level of the input terminal sampled last time stored in the general-purpose register with the current level of the input terminal, it is possible to determine whether the acquisition condition (rising edge, falling edge, etc.) is satisfied, The value of the timer counter acquired when the condition is satisfied is stored as a capture value, and a flag indicating that input capture is satisfied is stored. Therefore, the input capture function can be realized by software by executing the input capture instruction after setting the edge designation information in the general-purpose register in advance by the normal instruction.

  According to the microcomputer of the third aspect, when executing the sampling compare instruction, the CPU acquires a compare cycle value set in the general-purpose register. The general-purpose register stores the data obtained by cumulatively adding the compare cycle values at each sampling timing as a compare value. If the compare value matches the timer counter value, the sampling result and the establishment flag are stored in the general-purpose register. To do. Therefore, a sampling compare function can be realized by software by executing a sampling compare instruction after setting a compare cycle value in a general-purpose register in advance by a normal instruction.

  According to the microcomputer of the fourth aspect, when executing the input compare set instruction, the CPU acquires the compare period value set in the general-purpose register and the edge designation information of the input terminal which becomes the compare set condition. When the compare set condition is satisfied, a value obtained by adding the compare cycle value to the value of the timer counter at that time is stored as a compare value in the general-purpose register and the satisfied flag is stored. Therefore, the input compare set function can be realized by software by executing the input compare set instruction after setting the compare cycle value and edge designation information in the general-purpose register in advance by a normal instruction.

  According to the microcomputer of the fifth aspect, when executing the conditional sampling instruction, the CPU determines whether or not the condition flag is set in the general-purpose register. When the condition flag set is recognized, the sampling result and the establishment flag are stored in the general-purpose register. Therefore, when a predetermined condition is satisfied while executing a specific task, a conditional sampling function can be realized by software by setting a condition flag in a general-purpose register by a normal instruction.

According to the microcomputer of the sixth aspect, when the CPU executes the instruction of the input processing system, the CPU stores the state of the previous input terminal and the state of the current input terminal in the general-purpose register, and the values of both are stored. In case of a match, it has a double match filter function that permits execution of the input processing system instruction. The “input processing instructions” referred to here are “input capture instructions”, “sampling compare instructions”, “input compare set instructions”, and “conditional sampling instructions” in claims 2 to 5. Therefore, the input processing system command can be executed when it is confirmed that the state of the input signal or data is stable.
According to the microcomputer of the seventh aspect, the CPU is configured to be able to select whether or not to execute the coincidence filter function according to the bit setting in the general-purpose register. Can be selected according to the application.

  According to the microcomputer of the eighth aspect, when executing the output compare instruction, the CPU acquires the compare cycle value and the output level designation condition set in the general-purpose register. Similarly to the sampling compare instruction, the general-purpose register stores the data obtained by cumulatively adding the compare cycle values as a compare value. If the compare value matches the timer counter value, the specified level is stored. Output from the output terminal and store the establishment flag in the general-purpose register. Therefore, the output compare function can be realized by software by executing the output compare instruction after setting the compare cycle value in the general-purpose register in advance by the normal instruction.

  According to the microcomputer of the ninth aspect, when the conditional output instruction is executed, the CPU acquires the output level designation condition set in the general-purpose register. Also, it is determined whether a condition flag is set in the general-purpose register. When the condition flag set is recognized, a level corresponding to the specified condition is output to the output terminal and the establishment flag is stored in the general-purpose register. Therefore, after setting the output level specification condition in the general-purpose register in advance by a normal instruction, if a predetermined condition is satisfied while executing a specific task, the software can be set by setting a condition flag in the general-purpose register by a normal instruction. A conditional output function can be realized.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a functional block diagram showing the configuration of the microcomputer 10. The microcomputer 10 receives a CPU 11, a program memory 12 constituted by a ROM, a data memory 13 constituted by a RAM, an I / O block 14 (input / output pins), and a CPU switching signal (clock signal) described later. A timing generator (not shown) for generating data, a data bus 15 for transmitting and receiving data, an address bus 16 for transmitting and receiving address signals, and control buses 17 and 18 for transmitting and receiving read signals and write signals, respectively, are provided.
The CPU 11 includes, for example, two address registers 19 and 20 and two operation registers 21 and 22 for pipelining two types of tasks (L task and A task) in a time-sharing manner. , 20 and the arithmetic registers 21 and 22 are alternately switched by a CPU switching signal, and apparently function to switch the two CPUs alternately.

  In this case, one address register 19 and operation register 21 are registers for CPU0 (for L task), and the other address register 20 and operation register 22 are registers for CPU1 (for A task). The value of the program counter 23 (address of the next instruction to be fetched) is updated according to the switching of the address registers 19 and 20, and the CPU 0 (for L task) and CPU 1 (for A task) are updated from the program counter 23. Address signals are alternately output to the program memory 12.

  Further, in the CPU 11, an error detection circuit 24 serving as an error detection means for determining the type of task to which the instruction read from the program memory 12 belongs and detecting the error, and the instruction that has passed through the error detection circuit 24 are decoded. An instruction decoder / instruction sequencer 25 for decoding (decoding) is provided, and in accordance with the contents of the instruction decoded by the instruction decoder / instruction sequencer (hereinafter simply referred to as instruction decoder) 25, an arithmetic unit 26 (ALU) operates the operation register 21. , 22 and outputs a read signal or a write signal to the control buses 17, 18.

  On the other hand, in the program memory 12, a program area 27 for CPU0 (for L task), a program area 28 for CPU1 (for A task), and a table immediate data area 29 are provided. In this case, the L task stored in the program area 27 for the CPU 0 is composed of a fixed loop program in which a branch instruction that may lead to program runaway is prohibited. As a result, when the L task program is executed, the execution is started with the 2-byte instruction access from address 0, the instructions are executed in order of address 2, address 4, address 6, and so on, and then reach a predetermined address. Then, the program counter 23 overflows and returns to the address 0, and thereafter the instruction execution in the order of the addresses is repeated. In this L task, all instructions are fixed to 1 word (2 bytes) instructions.

The L task (specific task) is suitable for performing sequence control processing, and the program includes a routine for monitoring runaway of the A task and a routine for backup sequence for establishing system fail-safety. ing. Furthermore, this L task also has a function as a timer by a fixed loop operation. For example, when an increment instruction or a decrement instruction is executed and the count value reaches a predetermined set value, an interrupt is generated in the processing of the A task. This makes it possible to perform fixed-time processing equivalent to timer interrupts.
On the other hand, for the A task, branch instructions prohibited by the L task are also permitted, and are suitable for, for example, complex analysis processing and numerical processing. As for the A task, as in the L task, all instructions are fixed to a one-word instruction. In the A task and the L task, both an operation code and an operand (address) are allocated in one word.

  Next, a pipeline control system adopting the microcomputer having the above configuration will be described with reference to FIG. This pipeline is configured as, for example, a three-stage pipeline including instruction fetch, instruction decode, and instruction execution stages, and is designed so that all instructions can be processed without delay in the three-stage pipeline. Each stage is executed in one cycle, and one instruction is executed in three cycles, but apparently one instruction is processed in one cycle by processing three instructions in parallel by a three-stage pipeline. Is equivalent to running

The time for one cycle (each stage) is defined by a CPU switching signal (clock signal). This CPU switching signal has the same low-level time TLo and high-level time THi, and CPU0 (L task) instruction fetch is performed during the low level period, and CPU1 (A task) instruction fetch is performed during the high level period. By doing this, both the CPU0 (L task) and CPU1 (A task) programs are pipelined in parallel at a time division ratio of 1: 1.
Further, when the CPU 1 fetches the branch instruction included in the program of the A task, the branch destination is fetched at the instruction decode stage in order to fetch the instruction at the branch destination address at the instruction fetch stage next to the A task including the branch instruction. It is configured to set the address. FIG. 2 shows the processing timing when the instruction at address Y + 1 of the CPU 1 is a branch instruction (JMP) during pipeline processing.

  The CPU 11 has a plurality of address registers 19 and 20 for sequentially setting different instruction addresses in the program counter 23, and a plurality of operation registers (19 and 20 for sequentially setting instructions decoded by the instruction decoder 25 in the arithmetic unit 26. Instruction registers) 21 and 22, and by sequentially switching the plurality of address registers 19 and 20 and the plurality of operation registers 21 and 22, a plurality of programs 27 and 28 stored in the program memory 12 are pipeline processed. It is configured to be possible.

  Further, as a command set of the CPU 11, “peripheral function commands” to be described later are prepared. This “peripheral function instruction” is an instruction prepared for the CPU 11 to process the processing that has been realized by using hardware configured outside the CPU 11 in the L task as software. . The instruction decoder 25 and the arithmetic unit 26 are configured to execute peripheral function instructions in one cycle in the execution stage of pipeline processing.

  The general-purpose register 30 normally stores data read via the data bus 15 when, for example, a load instruction is executed on a peripheral circuit of the CPU 11. In the general-purpose register 30 of the present embodiment, when the instruction decoder 25 decodes the instruction and the instruction is a “peripheral function instruction”, the input signal level of the input terminal 31 is stored in some bits. Alternatively, a signal corresponding to data set in some bits can be output via the output terminal 32. In addition, data can be transferred between the general-purpose register 30 and the program counter 23. In practice, there are a plurality of general-purpose registers 30, input terminals 31, and output terminals 32, but only one is shown in FIG. 1 for convenience of illustration.

  Next, the operation of the present embodiment will be described with reference to FIGS. FIGS. 3 to 8 shown below are the case where (a) the setting state of each bit in the general-purpose register 30 when the CPU 11 executes the peripheral function instruction, and (b) the pipeline processing in the instruction decoder 25 or the arithmetic unit 26. 5 is a representation of the contents of processing executed in one cycle (by hardware) in the execution stage in C language, and FIG.

<Input capture instruction>
FIG. 3 shows the contents related to the input capture instruction. The input capture function reads the count value of the free-run counter at a timing when a specific trigger signal is given. For example, it is used when measuring the time between signal edges of the input terminal or for simple edge detection. In the present embodiment, when the CPU 11 executes an input capture instruction described in the L task, the count value of the program counter 23 is used as a timer counter, so that the CPU 11 performs processing in software.
Here, “processing in software” means processing completed inside the CPU 11 with respect to processing performed using hardware provided outside the CPU 11. That is, it is referred to as “software-like” including the part where the internal logic of the CPU 11 operates.

As shown in FIG. 3A, when the input capture instruction is executed, each bit of the register Rm, which is one of the general purpose registers 30, is assigned as follows.
Bit 15: Current input terminal state (level)
14: Previous input terminal state (level)
13: Sampling value (level) of input terminal
11: Double match filter enable / disable 10, 9: Signal edge specification of input terminal 8: Input capture establishment flag 7-0: Capture value Of these, the double match filter in bit 11 is enabled / disabled, The signal edge designation of the input terminal in bits 10 and 9 is preset in the register Rm by the load instruction described on the A task side, and the register Rm is designated by the operand in the input capture instruction.

The input capture instruction is executed in the execution stage as shown in FIG. 3B. Note that the procedure shown in FIG. 3B is not executed programmatically step by step, but when an input capture instruction is executed, these processes are performed in one cycle by the logic of the instruction decoder 25 or the arithmetic unit 26. Is executed.
That is, when the coincidence filter permission is set in bit 13, if the exclusive OR of bits 15 and 14 is established and the two do not coincide, the contents of bit 15 are transferred to bit 14. Similarly, if the two match, the content of bit 15 at that time is transferred to bit 14 in the same manner. When the filter prohibition is set, the content of bit 15 is transferred to bit 14 without performing the first mismatch determination. Then, the edge determination of the input terminal 31 is performed.

In the edge determination, the bit 15 which is the level of the current input terminal 31 is compared with the bit 13 in which the level of the input terminal 31 when the same instruction is executed last time is stored as a sampling value, and the two match. If there is no change in the input level, no edge is detected, and the contents of bit 15 are transferred to bit 13 and the process ends.
On the other hand, if the bits 15 and 13 do not match, the level of the input terminal 31 changes and an edge is detected. In this case, it is determined whether the edge condition (rising edge, falling edge, or any edge) specified by bits 10 and 9 is satisfied. If the condition is satisfied, the value of the program counter 23 is registered. The data is stored in bits 7: 0 of Rm, and the establishment flag is set in bit 8 to end the process. The designation of each input terminal 31 may be fixed by default or may be designated using other general-purpose instructions, for example.

Here, assuming that the above-described input capture function is realized by providing a circuit outside the CPU 11, the following circuit is generally required.
(1) Free-run timer (2) Capture register that stores the count value of the free-run timer (3) Control register for specifying the trigger edge and the presence / absence of the double match filter In the embodiment, (1) corresponds to the program counter 23, and (2) and (3) correspond to the register Rm, so that the input capture function is realized by the CPU 11 alone as hardware.

<Sampling compare instruction>
FIG. 4 shows the contents relating to the sampling compare instruction. The sampling compare function samples the level of the input terminal 31 every time a designated sampling period elapses. Also in this case, the count value of the program counter 23 is used as a timer counter.

As shown in FIG. 4A, when the sampling compare instruction is executed, the bits of the registers Rm and Rn in the general-purpose register 30 are assigned as follows.
Register Rm bit
15: Current input terminal state (level)
14: Previous input terminal state (level)
13: Sampling value (level) of input terminal
12: Sampling result (1 bit)
11: Double match filter enable / disable
10, 9: Specifying sampling
8: Sampling compare establishment flag
7 to 0: Compare value register Rn bit
15 to 8: Sampling result (in the case of 1 byte)
7 to 0: Compare cycle

The sampling compare instruction executes the processing contents as shown in FIG. In the process related to the twice match filter, if the bits 15 and 14 do not match, the contents of the bit 15 are transferred to the bit 14. If the two match, or if filter prohibition is set, the contents of bit 15 are transferred to bits 14 and 13, respectively. Then, when the count value of the program counter 23 becomes greater than or equal to the bit 7: 0 of the register Rm, that is, when the compare period Δt has elapsed, the bit 7: 0 of the register Rn is added to the bit 7: 0 of the register Rm and the next time The compare value is set. When the establishment flag is raised in bit 8, sampling is performed according to the mode specified by bits 10 and 9 of register Rm. The sampling designation is set as follows, for example.
Bit 10, 9 Sampling mode
00 1 bit
01 default
10 1 byte (left shift)
11 1 byte (right shift)
Note that the left shift corresponds to MSB first, and the bit 13 of the register Rm is stored from the bit 8 side of the register Rn while shifting the register Rn to the left bit by bit. The right shift corresponds to LSB first, and the bit 13 of the register Rm is stored from the bit 15 side of the register Rn while the register Rn is shifted right by one bit.

<Output compare instruction>
FIG. 5 shows the contents relating to the output compare instruction. The output compare function performs output from the output terminal every time a designated compare cycle elapses. For example, it is used when outputting a PWM signal or outputting a signal in conjunction with a sleep timer for measuring the time when the microcomputer 10 has shifted to the sleep mode. Also in this case, the count value of the program counter 23 is used as a timer counter.

As shown in FIG. 5A, when the output compare instruction is executed, each bit of the registers Rm and Rn in the general-purpose register 30 is assigned as follows.
Register Rm bit
15: Output terminal level setting
11-9: Designation of output level
8: Output compare establishment flag
7 to 0: Compare value register Rn bit
15 to 8: Output data (1 byte)
7 to 0: Compare cycle

Note that the output designation and the compare cycle are set by another instruction before the output compare instruction is executed. The output compare instruction is executed as follows. First, when the count value of the program counter 23 becomes greater than or equal to bit 7: 0 of the register Rm, that is, when the compare period Δt has elapsed, the bit 7: 0 of the register Rn is added to the bit 7: 0 of the register Rm and the next time The compare value is set. Then, when the establishment flag is set in bit 8, output is performed according to the mode specified by bits 11 to 9 of register Rm. The output level designation is set as follows, for example.
Bits 11-9 Sampling mode
000 No output
001 “L” output
010 “H” output
011 Invert current level
100 No output
101 No output
110 1 byte output (right shift)
111 1 byte output (left shift)
The right shift of 1-byte output corresponds to LSB first. When bit 8 of register Rn is stored in bit 15 of register Rm, bits 15 to 8 of register Rn are shifted right by 1 bit. The left shift of 1-byte output corresponds to MSB first. When bit 15 of register Rn is stored in bit 15 of register Rm, bits 15 to 8 of register Rn are shifted left by 1 bit.

<Input compare set instruction>
FIG. 6 shows the contents relating to the input compare set instruction. The input compare set function sets a compare value when a specified edge of the input terminal 31 is detected. Also in this case, the count value of the program counter 23 is used as a timer counter. The process related to the twice match filter is the same as that in the case of the input capture instruction.

As shown in FIG. 6A, when the input compare set instruction is executed, each bit of the registers Rm and Rn in the general-purpose register 30 is assigned as follows.
Register Rm bit
15: Current input terminal state (level)
14: Previous input terminal state (level)
13: Sampling value (level) of input terminal
11: Double match filter enable / disable
10, 9: Edge specification
8: Input compare set establishment flag
7 to 0: Compare set value register Rn bit
7 to 0: Compare value The edge designation and compare set value are set by another normal instruction before the execution of the input compare set instruction. The input compare set instruction is executed as follows. Note that the process related to the twice match filter is the same as that for the input capture command and the like, and is therefore omitted. First, the contents of bit 15 are transferred to bit 14 respectively. Then, as in the case of the input capture instruction, edge determination is performed on the input terminal 31, and when an edge is detected and the edge condition is satisfied, a value obtained by adding bits 7: 0 of the register Rm to the count value of the program counter 23 is obtained. Set bit 7: 0 of register Rn. Then, an establishment flag is set in bit 8. As shown in FIG. 6C, this input compare set command is used, for example, when the compare set value Δt is set at the time when the falling edge of the signal is detected.

<Conditional sampling instruction>
FIG. 7 shows the contents related to the conditional sampling instruction. The conditional sampling function samples the level of the input terminal 31 when a condition flag is set as a result of some processing. As shown in FIG. 7A, when a conditional sampling instruction is executed, each bit of the register Rm is assigned as follows.
Bit 15: Current input terminal state (level)
14: Previous input terminal state 13: Input terminal sampling value (level)
12: Sampling result (1 bit)
11: Double-match filter enable / disable 10, 9: Sampling designation 8: Conditional sampling establishment flag 7-0: Sampling result (1 bit)
A condition flag is stored in bit 8 of the register Rn. Then, as shown in FIG. 7B, when the condition flag is set, the sampling process is performed together with the twice matching filter process, and when the condition flag is not set, only the twice matching filter process is executed. In any case, the filtering process is performed when the filter permission flag is set, as described above.

  As for the sampling process, when the establishment flag is set in bit 8 of the register Rm, the sampling is performed according to the sampling designation similar to the sampling compare instruction. However, in the case of 1-byte sampling, the sampling result is stored in bits 7 to 0 of the register Rm. FIG. 7C shows a case where sampling is performed on condition that a falling edge of an input terminal 31 is detected, for example.

<Conditional output instruction>
FIG. 8 shows the contents related to the conditional output instruction. The conditional output function outputs a specified level from an output terminal when a condition flag is set as a result of some processing. As shown in FIG. 8A, when a conditional output instruction is executed, each bit of the register Rm is assigned as follows.
Register Rm bit
15: Output terminal level setting
11-9: Designation of output level
8: Output compare establishment flag
7 to 0: Output value (1 byte)
A condition flag is stored in bit 8 of the register Rn. The conditional output instruction is executed as the processing contents shown in FIG. 8B when the condition flag is set in bit 8 of the register Rn. First, when the establishment flag is set in bit 8 of the register Rm, output is performed from the output terminal 32 in accordance with the output designation similar to the output compare instruction. However, in the case of 1-byte output, data set in bits 7 to 0 is given to bit 15 of register Rm while being shifted bit by bit. FIG. 8C shows a case where inverted output, no output, and inverted output are performed on condition that a rising edge of an input terminal 31 is detected, for example.

[Case study: CSMA / CD, reception]
Next, FIG. 9 to FIG. 15 show an example in which a more specific function is realized by using the peripheral function instruction (peripheral instruction) described above. FIG. 9 shows a case where the function on the receiving side is realized for the CSMA / CD system which is one of the communication systems used in the LAN. The functions to be realized are as follows.
(1) When the falling edge of the received data Rx is detected,
Sampling of received data Rx after Δt2 from that point (2) If no edge is detected in the sampling result of (1), the received data Rx is further sampled after Δt1 (one bit period) and if an edge is detected (collision) Detection) Further sampling of received data Rx after Δt2 (bit synchronization)
Bit synchronization is performed as follows.
Previous received data: 0 → Synchronized on falling edge Previous received data: 1 → Synchronized on rising edge Dominant “0” transmitting → Synchronized on falling edge Dominant “1” transmitting → Synchronized on rising edge
<Input compare set instruction>
(1) When the edge of the received data Rx is detected, the sampling timing is changed to Δt2. <Sampling compare instruction>
(2) The reception data Rx can be realized by sampling every Δt1.

[Case study: CSMA / CD, transmission]
FIG. 10 realizes the function on the transmission side in the CSMA / CD system. The contents of the function are as follows.
(1) Transmission data is output at regular intervals (Δt1) (2) Transmission data is output when the received data level changes and an edge is detected.
<Output compare instruction>
(1) Transmission data is output from the output terminal at regular intervals (Δt1).
<Input compare set instruction>
(2a) Detecting edge of received data Rx In this case, when the establishment flag is set in bit 8 of register Rm according to the execution result of the instruction, the content of bit 8 is transferred to bit 8 of register Rn.
<Conditional output instruction>
(2b) By detecting the edge, transmission data can be output from the output terminal and realized by these peripheral function instructions.

[Case study: Event timer]
FIG. 11 implements the event timer function. This feature
(1) A signal edge is detected at the input terminal 31. (2) The level of the input terminal 31 is sampled after Δt from the edge detection.
<Input compare set instruction>
(1) Detect signal edge of input terminal 31 and set compare cycle Δt <Sampling compare command>
(2) The level of the input terminal 31 can be realized by sampling when the compare period Δt has elapsed.

[Case study: Port sampling]
FIG. 12 shows the port sampling function. This feature
(1) A signal is output from the output terminal at an arbitrary timing. (2) When the signal edge of the output terminal is detected, the input terminal 31 is sampled after Δt. The sampling port can be selected from, for example, “32”. These features are
<Output compare instruction>
(1) When the program counter 23 matches a predetermined count value, a signal is output from the output terminal 32 (PSMOUT) <input compare set instruction>
(2a) The compare cycle is set by detecting the edge of the output terminal 32. (2b) When the program counter 23 matches the compare cycle, the input terminal 31 can be realized by sampling.

[Case study: Clock synchronous serial]
FIG. 13 shows a case where the clock synchronous serial communication function is realized. This communication function is as follows.
(1) Signal output (transmission) from output terminal 32 (SOUT) upon detection of falling edge of serial clock SCLK
(2) Sampling (receiving) the input terminal 31 (SIN) by detecting the rising edge of SCLK
Other functions include external clock / internal clock, LSB / MSB first, clock polarity selection, and overrun error detection.

The functions (1) and (2) are realized as follows by peripheral function instructions.
<Input capture instruction>
(1a) SCLK edge (falling, rising) is detected <Conditional output instruction>
(1b) Transmission data is output from the output terminal 32 upon detection of the edge (falling) <Conditional Sampling Instruction>
(2) The input terminal 31 is sampled by detecting the above edge (rising edge).

[Case study: UART]
FIG. 14 shows a case where the UART communication function is realized. This communication function is: (1) Sampling input terminal 31 after Δt from edge detection (falling edge, start bit detection) (2) Thereafter, sampling (receiving) input terminal 31 every (Δt × 2)
Data output (transmission) from the output terminal 32 every (3) or (Δt × 2)
In addition, overrun errors, framing errors, and parity errors are detected.

The functions (1) to (3) are realized as follows by peripheral function instructions.
<Input compare set instruction>
(1) Detect signal edge (rising edge) of terminal and set compare cycle Δt <Sampling compare command>
(2) Sampling the input terminal 31 when the program counters match <Output compare instruction>
(3) When the program counters match (period: Δt × 2), data is output from the output terminal 32

[Case study: LIN]
FIG. 15 shows a case where a bit synchronization function performed at the start of communication is realized in LIN which is a kind of in-vehicle LAN. This function is as follows.
(1) When the fact that the SYNCH BRAKE low level period has reached Δt1 is measured, the start of communication is recognized. (Measure for 4 cycles and divide by “8”)
The functions (1) and (2) are realized as follows by peripheral function instructions.
<Input capture instruction>
The edge of the input terminal 31 is detected and the count value of the program counter 23 is acquired. Other processing can be realized by a normal instruction.

  That is, as described above, communication functions different in a plurality of methods can be realized by software. Therefore, the microcomputer 10 is equipped with a communication interface LSI corresponding to the case where each communication function is realized. There is no need. Therefore, the versatility of the microcomputer 10 can be improved.

  As described above, according to the present embodiment, the CPU 11 of the microcomputer 10 is configured to be able to execute processing with the peripheral function instruction described in the L task as one instruction. The CPU 11 obtains information necessary for executing the peripheral function instruction from the general-purpose register 30 specified by the operand, and stores information related to the execution result of the instruction in the general-purpose register 30. Therefore, the description of the program for realizing the peripheral function by software becomes extremely simple, and the program size can be reduced. Further, since the bits of the general-purpose register 30 can be manipulated by instructions normally prepared in the CPU 11, there is no need to separately prepare special instructions such as prefix instructions in order to execute peripheral function instructions.

  Further, when executing the input capture instruction, the CPU 11 acquires the edge designation information of the input terminal 31 as a timer value acquisition condition from the general-purpose register 30, and acquires the acquisition condition from the state of the input terminal 31 stored in the general-purpose register 30. Is established, the value of the program counter 23 acquired when the condition is established is stored as a capture value, and an establishment flag is stored. Therefore, the input capture function can be realized by software by executing the input capture instruction after the edge designation information is set in the general-purpose register 30 in advance by a normal instruction.

  Further, when executing the sampling compare instruction, the CPU 11 obtains a compare cycle value set in the general-purpose register 30, and uses data obtained by accumulating the compare cycle value in the general-purpose register 30 at each sampling timing as a compare value. Store. When the compare value matches the value of the program counter 23, the sampling result and the establishment flag are stored in the general-purpose register 30. Therefore, the sampling compare function can be realized by software by executing the sampling compare instruction after setting the compare cycle value in the general-purpose register 30 by the normal instruction in advance.

  Further, when executing the input compare set instruction, the CPU 11 obtains the compare cycle value set in the general-purpose register 30 and the edge designation information of the input terminal 31 that becomes the compare set condition. A value obtained by adding the compare cycle value to the value of the program counter 23 is stored in the general-purpose register 30 as a compare value, and an establishment flag is stored. Therefore, an input compare set function can be realized by software by executing an input compare set command after setting a compare cycle value and edge designation information in the general-purpose register 30 in advance by a normal command.

  Further, when executing the conditional sampling instruction, the CPU 11 determines whether or not the condition flag is set in the general-purpose register 30. When the CPU 11 recognizes the setting of the condition flag, the sampling result and the establishment flag are stored in the general-purpose register 30. Accordingly, when a predetermined condition is satisfied while the L task is being executed, a conditional sampling function can be realized by software by setting a condition flag in the general-purpose register 30 with a normal instruction.

  The CPU 11 stores the previous and current states of the input terminal 31 in the general-purpose register 30 when executing an input capture instruction, an input compare instruction, a sampling compare instruction, an input compare set instruction, or a conditional sampling instruction. Because it has a double match filter function that allows the execution of input processing instructions when both values match, the input processing instructions are executed when it is confirmed that the state of the input signal or data is stable. can do. Since the CPU 11 is configured to be able to select whether or not the coincidence filter function can be executed according to the bit setting in the general-purpose register 30, the CPU 11 selects whether or not the multi-function of the fill is necessary according to the user application. Can do.

  Further, when executing the output compare instruction, the CPU 11 obtains a compare cycle value and an output level designation condition set in the general-purpose register 30, and the general-purpose register 30 stores the same compare as in the case of the sampling compare instruction. The value is stored, and if the compare value and the program counter 23 value match, the designated level is output from the output terminal and the establishment flag is stored in the general-purpose register 30. Therefore, the output compare function can be realized by software by executing the output compare instruction after setting the compare cycle value in the general-purpose register 30 by the normal instruction in advance.

  Further, when executing the conditional output instruction, the CPU 11 acquires an output level designation condition set in the general-purpose register 30 and determines whether or not a condition flag is set in the general-purpose register 30. When the condition flag set is recognized, the level corresponding to the specified condition is output to the output terminal and the establishment flag is stored in the general-purpose register 30. Therefore, if a predetermined condition is satisfied while a specific task is executed after an output level specifying condition is set in advance in the general-purpose register 30 by a normal instruction, a condition flag is set in the general-purpose register 30 by a normal instruction. Conditional output function can be realized by software.

The present invention is not limited to the embodiments described above or shown in the drawings, and the following modifications are possible.
A function for setting whether or not to execute the double match filter may be provided as necessary, and a function of the double match filter itself may be provided as necessary.
The number of tasks that the CPU processes in a time-sharing manner may be three or more.
Peripheral function instructions may be realized by appropriately selecting necessary functions according to the specifications of the microcomputer.

1 is a functional block diagram showing a configuration of a microcomputer according to an embodiment of the present invention. Timing chart showing the state in which the microcomputer processes A task and L task in a time-sharing manner Regarding the input capture instruction, (a) the setting state of each bit in the general-purpose register, (b) the contents of the processing executed in the execution stage of the pipeline processing expressed in C language, (c) an example of the execution form Timing chart Figure 3 equivalent diagram of sampling compare instruction Figure 3 equivalent diagram of output compare instruction 3 equivalent diagram of the input compare set instruction Figure 3 equivalent diagram of conditional sampling instructions Figure 3 equivalent diagram of conditional output instructions The figure which shows the case where the function of a receiving side is implement | achieved by a peripheral function command about a CSMA / CD communication system FIG. 9 equivalent diagram of the function on the transmission side Figure 9 equivalent diagram of the event timer function Figure 9 equivalent diagram of the port sampling function Figure 9 equivalent diagram of clock synchronous serial communication function 9 equivalent diagram of the UART communication function FIG. 9 equivalent diagram for realizing the bit synchronization function performed at the start of LIN communication

Explanation of symbols

In the drawing, 10 is a microcomputer, 11 is a CPU, 23 is a program counter, 30 is a general-purpose register, 31 is an input terminal, and 32 is an output terminal.

Claims (9)

In a microcomputer in which a plurality of tasks can be processed in parallel in a time-sharing manner, and at least one of them is a specific task in which a program that loops so that the increment of the instruction address is constant is described.
One of the plurality of programs is described as a specific task in which the increment of the program address is fixed and looped, and the program counter can be used as a timer counter.
In the specific task, peripheral function instructions for executing peripheral functions with one instruction are described.
The peripheral function instruction is set to designate one or more general-purpose registers as operands,
The CPU is configured to be able to execute the peripheral function instruction as one instruction, acquires information necessary for execution of the instruction from the general-purpose register, and stores information on the execution result of the instruction in the general-purpose register. A microcomputer. When executing an input capture instruction as the peripheral function instruction, the CPU acquires edge designation information of an input terminal that is a condition for acquiring a timer value from a general-purpose register,
The general-purpose register stores the level of the input terminal sampled last time and the current level of the input terminal,
2. The microcomputer according to claim 1, wherein when it is determined that the acquisition condition is satisfied based on the previous and current input terminal states, a value of a timer counter is acquired and stored in a general-purpose register as a capture value. When the CPU executes a sampling compare instruction as the peripheral function instruction, the CPU obtains a compare cycle value set in a general-purpose register,
Set the compare value obtained by accumulating the compare cycle value at each sampling timing in the general-purpose register,
3. The comparison value and the timer counter value are compared to determine a match, and when the two match, the state of the input terminal is sampled and stored together with the establishment flag in a general purpose register. The microcomputer as described. The CPU, when executing an input compare set instruction as the peripheral function instruction, obtains a compare set value set in a general-purpose register and edge designation information of an input terminal serving as a compare set condition,
4. The establishment flag is stored together with a compare value obtained by adding a timer counter value at that time to the compare set value when the compare set condition is established. The microcomputer as described. When the CPU executes a conditional sampling instruction as the peripheral function instruction, it recognizes that the condition flag is set in the general-purpose register, and performs sampling of the input terminal.
5. The microcomputer according to claim 1, wherein the sampling result and the establishment flag are stored in a general-purpose register. When the CPU executes an input processing instruction as the peripheral function instruction, the general-purpose register stores the previous input terminal state and the current input terminal state;
6. The microcomputer according to claim 2, further comprising a twice-match filter function that permits execution of the input processing system instruction when both values match.   7. The microcomputer according to claim 6, wherein the CPU is configured to be able to select whether or not to execute the double match filter function according to a bit setting in the general-purpose register. When the CPU executes an output compare instruction as the peripheral function instruction, the CPU obtains a compare cycle value set in a general-purpose register and an output level designation condition,
In the general-purpose register, set the compare value obtained by accumulating the compare cycle value every time the output condition is satisfied,
The compare value and the timer counter value are compared to determine whether they match, and if both match (output condition is established), the level corresponding to the specified condition is output from the output terminal, and the establishment flag is set to a general-purpose register. The microcomputer according to claim 1, wherein the microcomputer is stored in the microcomputer. When executing a conditional output instruction as the peripheral function instruction, the CPU acquires an output level designation condition and a condition flag set in a general-purpose register,
9. When recognizing that the condition flag is set, a level corresponding to the specified condition is output from an output terminal, and the establishment flag is stored in a general-purpose register. Microcomputer.

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