JP2006172331A - Microcontroller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a microcontroller capable of diagnosing a peripheral module without applying a load to a CPU. <P>SOLUTION: In the microcontroler having the CPU 10, a ROM 20 and a RAM 21 which store an instruction executed by the CPU and data, peripheral modules 60, 61, 62, a CPU bus 70 to which the CPU, the ROM and the RAM are connected, a peripheral bus to which the peripheral modules are connected and a bus bridge 30 which connects the CPU bus with the peripheral bus, it has a RAM 50 connected to the peripheral bus and a diagnostic module 40 which reads a diagnostic program stored in the RAM and performs processing, the diagnostic module 40 reads a register of the peripheral module whose address is specified by the diagnostic program, compares comparison data to be specified by the diagnostic program with a value of the register of the peripheral module based on comparison conditions to be specified by the diagnostic program and outputs a signal indicating whether or not the comparison conditions are established. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a microcontroller, and more particularly to a technique effective when applied to a microcontroller used in a control device that requires high reliability.

  For example, a microcontroller (hereinafter referred to as a “microcomputer”) is incorporated in a device such as a home appliance, an AV device, a mobile phone, an automobile, or an industrial machine, and performs processing according to a program stored in a memory. It is a device that controls equipment.

  This microcomputer is required to have a performance necessary for controlling the device and to be inexpensive because of its nature of being incorporated in the device and used. Furthermore, there is a strong demand for reliability to operate normally under operating conditions where operation is guaranteed.

  In addition to the CPU and memory, the microcomputer is equipped with a large number of various types of peripheral modules such as a timer, A / D conversion, and communication. Conventionally used high reliability technologies include ECC, parity check, and software self-diagnosis. In the ECC and parity check, redundant bits are added to a storage element such as a memory so that when data stored in the storage element is broken, this is corrected at the time of reading or an error is detected. The software self-diagnosis is to check whether the CPU itself, the memory, and the peripheral modules function correctly by executing the program of the CPU. Software self-diagnosis is widely applied because it only needs a program for diagnosis. ECC and parity check are applied in fields where the environment used for automobile engine control is severe and reliability is particularly required.

  By the way, among the conventional diagnostic techniques, software self-diagnosis can be realized only by a program, and no special hardware is required. However, since this is done by executing the program of the CPU, the processing capability assigned to the original device control is reduced. In other words, in order not to reduce the processing capability of device control, a high-performance microcomputer that adds the performance necessary for software self-diagnosis is necessary, which increases the cost. Or it is necessary to give priority to cost and to suppress the processing of the diagnostic program within a range that the processing capability of the microcomputer to be used is sufficient.

  In addition, since ECC and parity check perform error correction and error detection with a dedicated logic circuit, no load is imposed on the processing of the CPU. However, the object of diagnosis is limited to the memory element. In addition, a logic circuit that performs error correction and error detection is required.

  As described above, when the peripheral module is diagnosed using the conventional technique, the method based on the software self-diagnosis has a problem that the processing load of the CPU increases. In the method based on ECC or parity check, a dedicated logic circuit is required, and peripheral modules designed for a microcomputer that does not require these circuits cannot be reused. In addition, there is a limitation that the object of diagnosis is limited to the memory element.

  Therefore, an object of the present invention is to solve the above-described problems and provide a technique for diagnosing peripheral modules without applying a processing load to a CPU.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  To achieve the above object, the present invention provides a CPU, a first memory for storing instructions and data executed by the CPU, a peripheral module having functions such as a timer, A / D conversion, and communication, a CPU, In a configuration having a CPU bus to which one memory is connected, a peripheral bus to which a peripheral module is connected, and a bus bridge for connecting the CPU bus and the peripheral bus when the CPU accesses the peripheral module, A second memory connected to the bus; and a diagnostic module for reading and processing a diagnostic program stored in the second memory. With this configuration, the diagnostic module reads the register of the peripheral module addressed by the diagnostic program, and based on the comparison condition specified by the diagnostic program, the comparison data specified by the diagnostic program and the register value of the peripheral module And a signal indicating whether or not this comparison condition is satisfied is output. As described above, by determining whether or not the diagnostic module matches the condition defined in the diagnostic program, the peripheral module can be diagnosed without imposing a load on the CPU.

  Further, the present invention further determines whether or not the diagnostic module matches a condition defined in the diagnostic program by a configuration having an interrupt controller that notifies the CPU of an interrupt request, and if the comparison condition is not satisfied The diagnostic error interrupt request is output to the interrupt controller, the interrupt controller notifies the CPU of the diagnostic error interrupt from the diagnostic module, and the CPU can execute the program processing corresponding to the diagnostic error interrupt.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the present invention, it is possible to diagnose peripheral modules without imposing a load on the CPU.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  The concept of the present invention is applied to a microcomputer that performs processing in accordance with a program (instruction), a CPU that processes the program, a first memory that stores the program and data, and a CPU that reads the program and reads and writes data. A CPU bus connection system comprising a CPU bus, a peripheral bus connection system comprising a peripheral module having functions such as a timer, A / D conversion, communication, etc., and a peripheral bus for reading and writing data to and from the peripheral module; In a configuration having a CPU bus and a bus bridge for connecting the peripheral bus when the CPU accesses the peripheral module, the second memory is connected to the peripheral bus and stores the diagnostic program of the peripheral module, and connected to the peripheral bus The diagnostic program is read and decoded, and the peripheral module registers are read and diagnosed. It determines whether to match the conditions programmed defined, and has a diagnostic module having a function of outputting a result. In addition, it has an interrupt controller that notifies the CPU of an interrupt request, and determines whether or not the diagnostic module matches the conditions defined in the diagnostic program. A request is output, the interrupt controller notifies the CPU of a diagnostic error interrupt from the diagnostic module, and the CPU executes a program process corresponding to the diagnostic error interrupt. This will be described in detail below.

  FIG. 1 is a block diagram for explaining a microcomputer according to an embodiment to which the present invention is applied.

  The microcomputer 1 of the present embodiment includes a CPU 10 that executes a program, a ROM 20 and a RAM (1) 21 that function as a first memory that stores programs and data, and a CPU bus 70 to which the CPU 10, the ROM 20, and the RAM 21 are connected. And peripheral modules (1) 60, (2) 61, (N) 62 having functions such as a timer, A / D conversion, and communication, and a second memory for storing diagnostic programs for the peripheral modules 60, 61, 62 A RAM (2) 50 that functions as: a diagnostic module 40 that reads and processes a diagnostic program stored in the RAM 50; a peripheral bus 60 to which the peripheral modules 60, 61, 62 and the RAM 50 and the diagnostic module 40 are connected; A bus bridge 30 connecting the CPU bus 70 and the peripheral bus 80, and a peripheral bus 80 Is connected to the CPU 10 and the diagnostic module 40, the interrupt controller 90 notifies the interrupt request to the CPU 10, is connected to the peripheral bus 80, and includes a like external bus controller 91 for inputting and outputting data with the outside.

  The microcomputer 1 is connected to the external bus 2 through the external bus controller 91, the peripheral module 62 is connected to the network 3 through a communication terminal, and the peripheral module 61 is connected to the sensor 4 through an analog input terminal.

  The CPU bus 70 is a bundle of signal lines used by the CPU 10 to perform access for program reading and data input / output, and includes information on commands, addresses, and data indicating access types.

  The peripheral bus 80 is a bundle of signal lines used for reading and writing to the RAM 50 and accessing for reading and writing of registers included in the peripheral modules 60, 61 and 62.

  The bus bridge 30 has a function of connecting the CPU bus 70 and the peripheral bus 80 and transferring commands, addresses, and data when the CPU 10 accesses the diagnostic module 40, the RAM 50, and the peripheral modules 60, 61, and 62.

  The diagnostic module 40 reads and decodes the diagnostic program stored in the RAM 50, reads the registers included in the peripheral modules 60, 61, and 62, determines whether or not the conditions defined in the diagnostic program are met, Output the result. The determination result of the diagnostic module is input to, for example, the interrupt controller 90. If the determination results do not match, it is considered that the register value of the peripheral module is invalid and the CPU 10 executes interrupt processing. .

  FIG. 2 is a block diagram for explaining the main functions of the diagnostic module 40 in FIG.

  The control status register 400 is a register for controlling the operation of the diagnostic module 40 and knowing the status. The diagnostic program address register 401 is a register that holds the address of the diagnostic program. The diagnosis target address register 402 is a register that holds the addresses of peripheral module registers to be diagnosed. The diagnosis target data register 403 is a register that holds data of peripheral module registers to be diagnosed. The comparison data register 404 is a register that holds data to be compared with the diagnosis target data register 403. The mask data register 405 is a register that designates a bit to be compared between the diagnosis target data register 403 and the comparison data register 404. The comparison condition register 406 is a register that holds comparison conditions of the diagnosis target data register 403 and the comparison data register 404.

  These registers are accessed using the peripheral bus 80 in FIG. Reference numeral 8003 denotes a data bus of the peripheral bus 80, which is connected to a register write terminal of the diagnostic module 40. In the diagnostic program address register 401, in addition to writing from the peripheral bus 80, the diagnostic program address generated by the diagnostic module 40 is written. Reference numeral 411 denotes a diagnostic program address generation circuit which inputs data 4010 in the diagnostic program address register 401 and generates the next diagnostic program address 4110. Reference numeral 410 denotes a diagnostic program address write data selection circuit, and the output data 4100 serves as write data to the diagnostic program address register 401. The diagnosis module output data selection circuit 413 selects data from the control state 4000, the diagnosis program address 4010, the diagnosis object address 4020, the diagnosis object data 4030, the comparison data 4040, the mask data 4050, and the comparison condition 4060, and the diagnosis module read data 4130. Is output. The diagnostic module read data 4130 is output to the peripheral bus data 8003 via the buffer 422.

  The comparison circuit 432 compares the result 4300 obtained by calculating the diagnosis target data 4030 and the mask data 4050 by the mask circuit 430 and the result 4310 obtained by calculating the comparison data 4040 and the mask data 4050 by the mask circuit 431 based on the comparison condition 4060. The comparison result 4320 is output. Mask operations in the mask circuits 430 and 431 can be performed by logical product of input data.

  The control logic 440 controls data reading and writing for the access of the register of the diagnostic module 40 from the peripheral bus 80, and controls the execution of the diagnostic program. In accessing from the peripheral bus 80, the peripheral bus command 8001 is input, and the operations of no access, read and write are decoded. In addition, the peripheral bus address 8002 is input to determine the register to be accessed. When executing the diagnostic program, the diagnostic module 40 accesses the peripheral bus 80. When the peripheral bus request signal 4401 is output and the peripheral bus request response signal 8000 indicating permission of use of the peripheral bus is returned, the peripheral bus access is started. The peripheral bus command 4400 generated by the control logic 440 is output to the peripheral control bus 8001 through the bus driver 420. When reading the diagnostic program, the diagnostic program address 4010 is selected by the selection circuit 412, and the selected signal 4120 is output to the peripheral address bus 8002 through the bus driver 421. When reading the peripheral module register to be diagnosed, the diagnosis target address 4020 is selected by the selection circuit 412, and the selected signal 4120 is output to the peripheral address bus 8002 through the bus driver 421. In the execution of the diagnosis program, when a program indicating the end of diagnosis is executed, a diagnosis end interrupt signal 4402 can be output. If the comparison result 4320 indicates a mismatch, a diagnostic error interrupt signal 4403 can be output.

  FIG. 3 is a diagram showing the format of the diagnostic program. (1) is a format for designating the address of the diagnostic program to be read next. That is, it is a format for setting the address of the diagnostic program, and consists of an 8-bit command portion and a 32-bit diagnostic program address portion. (2) is a format for designating the address of the peripheral module register to be read and the data to be compared with the value of the peripheral module register. That is, it is a format for setting a method for comparing peripheral module registers, and consists of an 8-bit command portion, a 32-bit diagnosis target address portion, and a D-bit comparison data portion. (3) is a format for designating the address of the peripheral module register to be read, the data to be compared with the value of the peripheral module register, and the mask data for designating the bit to be compared with the peripheral module register. That is, it is a format for setting a comparison method with a mask of a peripheral module register, and consists of an 8-bit command portion, a 32-bit diagnosis target address portion, a D-bit comparison data portion, and a D-bit mask data portion. (4) is a format for designating the termination of the diagnostic module processing. That is, it is a format for setting the end of the diagnostic program execution, and consists of an 8-bit command part.

  FIG. 4 is a diagram illustrating a command format of the diagnostic program in FIG. In FIG. 4, 2-bit TP1 and TP0 are information for identifying which of the formats (1) to (4) in FIG. That is, it is a field representing the command type, and its value and meaning are shown in FIG. When the value is 00, the format of the diagnostic program is the diagnostic program address setting format (1) in FIG. When the value is 01, the format of the diagnosis program is the diagnosis end format (4) in FIG. When the value is 10, the format of the diagnostic program is the comparison format (2) in FIG. When the value is 11, the format of the diagnostic program is a comparison format with a mask (3) in FIG.

  In FIG. 4, 2-bit SZ1 and SZ0 are information indicating the bit length of the peripheral module register to be read in the case of any of the formats (2) and (3) in FIG. That is, it is a field that represents the size of the diagnosis target data, specifies the bit size D of the comparison data in the comparison format (2) in FIG. Specify D. The values and meanings of SZ1 and SZ0 are shown in FIG. A value of 00 indicates that the data size is 8 bits. A value of 01 indicates that the data size is 16 bits. A value of 11 indicates that the data size is 32 bits. When the value is 10, the data size is undefined. In the case of the diagnostic programs of the formats (2) and (3) that refer to the comparison data in FIG. 3, SZ1 and SZ0 must be one of 00, 01, and 11 values. In the case of the diagnostic programs of the formats (1) and (4), SZ1 and SZ0 have no meaning and may be any value.

  In FIG. 4, 2-bit CM1 and CM0 are matched, mismatched, large or small as comparison conditions for the peripheral module register and the comparison data in the case of any of the formats (2) and (3) in FIG. Information to be specified. That is, it is a field that represents a comparison condition of diagnosis target data, and its value and meaning are shown in FIG. When the value is 00, the comparison condition is “the diagnosis target data matches the comparison data”. When the value is 01, the comparison condition is “the diagnosis target data does not match the comparison data”. When the value is 10, the comparison condition is “the diagnosis target data is larger than the comparison data”. When the value is 11, the comparison condition is “the diagnosis target data is smaller than the comparison data”. In the case of the diagnostic programs of the types (1) and (4) that do not perform comparison in FIG. 3, CM1 and CM0 have no meaning and may be any value.

  In FIG. 4, 1-bit UPT is stored in the register of the peripheral module read out by the diagnostic module 40 after the diagnostic program is executed in the case of any of the formats (2) and (3) in FIG. This is information specifying whether or not to write the value of the specified comparison data. That is, it is a bit indicating whether or not the diagnosis target register is updated to the value of the comparison data after execution of the diagnostic program, and its value and meaning are shown in FIG. When the value is 0, it indicates that the update is not performed, and when the value is 1, it indicates that the comparison data is overwritten. In the case of the diagnostic programs of the types (1) and (4) that do not perform comparison in FIG. 3, UPT has no meaning and may be any value.

  In FIG. 4, the 1-bit UPE is compared with the comparison data designated by the diagnostic program in the RAM 50 after the diagnostic module 40 executes the diagnostic program in the case of any of the formats (2) and (3) in FIG. This is information for designating whether or not to write the value of the read peripheral module register. That is, it is a bit indicating whether or not the comparison data part in the diagnostic program is updated to the value of the diagnosis target data after execution of the diagnostic program, and its value and meaning are shown in FIG. When the value is 0, it indicates that updating is not performed, and when the value is 1, it indicates that the diagnosis target data is overwritten. In the case of the diagnostic programs of the types (1) and (4) that do not perform comparison in FIG. 3, UPE has no meaning and may be any value.

  FIG. 10 is a diagram showing details of the control state register 400 in FIG. EX, IED, IER, and WCY of bits 15 to 8 are control bits for setting the operation of the diagnostic module 40 and are written by the CPU 10.

  EX is called a diagnostic enable bit, and is stored in a register for designating execution of processing by reading a program stored in the RAM 50, and can be set to any value from the CPU 10 where diagnosis can be executed and where diagnosis cannot be executed. It is. 1 is written when the diagnostic module 40 wants to execute the diagnostic program. When the EX bit is rewritten from 1 to 0, the currently running diagnostic program is terminated and then the stopped state is entered.

  The IED is called a diagnosis end interrupt enable bit, and whether or not to output the fact that the diagnosis has ended when a program of a format that specifies the end of the processing of the diagnosis module 40 stored in the RAM 50 is read. Can be read from and written to by the CPU 10. 1 is written when an interrupt signal is to be generated after executing the program of the diagnosis end format (4) in FIG.

  The IER is called a diagnostic error interrupt enable bit and executes a program in the format (2) or (3) in FIG. 3 stored in the RAM 50, and diagnoses when the diagnostic conditions specified by the program are not satisfied. It is stored in a register for designating whether or not to output an error interrupt signal, and can be read and written from the CPU 10. The diagnostic program in the format (2) and (3) in FIG. 3 is executed, and 1 is written when it is desired to generate an interrupt when the comparison results do not match.

  WCY is called a wait cycle number field, is stored in a register for setting the number of wait cycles until the next diagnostic program is read after execution of the diagnostic program, and can be read and written from the CPU 10. Specifies the number of wait cycles that occur between diagnostic programs. The relationship between the value of WCY and the number of wait cycles may be determined as appropriate in the microcomputer to which the present invention is applied. For example, the number of wait cycles may be 2 to the power of WCY.

  Bits 3 to 1 of FEX, FED, and FER are bits representing the state of the diagnostic module 40.

  The FEX is called a diagnostic execution flag, and is stored in a register for indicating whether or not processing is being executed by reading a program stored in the RAM 50, and can be read from the CPU 10. 1 is read when the diagnostic module 40 is executing the diagnostic program, and 0 is read when the diagnostic module 40 is in the stopped state.

  The FED is called a diagnosis end flag, is stored in a register for indicating whether or not the diagnosis is completed, and can be read from the CPU 10. The value is set to 1 after the diagnosis module 40 executes the program of the diagnosis end type (4) in FIG.

  The FER is called a diagnostic error flag, is stored in a register for indicating whether or not a diagnostic error has occurred, and can be read and written from the CPU 10. This is set to 1 when the diagnostic programs of the formats (2) and (3) in FIG. 3 are executed and the results do not match.

  Bits 7 to 4 and bit 0 RSV are reserved bits.

  FIG. 11 is a flowchart showing the processing of the diagnostic module 40. First, it is determined whether or not diagnosis is possible (S1). Whether or not diagnosis is possible is determined using the control status register 400 of FIG. Diagnosis is possible when EX = 1, FED = 0, and FER = 0. That is, if the diagnosis program execution is permitted by EX = 1, the diagnosis is not completed by FED = 0, and no diagnosis error has occurred by FER = 0, the diagnosis program can be executed. . Under conditions other than the above, the diagnostic module 40 is in a standby state.

  When the diagnosis is possible (Y), the diagnosis module 40 reads the diagnosis program stored in the RAM 50 (S2). The diagnostic program command is analyzed (S3), and each process is performed when the format is comparison or comparison with mask, address setting, or diagnosis end.

  In the case of comparison or comparison with mask, the diagnosis target address, comparison data, and mask data following the command are read (S4), then the peripheral module register is read (S5), and compared with the comparison data (S6). If they match, the process proceeds to the next wait process (S10). If they do not match, the FER of the control status register is set to 1 (S7), and the process proceeds to the wait process (S10). At this time, if IER of the control status register is set to 1, a diagnostic error interrupt is generated.

  When the command is an address setting, the diagnostic program address following the command is read out, set in the diagnostic program address register 401 in FIG. 2 (S8), and the process proceeds to the next wait process (S10).

  If the command is a diagnosis end, the FED of the control status register is set to 1 (S9), and the process proceeds to the next wait process (S10).

  In the wait process (S10), a wait state is established for the number of cycles determined by WCY in the control state register 400 of FIG. 10, and the process returns to the determination process (S1) as to whether diagnosis is possible.

  FIG. 12 is a time chart showing the operation of the peripheral bus 80 when the diagnostic program is executed. When the diagnosis module 40 is ready for diagnosis, the diagnosis module 40 outputs a peripheral bus request to the bus bridge 30 which is the bus master of the peripheral bus 80. The bus bridge 30 returns a peripheral bus request response at a timing when the bus right of the peripheral bus 80 can be passed. In response to this, the diagnosis module 40 starts accessing the peripheral bus 80. The diagnostic program i has the comparison form (2) in FIG. 3, and reads the command PiR1, the diagnostic target address PiR2, and the comparison data PiR3 from the RAM 50, and then reads the diagnostic target data DiR1 from the peripheral module register indicated by the diagnostic target address. . When the execution of the diagnostic program i is finished, the process enters a wait process, and the next diagnostic program j is executed.

  FIG. 13 is a time chart showing the case where the comparison result is inconsistent and a diagnostic error interrupt occurs when the diagnostic program is executed. The diagnostic program k is a comparison format with a mask (3) in FIG. 3, and reads the command PkR1, the diagnostic target address PkR2, the comparative data PkR3, and the mask data PkR4 from the RAM 50, and then from the peripheral module register indicated by the diagnostic target address. The diagnosis target data DkR1 is read out. A diagnostic error interrupt is output because the result of the masked comparison did not match.

  FIG. 14 is a time chart showing the case where the diagnostic program address setting format (1) in FIG. 3 is executed. The diagnostic program n has the diagnostic program address setting format (1) in FIG. 3, and reads the command PnR1 and the diagnostic program address PnR2 from the RAM 50. PnR2 is set in the diagnostic program address register 401 in FIG. After execution of the diagnostic program n, a wait process is started, and the command P1R1 of the diagnostic program 1 is read using PnR2 as an address.

  FIG. 15 is a diagram showing an example of a diagnostic program stored in the RAM 50 in FIG. In FIG. 15, one column of data is 1 byte. The diagnostic program 1 is a comparison format with a mask, and includes a 1-byte command 1, a 4-byte diagnosis target address 1, a 1-byte comparison data 1, and a 1-byte comparison mask data 1. Although the diagnostic program 2 is also a comparison format with a mask, the size of the comparison data and the comparison mask data is 2 bytes. The diagnosis program n has a diagnosis target address setting format, and includes a 1-byte command n and a 4-byte diagnosis target address n. If the value of the diagnosis target address n is the address of the command 1 of the diagnosis program 1, the diagnosis program 1 to the diagnosis program n can be executed infinitely.

  FIG. 16 is a block diagram for explaining a microcomputer according to another embodiment to which the present invention is applied.

  The microcomputer 1 of this embodiment is configured by connecting an external ROM 5 to the external bus 2 instead of the ROM 20 in FIG. Other configurations are the same as those in FIG.

  The CPU 10 executes the program by reading instructions and data from the ROM 5 via the external bus 2. The ROM 5 also stores a program executed by the diagnostic module 40. The diagnostic module 40 can read and execute a diagnostic program from the ROM 5, or can read and execute the diagnostic program from the RAM 50 by transferring the diagnostic program from the ROM 5 to the RAM 50 after resetting the microcomputer 1, for example. .

  As described above, according to the microcomputer 1 of each of the above-described embodiments (FIGS. 1 and 16), the peripheral module 60, 61, 62 is connected to the peripheral bus 80 different from the CPU bus 70 to which the CPU 10 is connected. The diagnostic module 40 reads out and decodes the diagnostic program from the RAM 50, and reads the diagnostic program stored in the RAM 50. The peripheral module 60 reads out the diagnostic program from the RAM 50. , 61, 62 can be read out and diagnosis can be performed by determining whether or not the conditions defined in the diagnostic program are met, so that the peripheral modules 60, 61, and 62 can be controlled without imposing a load on the CPU 10. Diagnosis can be made.

  In contrast to the present embodiment, for example, in the microcomputer 1 of the prior art (FIG. 17) that does not have a diagnostic module, there is no RAM 50 and diagnostic module 40 connected to the peripheral bus 80. Therefore, when the CPU 10 diagnoses the registers of the peripheral modules 60, 61, and 62 by software processing, the diagnostic program is prepared in the RAM 21, and the CPU 10 reads the comparison program and the peripheral module registers for comparison. Can be realized. However, since the peripheral bus 80 is operated with a low-speed clock as compared with the CPU bus 70, many wait cycles are entered when the CPU 10 accesses the peripheral module. Further, when the peripheral module diagnosis is started by an interrupt, an overhead of interrupt processing is added. Although there existed such a subject in the prior art, in this Embodiment, these subjects can be solved as mentioned above.

  Furthermore, according to the present embodiment, by having the interrupt controller 90 that notifies the CPU 10 of an interrupt request, it is determined whether or not the diagnostic module 40 matches the conditions defined in the diagnostic program, and the comparison condition is not satisfied. In this case, a diagnostic error interrupt request is output to the interrupt controller 90, the interrupt controller 90 notifies the diagnostic error interrupt from the diagnostic module 40 to the CPU 10, and the CPU 10 executes a program process corresponding to the diagnostic error interrupt. it can.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention relates to a microcomputer, and is particularly effective when applied to a microcomputer used in a control device that requires high reliability.

It is a block diagram for demonstrating the microcomputer of one Embodiment to which this invention is applied. FIG. 2 is a block diagram for explaining main functions of a diagnostic module in FIG. 1 in an embodiment to which the present invention is applied. In one Embodiment to which this invention is applied, it is a figure which shows the format of a diagnostic program. FIG. 4 is a diagram showing a command format of the diagnostic program in FIG. 3 in an embodiment to which the present invention is applied. FIG. 5 is a diagram showing values and meanings of TP1 and TP0 fields representing command formats in FIG. 4 in an embodiment to which the present invention is applied. In one Embodiment to which this invention is applied, it is a figure which shows the value and meaning of the SZ1, SZ0 field showing the size of diagnostic object data in FIG. FIG. 5 is a diagram showing values and meanings of CM1 and CM0 fields representing comparison conditions of diagnosis target data in FIG. 4 in an embodiment to which the present invention is applied. FIG. 5 is a diagram illustrating the value and meaning of a UPT bit indicating whether or not a diagnosis target register is updated to a value of comparison data after execution of a diagnosis program in FIG. 4 in an embodiment to which the present invention is applied. FIG. 5 is a diagram showing the value and meaning of a UPE bit indicating whether or not the comparison data portion in the diagnostic program is updated to the value of the diagnosis target data after execution of the diagnostic program in FIG. 4 according to an embodiment to which the present invention is applied. is there. FIG. 3 is a diagram showing details of a control state register in FIG. 2 in an embodiment to which the present invention is applied. In one embodiment to which the present invention is applied, it is a flow chart which shows processing of a diagnostic module. In one embodiment to which the present invention is applied, it is a time chart which shows operation of a peripheral bus at the time of execution of a diagnostic program. 7 is a time chart showing a case where a comparison result is inconsistent and a diagnostic error interrupt occurs when a diagnostic program is executed in an embodiment to which the present invention is applied. FIG. 4 is a time chart showing a case where a diagnostic program address setting format (1) in FIG. 3 is executed in an embodiment to which the present invention is applied. FIG. 2 is a diagram illustrating an example of a diagnostic program stored in a RAM in FIG. 1 in an embodiment to which the present invention is applied. It is a block diagram for demonstrating the microcomputer of another embodiment to which this invention is applied. It is a block diagram for demonstrating the microcomputer of a prior art which does not have a diagnostic module with respect to this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Microcomputer, 2 ... External bus, 3 ... Network, 4 ... Sensor, 5 ... ROM, 10 ... CPU, 20 ... ROM, 21 ... RAM, 30 ... Bus bridge, 40 ... Diagnostic module, 50 ... RAM, 60, 61 62 ... Peripheral module, 70 ... CPU bus, 80 ... Peripheral bus, 90 ... Interrupt controller, 91 ... External bus controller, 400 ... Control status register, 401 ... Diagnostic program address register, 402 ... Diagnosis target address register, 403 ... Diagnosis Target data register 404 ... Comparison data register 405 ... Mask data register 406 ... Comparison condition register 410 ... Selection circuit 411 ... Diagnostic program address generation circuit 412 ... Selection circuit 413 ... Diagnostic module output data selection circuit 420 421 Bus driver 422 Bar Fa, 430, 431 ... masking circuit, 432 ... comparison circuit 440 ... control logic.

Claims (21)

A CPU, a first memory for storing instructions and data executed by the CPU, a peripheral module, a CPU bus to which the CPU and the first memory are connected, and a peripheral bus to which the peripheral module is connected A microcontroller having a bus bridge for connecting the CPU bus and the peripheral bus when the CPU accesses the peripheral module;
A second memory connected to the peripheral bus; and a diagnostic module for reading and processing a diagnostic program stored in the second memory;
The diagnostic module reads the register of the peripheral module addressed by the diagnostic program, and compares the comparison data specified by the diagnostic program and the register of the peripheral module based on the comparison condition specified by the diagnostic program. A microcontroller that compares a value and outputs a signal indicating whether or not the comparison condition is satisfied. A CPU, a first memory for storing instructions and data executed by the CPU, a peripheral module, an interrupt controller for notifying the CPU of an interrupt request, and a CPU bus to which the CPU and the first memory are connected And a peripheral bus to which the peripheral module is connected, and a bus bridge that connects the CPU bus and the peripheral bus when the CPU accesses the peripheral module,
A second memory connected to the peripheral bus; and a diagnostic module for reading and processing a diagnostic program stored in the second memory;
The diagnostic module reads the register of the peripheral module addressed by the diagnostic program, and compares the comparison data specified by the diagnostic program and the register of the peripheral module based on the comparison condition specified by the diagnostic program. Value is compared to determine whether this comparison condition is satisfied, and if the comparison condition is not satisfied, a diagnostic error interrupt request is output to the interrupt controller,
The interrupt controller notifies the CPU of a diagnostic error interrupt from the diagnostic module;
The microcontroller executes a program process corresponding to the diagnostic error interrupt. The microcontroller according to claim 1 or 2,
The microcontroller includes a format for specifying an address of a peripheral module register to be read and data to be compared with a value of the peripheral module register. The microcontroller according to claim 1 or 2,
The diagnostic program includes a format for designating an address of a peripheral module register to be read, data to be compared with a value of the peripheral module register, and mask data for designating a bit to be compared with the peripheral module register. Microcontroller. The microcontroller according to claim 1 or 2,
The microcontroller includes a format for designating an address of a diagnostic program to be read next. The microcontroller according to claim 1 or 2,
The microcontroller characterized in that the diagnostic program includes a format for designating the termination of the processing of the diagnostic module. The microcontroller according to claim 1 or 2,
The diagnostic program includes:
A format for designating the address of the peripheral module register to be read and the data to be compared with the value of the peripheral module register;
A format for designating an address of a peripheral module register to be read, data to be compared with the value of the peripheral module register, and mask data for designating a bit to be compared with the peripheral module register;
The format to specify the address of the diagnostic program to be read next,
A microcontroller having information for identifying which format is designated to end the processing of the diagnostic module, and which format is designated. The microcontroller according to claim 1 or 2,
The diagnostic program includes:
A format for designating the address of the peripheral module register to be read and the data to be compared with the value of the peripheral module register;
In the case of any one of the formats for specifying the address of the peripheral module register to be read, the data to be compared with the value of the peripheral module register, and the mask data for specifying the bit to be compared with the peripheral module register, A microcontroller having information indicating a bit length of a peripheral module register to be read. The microcontroller according to claim 1 or 2,
The diagnostic program includes:
A format for designating the address of the peripheral module register to be read and the data to be compared with the value of the peripheral module register;
In the case of any one of the formats for specifying the address of the peripheral module register to be read, the data to be compared with the value of the peripheral module register, and the mask data for specifying the bit to be compared with the peripheral module register, A microcontroller having information specifying match, mismatch, large, or small as a comparison condition between a peripheral module register and comparison data. The microcontroller according to claim 1 or 2,
The diagnostic module includes the diagnostic program,
A format for designating the address of the peripheral module register to be read and the data to be compared with the value of the peripheral module register;
In the case of any one of the formats for specifying the address of the peripheral module register to be read, the data to be compared with the value of the peripheral module register, and the mask data for specifying the bit to be compared with the peripheral module register, A microcontroller having a function of writing a value of comparison data designated by the diagnostic program into a register of a read peripheral module after the diagnostic program is executed. The microcontroller according to claim 1 or 2,
The diagnostic program includes:
A format for designating the address of the peripheral module register to be read and the data to be compared with the value of the peripheral module register;
In the case of any one of the formats for specifying the address of the peripheral module register to be read, the data to be compared with the value of the peripheral module register, and the mask data for specifying the bit to be compared with the peripheral module register, A microcontroller comprising: information specifying whether or not to write a value of comparison data specified by the diagnostic program into a register of a peripheral module that has been read after the diagnostic module has executed the diagnostic program. The microcontroller according to claim 1 or 2,
The diagnostic module includes the diagnostic program,
A format for designating the address of the peripheral module register to be read and the data to be compared with the value of the peripheral module register;
In the case of any one of the formats for specifying the address of the peripheral module register to be read, the data to be compared with the value of the peripheral module register, and the mask data for specifying the bit to be compared with the peripheral module register, A microcontroller having a function of writing a read register value of a peripheral module into comparison data designated by the diagnostic program in the second memory after execution of the diagnostic program. The microcontroller according to claim 1 or 2,
The diagnostic program includes:
A format for designating the address of the peripheral module register to be read and the data to be compared with the value of the peripheral module register;
In the case of any one of the formats for specifying the address of the peripheral module register to be read, the data to be compared with the value of the peripheral module register, and the mask data for specifying the bit to be compared with the peripheral module register, The diagnostic module has information for designating whether or not to write the value of the register of the read peripheral module into the comparison data designated by the diagnostic program in the second memory after the diagnostic program is executed. Microcontroller. The microcontroller according to claim 1 or 2,
The diagnostic module includes a diagnostic enable register for designating that the program stored in the second memory is read and the process is executed, and the diagnostic enable register can perform diagnostic execution from the CPU and perform diagnostic execution. A microcontroller that can be set to any of the impossible values. The microcontroller according to claim 1 or 2,
The diagnostic module includes a diagnostic execution status register for indicating whether the program stored in the second memory is read and processing is being executed, and the diagnostic execution status register is the CPU A microcontroller which can be read from The microcontroller according to claim 1 or 2,
The diagnostic module has a signal for outputting to the outside that the diagnosis has been completed when a program stored in the second memory is designated so that the process of the diagnostic module is to be terminated. A microcontroller characterized by The microcontroller according to claim 1 or 2,
Whether or not to output the fact that the diagnosis has been completed to the outside when the diagnostic module reads out a program stored in the second memory that specifies the termination of the processing of the diagnostic module A microcontroller comprising a diagnostic end interrupt enable register for designating, wherein the diagnostic end interrupt enable register is readable and writable from the CPU. The microcontroller according to claim 1 or 2,
2. The microcontroller according to claim 1, wherein the diagnostic module includes a diagnostic end status register for indicating whether or not the diagnosis is completed, and the diagnostic end status register can be read from the CPU. The microcontroller according to claim 1 or 2,
The diagnostic module is stored in the second memory,
A format for designating the address of the peripheral module register to be read and the data to be compared with the value of the peripheral module register;
Execute a program in one of the formats: specifying the address of the peripheral module register to be read, the data to be compared with the value of the peripheral module register, and the mask data specifying the bit to be compared in the peripheral module register A diagnostic error interrupt enable register for designating whether or not to output a diagnostic error interrupt signal when a diagnostic condition designated by the program is not satisfied, and the diagnostic error interrupt enable register is read from the CPU And a writable microcontroller. The microcontroller according to claim 1 or 2,
The microcontroller, wherein the diagnostic module has a diagnostic error status register for indicating whether or not a diagnostic error has occurred, and the diagnostic error status register is readable and writable from the CPU. The microcontroller according to claim 1 or 2,
The diagnostic module has a wait cycle register for setting the number of wait cycles until the next diagnostic program is read after execution of the diagnostic program, and the wait cycle register is readable and writable from the CPU. A microcontroller to do.

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