JP2006004918A - Liquid crystal display system with lamp feedback - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display system and a CCFL power converter circuit by using a high-efficiency zero-voltage switching technique that eliminates a switching loss related to power MOSFETs. <P>SOLUTION: An optimum sweeping-frequency technique is used in CCFL ignition by parasitic capacitance in a resonance tank circuit. Additionally, the circuit is a self-learning type and adapted to determine an optimum operating frequency for the circuit with a given load. An overvoltage protection circuit can also be provided to ensure that circuit components are protected in the case of an open-lamp condition. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a crossflow power conversion circuit. More particularly, the present invention provides a high efficiency control circuit that regulates the power delivered to the load using zero voltage switching techniques. The general utility for the present invention can be found as a circuit for driving one or more cold cathode fluorescent lamps (CCFLs), but for those skilled in the art, the present invention provides high efficiency and fine power control. You can see that it can be used for whatever load is needed.

  FIG. 1 depicts a conventional CCFL power supply system 10. The system broadly includes a power supply 12, a CCFL drive circuit 16, a controller 14, a feedback loop 18, and one or more lamps CCFL coupled to a liquid crystal panel 20. The power supply 12 supplies a DC voltage to the circuit 16 and is controlled by the controller 14 through the transistor Q3. Circuit 16 is a self-resonant circuit known as a Royer circuit. Basically, the circuit 16 is a self-resonant type cross-flow converter, the resonance frequency of which is set by L1 and C1, and N1 to N4 indicate the windings of the transformer and the number of windings. In operation, transistors Q1 and Q2 conduct and switch inputs with windings N1 and N2, respectively. If Q1 conducts, the input voltage is set through winding N1. A voltage with a corresponding curve will be set through the other windings. The voltage induced at N4 makes the base of Q2 positive and Q1 causes a slight voltage drop between the collector and emitter. The voltage induced at N4 also keeps Q2 cut off. Q1 is conducted until the magnetic flux inside the core of TX1 is saturated.

When saturated, the collector of Q1 rises rapidly (up to the voltage determined by the base circuit) and the voltage induced in the transformer drops rapidly. Q1 is pulled further beyond _{saturation, V CE} rises, further reducing the voltage sandwiching the N1. Loss in driving the base turns off Q1, which in turn causes the magnetic flux inside the core to be slightly reduced, inducing a N4 current to turn on Q2. The voltage induced at N4 keeps Q1 conducting in saturation until the core is saturated in the opposite direction, and a similar opposite operation occurs to complete the switching cycle.

  Although the inverter circuit 16 is composed of relatively few parts, its correct operation is determined by nonlinear and complicated exchange between the transistor and the transformer. In addition, any duplication of the circuit 16 creates an additional undesirable operating frequency, which may resonate at some harmonics, thus causing variations in C1, Q1, and Q2 (typically 35% tolerance). ) Prevents the circuit 16 from adapting to the parallel configuration of the transformer. When applied to a CCFL load, the circuit creates a “beat” effect within the CCFL, which is also detectable and undesirable. Although circuit 16 operates in a self-resonant mode, even if the tolerances closely match, the beat effect cannot be removed because any overlap of the circuit will have its own operating frequency.

US Pat. No. 5,430,641 US Pat. No. 5,619,402 US Pat. No. 5,615,093 US Pat. No. 5,818,172

  In Patent Document 1, Patent Document 2, Patent Document 3, and Patent Document 4, several other drive systems are found. Each of these documents suffers from low efficiency and / or two-stage power conversion and / or variable frequency operation and / or load dependency. In addition, the inclusion of CCFLs and assemblies in the load causes parasitic capacitance, which affects the impedance of the CCFL itself. In order to effectively design a circuit to operate correctly, the circuit must be designed with parasitic impedances in mind to drive a CCFL load. Such an effort is not only time consuming and expensive, but also makes it difficult to design an optimal transducer when handling various loads. Therefore, there is a need to overcome these drawbacks and provide a circuit with efficient and reliable CCFL ignition, load independent power regulation and single frequency power conversion.

  A liquid crystal display system includes a liquid crystal display panel, a cold cathode fluorescent lamp for illuminating the liquid crystal display panel, and a secondary transformer coupled to the cold cathode fluorescent lamp to supply current to the cold cathode fluorescent lamp. A transformer winding, a primary transformer winding coupled to the secondary transformer winding to provide magnetic flux to the secondary transformer winding, and current passing through the primary transformer winding A switch coupled to the primary transformer winding to flow and a feedback signal coupled to the cold cathode fluorescent lamp to indicate that power is being supplied to the cold cathode fluorescent lamp; And a feedback control loop circuit for controlling the power supplied to the cold cathode fluorescent lamp if the feedback signal exceeds a predetermined threshold.

  In another embodiment, the liquid crystal display system is coupled to a liquid crystal display panel, a cold cathode fluorescent lamp for illuminating the liquid crystal display panel, and the cold cathode fluorescent lamp for supplying current to the cold cathode fluorescent lamp Secondary transformer winding, a primary transformer winding coupled to the secondary transformer winding to provide magnetic flux to the secondary transformer winding, and a current flowing through the primary transformer A switch coupled to the primary transformer winding to flow through the winding and coupled to the cold cathode fluorescent lamp to receive a feedback signal from the cold cathode fluorescent lamp, the feedback signal being transmitted from the fluorescent lamp When the open state is shown, a feedback control loop circuit for reducing power supplied to the cold cathode fluorescent lamp is provided.

  In another embodiment, a liquid crystal display panel, a cold cathode fluorescent lamp for illuminating the liquid crystal display panel, and a secondary transformer coupled to the cold cathode fluorescent lamp for supplying current to the cold cathode fluorescent lamp A winding, a primary transformer winding coupled to the secondary transformer winding to provide magnetic flux to the secondary transformer winding, and a current passing through the primary transformer winding. A first switch coupled to the primary transformer winding for directing in one direction; and the primary transformer winding for directing current through the primary transformer winding in a second direction. A second switch coupled to the first transformer, and configured to supply current to the primary transformer winding when there is an overlap between the third switch and the first switch, the primary transformer A third switch coupled to the winding and the first switch; A predetermined minimum to the cold cathode fluorescent lamp coupled to the lamp by receiving a feedback signal from the cold cathode fluorescent lamp and keeping the overlap between the third switch and the first switch to a minimum A feedback control loop circuit that maintains power.

  Providing a pulse signal to a transistor for a conduction path to a primary transformer winding for controlling power to the cold cathode fluorescent lamp in a liquid crystal display system, and electrical conditions in the cold cathode fluorescent lamp Generating a feedback signal from a cold cathode fluorescent lamp coupled to a secondary transformer winding indicating: receiving the feedback signal from the cold cathode fluorescent lamp; and if the feedback signal is the cold cathode A method comprising adjusting the power to the cold cathode fluorescent lamp is also described if it indicates ignition of a fluorescent lamp.

  Those skilled in the art will proceed with the following detailed description with reference to embodiments and methods made using the same, but the invention is limited to those embodiments and methods using the same. Is not intended. Rather, the present invention is intended to be broad and limited only by what is set forth in the appended claims.

  Other features and advantages of the present invention will become apparent from the following detailed description, which proceeds with reference to the drawings, in which like parts are provided with like reference numerals.

  While not wishing to be bound by example, the following detailed description proceeds with reference to the CCFL board as a load on the circuit of the present invention. However, it will be apparent that the present invention is not limited to driving one or more CCFLs, and the present invention is broadly interpreted as a power conversion circuit, and a method independent of a particular load for a particular application. Should be.

  Overall, the present invention provides a circuit that uses a feedback signal and a pulse signal to controllably provide power to a load to adjust the on-time of the two sets of switches. When a set of switches is controllably turned on so that the on-time overlaps, power is delivered to the load (via the transformer) along a conduction path determined by the set of switches. Similarly, when other sets of switches are controllably turned on so that the on times overlap, power is provided to the load (via the transformer) along a conduction path determined by the other sets of switches. It is done. Thus, by selectively turning on the switches and controlling the overlap between the switches, the present invention can accurately control the power applied to a given load. In addition, the present invention includes overcurrent and overvoltage protection circuits that stop powering the load when a short circuit or open circuit condition occurs. Furthermore, the controlled topology described herein allows the circuit to operate at a single operating frequency independent of the resonant effects of the transformer configuration, regardless of load. These features are described below with reference to the drawings.

  The circuit diagram of FIG. 2A shows a phase shift, full bridge, zero voltage switching power converter of the present invention. Basically, the circuit shown in FIG. 2A includes a power supply 12, a plurality of switches 80 arranged as a pair of opposed switches defining an AC conduction path, a drive circuit 50 for driving each of the switches, and a circuit. 50 includes a frequency swept oscillator 22 that generates a square wave pulse driving 50, a transformer TX1 (an associated resonant tank circuit defined on the primary side of TX1 and C1), and a load. Advantageously, the present invention also includes an overlap feedback control loop 40 that controls at least one on-time of each set of switches, thereby providing controllable power to the load.

  The power supply 12 is applied to this system. Initially, a bias / reference signal 30 is generated from the power supply to the control circuit (in control loop 40). Desirably, the frequency sweep oscillator 22 starts from the upper frequency and sweeps downward at a predetermined speed and a predetermined interval (that is, a rectangular wave signal having a variable pulse width) to generate a pulse signal having a 50% duty cycle. The frequency sweep oscillator 22 is preferably a programmable frequency generator, as is well known to those skilled in the art. The pulse signal 90 (from the sweep oscillator 22) is sent to B_Drive (which drives Switch_B, ie controls the gate of Switch_B), and is sent to A_Drive to send the complementary pulse signal 92 and the ramp signal 26. Generate. As described below, the complementary pulse signal 92 is approximately 180 degrees out of phase with the pulse signal 90, and the ramp signal 26 is approximately 90 degrees out of phase with the pulse signal. The ramp signal is preferably a sawtooth signal as shown. The ramp signal 26 is compared with the output signal 24 (referred to herein as CMP) of the error amplifier 32 through a comparator 28 to produce a signal 94. Similarly, the output signal 94 of the comparator 28 is a 50% duty pulse that is sent to C_Drive and begins to turn on Switch_C, which in turn determines the amount of overlap between switches B and C and switches A and D. . The complementary signal (about 180 ° phase) is given to Switch_D through D_Drive. One skilled in the art will understand that the circuits Drive_A-Drive_D are connected to the control lines (eg, gates) of Switch_A-Switch_D, respectively, so that each of the switches can be controllably conducted as described herein. Let's do it. By adjusting the amount of overlap between switches B, C and A, D, lamp-current regulation is achieved. In other words, it is the amount of overlap of the conductive states of the paired switches that determines the amount of power processed inside the converter. Accordingly, switches B and C, and A and D are referred to herein as overlapping switches.

  Although not wishing to be bound by an example, in the present embodiment, B_Drive is preferably made of a totem pole circuit, a low impedance operational amplifier circuit, or an emitter follower circuit. C_Drive is similarly configured. Since both A_Drive and D_Drive are not directly connected to ground potential (ie floating), these drives are preferably formed from a bootstrap circuit or other known high-side drive circuit. In addition, as described above, A_Drive and D_Drive include inverters that invert (ie, phase) the signals flowing from B_Drive and C_Drive.

  Through the zero voltage switching approach, high efficiency operation is achieved. The four MOSFETs (Switch_A to Switch_D) 80 are turned on after the parasitic diodes (D1 to D4) are conducted to provide a current flow path for energy in the transformer / capacitor device (TX1 / C1), and as a result Make sure that both sides of the switch are at zero voltage. With this controlled operation, switching loss is minimized and high efficiency is maintained.

  A preferred switching operation of the overlap switch 80 is shown with reference to the timing diagrams of FIGS. 2B (a)-(f) (FIG. 2B (f)). Switch_C is turned off during a period of conduction of both switches B and C. The current flowing in the tank (see FIG. 2A) then flows through the diode D4 in Switch_D (FIG. 2B (e)), and after Switch_C is turned off, the diode D4 in Switch_D, the primary side of the transformer, C1, flows through Switch_B, and as a result of the energy provided when switches B and C conduct, resonates the voltage and current in capacitor C1 and the transformer. This situation must occur because the instantaneous change in the direction of the current on the primary side of the transformer violates Faraday's law. Thus, current should flow through D4 when Switch_C is off. Switch_D is turned on after D4 is turned on. Similarly, Switch_B is turned off (FIG. 2B (e)), and the current is diverted to diode D1 associated with Switch_A before Switch_A is turned on (FIG. 2B (e)). Similarly, Switch_D is turned off (FIG. 2B (d)), and current then flows from Switch_A through C1 through the transformer primary, diode D3. Switch_C is turned on after D3 is turned on (FIG. 2B (e)). Switch_B is turned on after Switch_A is turned off, which allows diode D2 to conduct first before turning on. The overlapping of the on-time of the opposing switches B, C and A, D determines the energy given to the transformer, as shown in FIG. 2B (f).

  In the present embodiment, FIG. 2B (b) shows that the ramp signal 26 is generated only when Switch_A is turned on. Accordingly, Drive_A generates a ramp signal 26, but preferably includes a constant current generation circuit (not shown) including a capacitor having an appropriate time constant for generating the ramp signal. For this, a reference current (not shown) is used to charge the capacitor, which is grounded (eg via a transistor switch) so that the discharge rate exceeds the charge rate, and so on. A sawtooth ramp signal 26 is generated. Of course, as discussed above, this can be accomplished by integrating the pulse signal 90, and therefore the ramp signal 26 can be made using an integrating circuit (eg, an op amp and a capacitor).

  During the ignition period, a predetermined minimum overlap between two opposing switches is generated (ie, between switches A, D and B, C). This gives the least energy from the input to the tank circuit containing C1, transformer, C2, C3 and CCFL loads. Note that the load may be resistive and / or capacitive. The drive frequency starts at a predetermined high frequency and a significant amount of energy is applied to the load to which the CCFL is connected until the resonant frequency of the equivalent circuit reflected at the secondary side of the tank circuit and transformer is reached. Because of the high impedance characteristics before ignition, the CCFL receives a high voltage from the energy supplied to the primary side. This voltage is sufficient to ignite the CCFL. The impedance of the CCFL drops to the normal operating voltage (eg, 100K ohms to 130K ohms) and the energy applied to the primary side based on the minimum overlap operation is no longer sufficient to maintain CCFL steady state operation. . The output of the error amplifier 26 starts its adjustment function and increases the overlap. It is the level of the error amplifier output that determines the amount of overlap. For example:

  Referring to the feedback loop 40 of FIGS. 2B (b), 2B (c) and 2A, if it is determined in the comparator 28 that the ramp signal 26 is equal to the value of the signal CMP24 (generated by the error amplifier 32), It is important to note that Switch_C is turned on. This is indicated by the intersection 36 in FIG. 2B (b). In order to prevent a short circuit, the switches A, B and C, D must never be turned on at the same time. By controlling the level of CMP, the overlap time between switches A, D and B, C regulates the energy supplied to the transformer. In order to adjust the energy supplied to the transformer (thus adjusting the energy supplied to the CCFL load), switches C and D control the switches A and B by controlling the error amplifier output CMP24. Shift in time. As can be seen from the timing diagram, if the drive pulses from the output of the comparator 28 to the switches C and D shift to the right by increasing the level of CMP, the overlap between the switches A, C and B, D Increase in energy and increase the energy supplied to the transformer. In practice, this corresponds to larger lamp current operation. Conversely, shifting the drive pulses of switches C and D to the left (by reducing the CMP signal) reduces the energy supplied.

  For this purpose, the error amplifier 32 compares the feedback signal FB with the reference voltage REF. FB is a measured value of the current value passing through the detection resistor Rs, and this indicates the total current passing through the load 20. REF is a signal indicating a desired load condition, for example, a desired current flowing through the load. In normal operation, REF = FB. However, if the load condition is deliberately offset from, for example, a dimmer switch associated with an LCD panel display, the value of REF will eventually increase / decrease. The value of CMP reflects the load condition and / or internal bias and is understood as the difference between REF and FB (ie, REF−FB).

  To protect the load and circuit from an open circuit condition at the load (eg, an open CCFL lamp condition during normal operation), the FB signal is also preferably compared to a reference value in the current sense comparator 42, and its output is The state of the switch 28 is defined as will be described below. This reference value is programmable and / or can be determined by the user and reflects the minimum or maximum current that the system will tolerate (eg, can be determined for individual components, particularly CCFL loads). Is desirable. If the value of the feedback FB signal and the reference signal are within the allowable range (normal operation), the output of the current detection comparator is 1 (or high). This allows CMP to flow through switch 38 and the circuit operates as described herein to supply power to the load. However, if the value of the FB signal and the reference signal are outside the allowable range (open circuit or short circuit state), the output of the current detection comparator is 0 (or low), indicating that the CMP signal flows through the switch 38. Ban. (Of course, the converse can be true, in which case the switch will trigger in a low state). Instead, a minimum voltage Vmin is provided by switch 38 (not shown) and provided to comparator 28 until the current sense comparator indicates that an acceptable current is flowing through Rs. Accordingly, the switch 38 includes Vmin as an appropriate programmable voltage selection for when the sense current is zero. Returning to FIG. 2B (b) again, the effect of this operation is to reduce the CMP DC value to a normal or minimum value (ie, CMP = Vmin) so that a high voltage condition does not appear on the transformer TX1. is there. Therefore, the intersection 36 is shifted to the left, resulting in a decrease in the amount of overlap between the complementary switches (recall that Switch_C is turned on at the intersection 36). Similarly, the current sense comparator 42 is connected to the frequency generator 22 and turns off the generator 22 when the sensed value is 0 (or some other preset value indicating an open circuit condition). The CMP is guided to the protection circuit 62. This is to turn off the frequency sweep oscillator 22 if the CCFL disappears during operation (open circuit state).

  In order to protect the circuit from overvoltage conditions, the present embodiment preferably includes a protection circuit 60, the operation of which will be described below (the description of overcurrent protection flowing through the current sense comparator 42 has been described above). The circuit 60 includes a protection comparator 62 that compares the signal CMP with the voltage signal 66 from the load 20. The voltage signal is preferably derived from voltage dividers C2 and C3 (ie in parallel with load 20) as shown in FIG. In the open ramp condition, the frequency sweep oscillator continues to sweep until the OVP signal 66 reaches a threshold value. The OVP signal 66 is taken at the output capacitor dividers C2 and C3 to detect the voltage at the output of the transformer TX1. To simplify the analysis, these capacitors also represent equivalent load capacitance ramp capacitors. The threshold is a reference value, and the circuit is designed such that the voltage on the secondary side of the transformer is greater than the minimum starting voltage in a range that is less than the rated voltage of the transformer. When OVP exceeds the threshold, the frequency sweep oscillator stops the frequency sweep. Meanwhile, the current detection 42 does not detect a signal passing through the detection resistor Rs. Accordingly, the signal at 24, ie the output of the switch block 38, is set to a minimum value so that a minimum overlap between the switches A, C and B, D can be seen. Timer 64 is started once the OVP exceeds the threshold, thereby initiating a timeout procedure. The length of time for the timeout is preferably designed from the load requirements (e.g., LCD panel CCFL), but could alternatively be set to some programmable value. Once timed out, the drive pulse is disabled, thus providing an output of safe operation of the converter circuit. That is, the circuit 60 supplies enough voltage to ignite the fluorescent lamp, but if the fluorescent lamp is not connected to the converter, it will shut off after a certain time, resulting in a false high voltage at the output. Absent. This interval is necessary because the non-ignition fluorescent lamp is close to the state in which the fluorescent lamp is open.

  3A and 3B (a)-(f) depict other embodiments of the DC / AC circuit of the present invention. In this embodiment, the circuit operates in the same way as given in FIGS. 2A and 2B (a)-(f), but this embodiment further controls the frequency sweep oscillator 22 and flip-flop circuit 72. , Further includes a phase-locked loop circuit (PLL) 70 for timing the input of the signal to C_Drive. As can be seen from the timing diagram, if the 50% drive pulse of switches C and D shifts to the right by increasing the level of CMP, an increase in overlap between switches A, C and B, D is realized. The energy distributed to the transformer increases. In practice, this corresponds to the high current operation of a fluorescent lamp (which may be required, but for example by manually increasing the REF voltage as described above). Conversely, shifting the drive pulses of switches C and D to the left (by reducing the CMP signal) reduces the energy supplied. Phase locked loop circuit 70 maintains the phase relationship between the feedback current (through Rs) and the tank current (TX1 / C1) during normal operation, as shown in FIG. The PLL circuit 70 preferably includes a signal 98 that is an input signal from the tank circuit and a signal from the Rs (the FB signal described above). Once the CCFL is ignited and the current in the CCFL is detected through Rs, a PLL 70 circuit is activated that locks the phase between the fluorescent lamp current and the current in the primary resonant tank (C1 and the transformer primary). That is, frequency sweep oscillators for all parasitic variables such as temperature effects, mechanical devices such as the wiring between the converter and the LCD panel, and fluorescent and LCD panel metal chassis that affect the capacitance and inductance. A PLL is provided to adjust the 22 frequencies. The system preferably maintains a 180 ° phase difference between the resonant tank circuit and the current flowing through Rs (load current). The system then finds the optimal operating point regardless of the specific load conditions and / or the operating frequency of the resonant tank circuit.

  The operation of the feedback loop of FIG. 3 is close to the above description for FIG. However, as shown in FIG. 3B (b), the present embodiment measures the output of the start signal that passes through the flip-flop 72 and passes through C_Drive. For example, during normal operation, the output of error amplifier 32 is provided through control switch block 38 (described above) to become signal 24. A certain amount of overlap between switches A, C and B, D is seen through comparator 28 and flip-flop 72 driving switches C and D (recall that D_Drive produces a complementary signal of C_Drive). . This provides steady state operation for CCFL (plate) loads. Considering removing the CCFL (plate) during normal operation, CMP increases to the rail of the error amplifier output and immediately triggers the protection circuit. This function is prohibited during the ignition period.

  Referring to FIGS. 3B (a) to 3 (f) schematically, in this embodiment, triggering the switches C and D through C_Drive and D_Drive is a change in response to the result of the flip-flop circuit 72. . As shown in FIG. 3B (b), the flip-flop triggers every other time, thereby starting C_Drive (and thus D_Drive). Other than that, the operation is similar to that described above with reference to FIGS. 2B (a) to 2 (f).

  4A-4F, which is comparable to the output circuit of FIG. 2A or FIG. 3A. For example, FIG. 4A shows that at a 21V input (overlap of 0.5 μs) when the frequency swept oscillator reaches 75.7 KHz, the output reaches 1.67 KVp-p. This voltage is insufficient to turn on on the CCFL if 3300 Vp-p is required for ignition. When the frequency drops to about 68 KHz, the minimum overlap produces about 3.9 KVp-p at the output, which is sufficient to ignite the CCFL. This is illustrated in FIG. 4B. At this frequency, the overlap increases to 1.5 μs, so the output is about 1.9 Vp-p, and the 130 k ohm fluorescent lamp impedance is activated. This is illustrated in FIG. 4C. As another example, FIG. 4D shows operation while the input voltage is 7V. At 71.4 KHz, the output is 750 Vp-p before the fluorescent lamp starts. As the frequency decreases, the output voltage increases until the fluorescent lamp ignites. FIG. 4E shows that the output reaches 3500 Vp-p at 65.8 KHz. CCFL current regulation is achieved by adjusting the overlap to maintain an impedance of 130 Kohm after ignition. The voltage before and after the CCFL is 1.9 KVp-p for a 660 Vrms fluorescent lamp. This is shown in FIG. 4F. Although not shown, the emulation of the circuit of FIG. 3A operates similarly.

  It should be noted that the difference between the first embodiment and the second embodiment (ie, due to the addition of flip-flops and PLLs in FIG. 3) does not affect the overall operating parameters described in FIGS. However, the addition of the PLL is determined to be a source of the non-ideal impedance generated in the circuit, and can be added instead of the circuit shown in FIG. Further, by adding the flip-flop, the constant current circuit can be removed as described above.

  As described above, it is clear that a high-efficiency adaptive DC / AC converter circuit that satisfies the above-described goals and objectives has been provided. It will be apparent to those skilled in the art that changes are possible. For example, although the present invention has used a MOSFET for the switch, those skilled in the art will understand that the entire circuit can be constructed using a BJT transistor, or a mixture of some kind of transistor, including a MOSFET or BJT. I will. Other changes are possible. For example, the drive circuit associated with Drive_B and Drive_D can be comprised of a common collector circuit because the associated transistor is coupled to ground potential and as a result does not become floating. The PLL circuit described herein is preferably a standard PLL circuit 70 well known in the industry, suitably modified to receive an input signal and generate a control signal. The pulse generator 22 is preferably a pulse width modulation circuit (PWM) or a frequency width modulation circuit (FWM), both of which are well known in the industry. Similarly, the protection circuit 62 and the timer are configured by known circuits and appropriately changed so as to operate as described above.

  FIG. 5 shows a liquid crystal display system according to an embodiment of the present invention. The liquid crystal display system 100 includes a thin film transistor screen 501. Thin film transistor screen 501 is coupled to column drive circuit 502. The column driving circuit 502 controls the columns on the thin film transistor screen 501. Thin film transistor screen 501 is also coupled to row drive circuit 503. The row driving circuit 503 controls a row on the thin film transistor screen 501. Column drive circuit 502 and row drive circuit 503 are coupled to timing controller 504. The timing controller 504 controls timing for the column driving circuit 502 and the row driving circuit 503. Timing controller 504 is coupled to video signal processor 505. The video signal processor 505 processes the video signal. In another embodiment, the video signal processor 505 may be a counting device.

  Thin film transistor screen 501 is illuminated by display illumination system 599. The display illumination system 599 includes a cold cathode fluorescent lamp 562. Cold cathode fluorescent lamp 562 is coupled to secondary transformer winding 560. Secondary transformer winding 450 provides current to cold cathode fluorescent lamp 562. Secondary transformer winding 560 is coupled to primary transformer winding 518. The primary transformer winding provides magnetic flux to the secondary transformer winding 560. Primary transformer winding 518 is coupled to switch 532. Switch 532 allows current to flow through primary transformer winding 518. Primary transformer winding 518 is also coupled to switch 512. Switch 512 allows current to flow through primary transformer winding 518. Switch 532 and switch 512 are coupled to controller 550. The controller 550 supplies a pulse signal that controls switching between the switch 532 and the switch 512. It will be appreciated that any controller described herein can be used as the controller 550. It will also be appreciated that all display lighting systems described herein can be used in place of the display lighting system 599.

  FIG. 6 shows a liquid crystal display system according to an embodiment of the present invention. The liquid crystal display system 600 includes a thin film transistor screen 601. Thin film transistor screen 601 is coupled to column drive circuit 602. The column driving circuit 602 controls the columns on the thin film transistor screen 601. The thin film transistor screen 601 is also coupled to the column drive circuit 603. The row driving circuit 603 controls a row on the thin film transistor screen 601. Column drive circuit 602 and row drive circuit 603 are coupled to timing controller 604. The timing controller 604 controls timing for the column driving circuit 602 and the row driving circuit 603. Timing controller 604 is coupled to video signal processor 605. The video signal processor 605 processes the video signal. Video signal processor 605 is coupled to video demodulator 606. The video demodulator 606 demodulates the video signal. Video demodulator 606 is coupled to tuner 607. The tuner 607 supplies the video signal to the video demodulator 606. The tuner 607 adjusts the liquid crystal display system 600 to a specific frequency. Video demodulator 606 is also coupled to microcontroller 608. Tuner 607 is also coupled to audio demodulator 611. The audio demodulator 611 demodulates the audio from the tuner 607. Audio demodulator 611 is coupled to audio signal processor 610. The audio signal processor 610 processes the audio signal from the audio demodulator 610. The audio signal processor 610 is connected to the audio amplifier 609. The audio amplifier 609 amplifies the audio signal from the audio signal processor 610.

  The thin film transistor screen 601 is illuminated by a display illumination system 699. The display illumination system 699 includes a cold cathode fluorescent lamp 662. Cold cathode fluorescent lamp 662 is coupled to secondary transformer winding 660. The secondary transformer winding 660 supplies current to the cold cathode fluorescent lamp 662. Secondary transformer winding 660 is coupled to primary transformer winding 618. Primary transformer winding 618 provides magnetic flux to secondary transformer winding 660. Primary transformer winding 618 is coupled to switch 632. Switch 632 allows current to flow through primary transformer winding 618. Primary transformer winding 618 is also coupled to switch 612. Switch 612 allows current to flow through primary transformer winding 618. Switch 632 and switch 612 are coupled to the controller. The controller 650 supplies a pulse signal that controls switching between the switch 632 and the switch 612. It will be appreciated that any controller described herein can be used as the controller 650. It will also be appreciated that all display lighting systems described herein can be used in place of the display lighting system 699.

  FIG. 7 shows a liquid crystal display system according to an embodiment of the present invention. The liquid crystal display system 700 includes a graphics adapter 790. The liquid crystal display system 700 may include the components of the liquid crystal display system 500 shown in FIG. 5 as described above, or may include the components of the liquid crystal display system 600 described above as shown in FIG. . The graphics adapter 790 may be the video signal processor 505 described above and shown in FIG. 5, or the video signal processor 605 described above and shown in FIG.

  Graphics adapter 790 is coupled to chipset core logic 791. Chipset core logic 791 transfers data to and from devices coupled to it. Chipset core logic 791 is also coupled to the microprocessor. The microprocessor 792 processes data including video data. Chipset core logic 791 is also coupled to memory 793. The memory 793 may be a random access memory, and is used for storing data for a short time. Chipset core logic 791 is also coupled to hard disk drive 794. The hard disk drive 794 is used for storing data for a long time. Chipset core logic 791 is also coupled to optical drive 795. The optical drive 795 reads data from a CD-ROM or DVD-ROM.

  Referring to FIG. 8, one embodiment of a switched CCFL power supply 100 according to the present invention is depicted. The present invention is a switched power supply for supplying energy to a cold cathode fluorescent lamp (CCFL). The power supply converts a low direct current (DC) voltage into a high alternating current (AC) voltage and supplies it to the CCFL.

  The switchable power supply circuit includes a first switch having a source terminal, a drain terminal, and a gate terminal. The drain terminal of the first switch is connected to the primary winding of the booster. The secondary winding of the booster has at least 20 times more windings than the primary winding, and preferably 50 to 150 times as many windings. The source terminal of the first switch is connected to the power source.

  The second switch also has a source terminal, a drain terminal, and a gate terminal. The drain terminal of the second switch is connected to both the drain terminal of the first switch and one end of the primary winding of the transformer. The source terminal of the second switch is connected to the ground reference potential of the power source. The primary winding has a second end coupled to the midpoint of the two capacitor divider. In this way, the two switches are connected in series and divide the voltage input of the power supply into approximately equal parts. Two capacitors are connected in series across the power supply.

  The control circuit transmits a control signal to the first switch and the second switch to alternately turn on the switches by shifting the phase by 180 degrees. When the first switch is turned on, the current flows through the first switch and the secondary winding of the transformer in the forward direction as a reference. When the second switch is turned on, current flows through the second switch in the reverse direction through the primary winding of the transformer.

  The transformer is driven in both directions so that flux redirection around the core is utilized in both the quadrant of the hysteresis curve associated with the transformer. In this way, the size of the transformer core is reduced, thereby reducing the cost of the transformer.

  Two capacitors form a capacitor divider that connects to one end of the primary winding of the transformer. The two capacitors are charged or discharged with the current flowing through the primary winding of the transformer when each switch is turned on. When the first switch is turned on, the current charges the second capacitor while discharging the first capacitor, and the first switch turns on while the body diode associated with the second switch is conducting. Reset when turned off. The current flowing through the primary side of the transformer is reversed when the second switch is turned on. While discharging in the direction of current flow, the second capacitor is charged. After the second switch is turned off, current is captured through the body diode of the first switch. If the switch is turned on while the body diode is conducting, the switch is basically turned on at zero volts across the switch. This zero volt switching technique minimizes switch switching losses. Therefore, power conversion efficiency increases.

  The power source 100 includes a controller 150, a first switch 112, a second switch 132, and a transformer 120, and supplies power to a load such as a CCFL 162 of a display panel such as a liquid crystal display device. Connected to power supply 274.

  The first switch 112 may be a gate-controlled switch of a field effect transistor (MOSFET) of an N-channel metal participation film semiconductor, and includes a drain terminal 114 connected to one end of the primary winding 118 of the booster 120. . The second end portion 125 of the primary winding 118 is connected to the connection portion between the first capacitor 124 and the second capacitor 126. The source terminal 128 of the first switch 112 is connected to the reference ground potential of the power source 274. The second switch 132 may be a P-channel MOSFET gate control type switch. The drain terminal of the P channel switch 132 is also connected to the drain terminal 114 of the switch 112. Both switch 112 and switch 132 include body diodes 134 and 136, respectively. The gate terminals 138 and 152 of the switches 132 and 112 are connected to the output terminal of the controller 150.

  The secondary winding 160 of the booster 120 is connected to the CCFL 162. Unlike the non-saturable core nonlinear permeability used in transformers in the prior art Royer circuit, a linear permeability core is created in the booster 120 that does not saturate during operation of the power supply circuit 100. The booster has a turns ratio of at least 20: 1 and is generally in the range of 50: 1 to 150: 1.

  The secondary winding of the booster 120 is connected in parallel with two capacitors 163 and 164 connected in series. Capacitors 163 and 164 form a voltage divider that senses the voltage at the secondary winding 160 of the booster 120 and builds a square wave at the primary winding 118 into a pseudo-sine curve for supply to the CCFL adder 162. . During normal operation, sense voltage 186 is always reset by switch 170 controlled by the current flowing through CCFL 162. The function of this switch 170 will be disclosed in detail below.

  Controller 150 may be a pulse width modulation controller for supplying first gate drive signal 152 to gate 152 of switch 112 and supplying second gate drive signal 138 to gate 138 of switch 132. In addition to providing drive signals to switches 112 and 132, controller 150 also provides other functions such as two different frequencies for CCFL start-up and normal operation. A circuit 250 for identifying the fluorescent lamp lighting in the controller 150 is used to determine whether the CCFL 162 is turned on and which of the two frequencies is output. While starting CCFL 162, 252 is de-asserted, indicating that there is no electrical CCFL 162 that is not turned on. The first frequency is obtained in the oscillator 254 based on the signal 252. After ignition, the current flowing through CCFL 162 is detected. Thus, signal 252 is asserted to indicate that CCFL is on. The second frequency is obtained at the output of oscillator 254. The lighting signal 252 also determines the output 256 of the low frequency pulse width modulation (PWM) circuit 258. During the lighting period, the signal 256 cannot disturb the waveform applied to the CCFL 162 in order to obtain a smooth lighting voltage. In other words, signal 256 is negated to affect output control logic 286 before signal 252 is asserted.

  The controller 150 includes a function of detecting and controlling the current and voltage of the fluorescent lamp. The current of the fluorescent lamp is detected by the detection resistor 182. The sensed value 184 is compared to a reference value 212 through a comparator such as error amplifier 230 to control the on-time of switches 112 and 132. The lighting voltage is detected through capacitor dividers 163 and 164. The detected value 186 is compared with the reference value 214 by the comparator 232. The output 234 of the comparator 232 determines the start of the digital clock timer 236. After about 1 or 2 seconds, after the start of the clock timer 236, if the output 234 is still deasserted, the output signal 238 of the clock timer 236 asserts the protection circuit 240 and stops the operation of the switches 112 and 132. . That period is used to provide the ignition time, which in the case of CCFL 162 is for example 1 or 2 seconds. The oscillator 254 provides two frequencies for the operation of the power supply 100, a high frequency for lighting the fluorescent lamp and a low frequency for normal operation. The high frequency may be 20-30% higher than the low frequency. The low frequency may be 68 kHz as described in FIG. 4B, or 65.8 kHz as described in FIG. 4E, or some value lower than either frequency.

  A low frequency PWM circuit 258 is provided to generate a signal 256 for modulating the energy delivered to the fluorescent lamp to achieve darkness control. The frequency of signal 256 is preferably in the range of 150 Hz to 400 Hz. The lighting identification circuit 250 receives the fluorescent lamp current detection signal 184, and its output signal 252 is asserted to identify the presence of the CCFL load 162 or the lighting completion. Protection circuit 240 receives signal 252 indicating the presence of CCFL 162, signal 260 indicates that CCFL 162 indicates that there is a current sensed by CCFL 162, and signal 238 indicates that the time when the fluorescent lamp is open has expired. Indicates. Accordingly, the output 262 of the protection circuit 240 is asserted when the fluorescent lamp 162 is in a fluorescent lamp open state, overcurrent, or overvoltage state, or when an undervoltage occurs at the voltage input 130, and the switches 112 and 132 are asserted. Stop the operation.

  Controller 150 includes a ground potential pin 272 that is electrically connected to the ground potential of the circuit, and a voltage input pin 130 that is connected to a DC voltage source. Within controller 150, voltage input pin 130 connects to a reference / bias circuit 210 that generates various reference voltages 212, 214 for internal use. The voltage input pin 130 is also connected to the undervoltage lockout circuit 220 and the output driver 222. As long as the voltage supplied to voltage input pin 130 exceeds the threshold, output signal 224 of circuit 220 can do the rest of controller 150. On the other hand, if the voltage at voltage input pin 130 is below the threshold, signal 224 will stop the remaining processing of controller 150.

  In the operation of the CCFL, the darkness function and the fluorescent lamp opening function of the CCFL are essentially complementary. Advantageously, the two signals 168 and 186 can be multiplexed such that both or the signals 168 and 186 are received at one pin 284 of the controller 150. By implementing this, the price of the controller 150 is reduced.

  The clock pin 276 of the controller 150 connects a capacitor 278 to the circuit ground potential or a resistor 280 to an oscillator 254 that connects to the voltage input pin 130 to provide a clock signal, preferably a ramp signal, to 276. Connect to oscillator 254.

  Advantageously, in the present invention, the power supply 100 utilizes the minimal connections of the controller 150 to achieve the maximum functionality necessary to drive a CCFL load. The operation of the power supply will be described below.

  A DC voltage VIN is applied to the power supply 100. Once the 130 voltage input is greater than the threshold set by the undervoltage lockout circuit, the controller 150 begins operation. The Ref / I-Bias circuit 210 generates a reference voltage for the remaining circuits of the controller 150.

  Because CCFL 162 is not suspended and there is no current feedback signal 184 from CCFL load 162, oscillator 254 generates a higher frequency pulse signal. The driver 222 outputs pulse width modulation drive signals 152 and 138 to the switches 112 and 132, respectively. Capacitor 216 is gradually charged so that voltage 260 gradually increases with time. As the voltage at 260 gradually increases with time, the pulse widths of the drive signals 138 and 152 increase gradually. Accordingly, the power sent to the booster 120 and the load 162 gradually increases as well. Capacitors 124 and 126 are designed so that the voltage across each capacitor is approximately half the input voltage. During the first half cycle, switch 132 is turned on and current flows from the power source through switch 132 to primary winding 118. Thereafter, current flows into the capacitor 126, which includes the magnetizing current and the reflected load current. While the capacitor 126 is being charged, the capacitor 24 is discharged. When switch 132 is turned off, the current in primary winding 118 continues to flow in the same direction. The diode 134 receives a current flow. The switch 112 is turned on approximately 180 degrees after the switch 132 is turned on. The power supply sends current to the primary winding 118 in a reverse direction through the capacitor 124 and through the switch 112 to the reference circuit ground potential 272. The current including the magnetizing current and the reflected load current flows in the opposite direction. At the same time, the capacitor 124 is charged while the capacitor 126 is discharged. When switch 112 is turned off, diode 136 assists in the continuous flow of current in primary winding 118. The switch 132 is turned on approximately 180 degrees after the switch 112 is turned on. Each cycle, the switch operation continues. Thus, the voltage across the primary winding 118 is substantially a rectangular wave.

  Referring to FIG. 9, the waveform at another terminal is depicted. FIG. 9A shows the drive waveform at 152. FIG. 9B shows the corresponding drive waveform at 138. Note that the on times of switches 112 and 132 are 180 degrees apart. Of course, the switch 132 can be changed to an N-channel device. In this case, the drive signal 138 will be logically inverted to represent an on / off drive signal. FIG. 9C shows the voltage waveform at 125. Small ripples on the DC voltage (half of the voltage flow VIN) represent charging and discharging of the capacitor 126. Subtracting the input voltage VIN by the voltage at 125 produces a similar waveform representing the voltage across the capacitor 124, which also has a small ripple that rides on half of the input voltage. FIG. 9 (d) shows the voltage at 114, while the current through the primary winding 118 is shown in FIG. 9 (f). Note that when switch 132 is turned on at t1, the voltage at 114 is near VIN. The current in the primary winding 118 flows in the positive direction as a reference, and this current charges the capacitor 126 and discharges the capacitor 124. Thus, the voltage at capacitor 126 increases (positive slope). At time t2, the switch 132 is turned off. The current in the primary winding 118 flows in the same direction but decreases. The diode 134 receives current until the current decreases to zero. During the period from t2 to t3, the voltage at 114 is clearly almost zero. Since the current flows in the same direction, the voltage at capacitor 126 still increases. Due to the back magnetomotive force in primary winding 118 temporarily after t3, a small amount of current flows in the reverse direction and the voltage at 114 reaches VIN plus the positive voltage drop of 136. The diode 136 becomes conductive. At time t4, the switch 112 is turned on. The voltage 114 decreases to near zero while the current in the primary winding 118 increases in the reverse direction. The capacitor 126 is discharged and the capacitor 124 is charged. The voltage at capacitor 126 will therefore decrease (negative slope). The switch 112 is turned off at time t5, the diode 136 is turned on, and continues to pass current. The diode 136 stops conducting when the current in the primary winding 118 becomes zero. At this time, a small amount of current flows in the positive direction as a reference. In other words, the diode 134 conducts so that the voltage at 114 is nearly zero. This continues until the next cycle begins at time t7 when switch 132 is turned on again. The booster 120 is driven in both directions to maximize the flux swing and supply power to the CCFL load. A tank circuit is formed by all the parasitic reactance components related to the booster 120, the output capacitors 163 and 164, and the secondary circuit of the transformer 120. The tank circuit picks out the harmonic components associated with the square wave present in the primary winding 118 and produces a shaped, approximately sinusoidal curve in CCFL 162. This can be seen in FIG. 9 (e). Due to the parasitic elements of the secondary winding 160 and the load 162, the waveform 172 will have a different phase with respect to the waveforms shown in FIGS. 9 (a)-(d) and FIG. 9 (f). The voltage at 172 is divided by capacitors 163 and 164. Thus, capacitors 163 and 164 serve two purposes. One purpose is voltage sensing 186 and the other purpose is waveform shaping.

  When CCFL 162 is connected, the amount of current flowing through CCFL 162 is detected by resistor 182. The sensed signal 184 is sent into the current amplifier 230 with a compensation capacitor 216 connected to the output 260. Signal 260 is compared with the signal from oscillator 254 and provides an output to control logic 286 to determine the on-time of switches 112 and 132. One way to adjust the amount of power delivered to the load is to add a command signal 168 to the input 284 of the controller 150. The signal at 284 outputs the low frequency pulse signal to the output control logic 286 so that the outputs 138 and 152 of the drive circuit 222 are modulated with the low frequency pulse signal, thereby effectively controlling the amount of energy applied to the CCFL 162. Is converted through a low frequency PWM circuit 258.

  During the ignition period, the CCFL 162 operates as an infinite impedance element with respect to the power supply circuit 100. Also, the CCFL 162 normally requires a predetermined ON voltage during this period. Power supply circuit 100 including capacitors 163 and 164 detects the voltage at CCFL 162. Accordingly, the predetermined on-voltage is increased or decreased at a signal 186 that is transmitted to the input 284 of the controller 150 for voltage control. The fluorescent lamp on identification circuit 250 generates a signal 252 indicating that the CCFL 162 is not on. Signal 234 is asserted to start digital clock timer circuit 236. Signal 252 also generates a high frequency suitable for commanding the oscillator to start CCFL 252. During this time, the voltage at the CCFL 162 is controlled to a predetermined value. Signal 238 is generated from digital clock timer circuit 236 one to two seconds after signal 234 is asserted. If CCFL 162 turns on before signal 238 is asserted, operation of CCFL 162 continues as described in the previous paragraph. If CCFL 162 does not turn on (failure, disconnection or loose connection), assertion of signal 238 activates protection circuit 240. The operation of the drive circuit 222 is stopped so that the signal 262 output from the protection circuit 240 is generated and the switches 112 and 132 are cut off. During this time, the CCFL 162 is not turned on, so that no power is supplied to the CCFL 162, and the power control command signal 168 is naturally invalid for the operation of the power source. In other words, the power supply circuit 100 performs the ignition function of the CCFL 162, and the darkness control for adjusting the power to the CCFL 162 is disabled. Further, during normal operation, the voltage detection signal 186 is reset by the device 170 so as not to affect the CCFL darkness control. Thus, the multiplex function reduces the number of pins, thereby saving the cost of the controller 150 and the power circuit.

  The oscillation circuit 254 generates a pulse signal by connecting the capacitor 278 to the reference circuit ground potential or connecting the resistor 280 to the voltage input. When capacitor 278 is connected to circuit ground potential, oscillator circuit 254 supplies / withdraws current to / from capacitor 278. When resistor 280 is connected to the voltage input, oscillator circuit 254 draws current from voltage input and resistor 280. The feature of current draw and supply or draw only allows distinction between different control modes for adjusting the power supplied to the CCFL 162. The power control command signal 168 controls and adjusts the power supplied to the CCFL 162 without passing through the low frequency PWM circuit 258 to distinguish the low frequency PWM mode as described above for the linear mode. Signal 168, or signal 284, passes through low frequency PWM circuit 258 and generates / overwrites reference signal 212 toward amplifier 230 when the oscillator circuit connects resistor 280 to the voltage input. Command signal 168 thus directly commands the amount of current feedback signal 184 and regulates the current flowing through CCFL 162. In this mode of operation, the signal at 282 blocks the low frequency PWM circuit 258 and passes the signal 284. Therefore, by connecting the resistor 280 or the capacitor 278 to the oscillation circuit, not only the pulse signal is generated, but also the control mode for adjusting the power to the CCFL load 162 in the linear control mode or the low frequency pulse width modulation mode is determined. To do. Such a design minimizes the number of parts used around the controller 150 while providing the designer with great flexibility.

  As described above, the first switch 112 and the second switch 132 of the power supply 100 according to the present invention are controlled by the controller 150 and are alternately turned on, so that the current flows through the CCFL 162 in the first direction and the second direction. The power source 100 converts the DC power source to an AC power source in order to supply power to the CCFL 162.

  Thus, various modifications and / or alternative uses of the present invention will be apparent without departing from the spirit and scope of the present invention and will be suggested to those skilled in the art after reading the foregoing disclosure. Accordingly, the appended claims are intended to be construed as including all modifications or alternative uses falling within the spirit and scope of the invention.

  Other circuits will be readily apparent to those skilled in the art, and all such modifications are within the spirit and scope of the invention and are considered limited only by the appended claims.

It is a figure of the conventional crossflow conversion circuit. It is a figure of one Embodiment of the crossflow conversion circuit of this invention. FIG. 2B is a timing diagram as an example of the circuit of FIG. 2A. It is a figure of other embodiment of the crossflow conversion circuit of this invention. FIG. 3B is a timing diagram as an example of the circuit of FIG. 3A. 3B is an emulation diagram for the circuit shown in FIGS. 2A and 3A. FIG. 3B is an emulation diagram for the circuit shown in FIGS. 2A and 3A. FIG. 3B is an emulation diagram for the circuit shown in FIGS. 2A and 3A. FIG. 3B is an emulation diagram for the circuit shown in FIGS. 2A and 3A. FIG. 3B is an emulation diagram for the circuit shown in FIGS. 2A and 3A. FIG. 3B is an emulation diagram for the circuit shown in FIGS. 2A and 3A. FIG. It is a figure of the liquid crystal display system of one Embodiment of this invention. It is a figure of the liquid crystal display system of one Embodiment of this invention. It is a figure of the liquid crystal display system of one Embodiment of this invention. It is a figure of the display illumination system of the liquid crystal display system of one Embodiment of this invention. It is a wave form diagram of the liquid crystal display system of one Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 12 ... Power supply 20 ... Liquid crystal display board 22 ... Frequency sweep oscillator 24 ... Output signal 26 ... Ramp signal 28 ... Comparator 30 ... Bias / reference signal 32 ... Error amplifier 38 ... Switch 40 ... Overlap feedback control loop 42 ... Current detection comparator DESCRIPTION OF SYMBOLS 50 ... Drive circuit 60 ... Protection circuit 62 ... Protection comparator 64 ... Timer 66 ... Voltage signal 80 ... Switch 90 ... Pulse signal 92 ... Complementary pulse signal

Claims (29)

A liquid crystal display board;
A cold cathode fluorescent lamp for illuminating the liquid crystal display panel;
A secondary transformer winding coupled to the cold cathode fluorescent lamp to supply current to the cold cathode fluorescent lamp;
A primary transformer winding coupled to the secondary transformer winding to provide magnetic flux to the secondary transformer winding;
A switch coupled to the primary transformer winding such that current flows through the primary transformer winding;
A feedback signal coupled to the cold cathode fluorescent lamp to indicate that power is being supplied to the cold cathode fluorescent lamp; and if the feedback signal exceeds a predetermined threshold, the cold cathode fluorescent lamp A liquid crystal display system, comprising: a feedback control loop circuit for controlling supplied power.   The liquid crystal display system of claim 1, further comprising an input voltage source coupled to the switch for supplying current to the switch.   The liquid crystal display system according to claim 2, wherein the input voltage source is a power source. A first capacitor coupled to the primary transformer winding and ground potential;
The liquid crystal display system according to claim 2, further comprising: a second capacitor coupled to the primary transformer winding and the input voltage source.   2. The liquid crystal display system according to claim 1, wherein the feedback control loop circuit maintains a predetermined minimum power for the cold cathode fluorescent lamp if the feedback signal is not greater than a predetermined threshold. A second switch coupled to the primary transformer winding such that current flows in the reverse direction through the primary transformer winding;
Configured to supply current to the primary transformer winding when there is an overlap between the third switch and the first switch, coupled to the primary transformer winding and the first switch The liquid crystal display system according to claim 5, further comprising: a third switch.   The feedback control loop maintains the predetermined minimum power to the cold cathode fluorescent lamp by keeping the overlap between the third switch and the first switch to a minimum. 6. The liquid crystal display system according to 6.   The liquid crystal display system according to claim 1, further comprising a voltage detector coupled to the cold cathode fluorescent lamp to detect a voltage across the cold cathode fluorescent lamp.   A voltage protection circuit coupled to the voltage detector, further comprising a voltage protection circuit that reduces power to the cold cathode fluorescent lamp when the voltage across the cold cathode fluorescent lamp exceeds a predetermined threshold. Item 9. A liquid crystal display system according to Item 8.   The liquid crystal display system according to claim 9, further comprising a timer coupled to the voltage protection circuit to provide a time-out period. A liquid crystal display board;
A cold cathode fluorescent lamp for illuminating the liquid crystal display panel;
A secondary transformer winding coupled to the cold cathode fluorescent lamp to supply current to the cold cathode fluorescent lamp;
A primary transformer winding coupled to the secondary transformer winding to provide magnetic flux to the secondary transformer winding;
A switch coupled to the primary transformer winding such that current flows through the primary transformer winding;
Feedback control coupled to the cold cathode fluorescent lamp for receiving a feedback signal from the cold cathode fluorescent lamp and reducing the power supplied to the cold cathode fluorescent lamp when the feedback signal indicates that the fluorescent lamp is open. A liquid crystal display system comprising: a loop circuit.   12. The liquid crystal display system according to claim 11, wherein the feedback signal indicates a voltage across the cold cathode fluorescent lamp, and the state where the fluorescent lamp is open is indicated when the voltage exceeds a predetermined threshold. .   13. The liquid crystal display system according to claim 12, wherein the feedback control loop circuit maintains a predetermined minimum power to the cold cathode fluorescent lamp when the voltage exceeds a predetermined threshold. A second switch coupled to the primary transformer winding such that current flows in the reverse direction through the primary transformer winding;
Configured to supply current to the primary transformer winding when an overlap condition exists between the third switch and the first switch, and to the primary transformer winding and the first switch The liquid crystal display system according to claim 13, further comprising a coupled third switch.   15. The feedback control loop maintains a predetermined minimum power to the cold cathode fluorescent lamp by keeping the overlap between the third switch and the first switch to a minimum. LCD display system.   The feedback signal indicates a voltage across the cold cathode fluorescent lamp, and the state where the fluorescent lamp is open is indicated when the voltage exceeds a predetermined threshold for a predetermined length of time. Item 12. A liquid crystal display system according to item 11. A first capacitor coupled to the primary transformer winding and ground potential;
The liquid crystal display system of claim 11, further comprising: a second capacitor coupled to the primary transformer winding and the potential input.   12. The liquid crystal display system of claim 11, further comprising an input voltage source coupled to the switch for supplying current to the switch.   The liquid crystal display system according to claim 11, wherein the input voltage source is a power source.   12. The liquid crystal display system according to claim 11, wherein the feedback signal indicates a current passing through the cold cathode fluorescent lamp, and a state where the fluorescent lamp is open is indicated when the current is smaller than a predetermined threshold value. . A liquid crystal display board;
A cold cathode fluorescent lamp for illuminating the liquid crystal display panel;
A secondary transformer winding coupled to the cold cathode fluorescent lamp to supply current to the cold cathode fluorescent lamp;
A primary transformer winding coupled to the secondary transformer winding to provide magnetic flux to the secondary transformer winding;
A first switch coupled to the primary transformer winding such that current flows through the primary transformer winding in a first direction;
A second switch coupled to the primary transformer winding such that current flows in a second direction through the primary transformer winding;
Configured to supply current to the primary transformer winding when an overlap state exists between the third switch and the first switch, and the first transformer winding and the first switch Coupled to the cold cathode fluorescent lamp, coupled to the third switch, receiving a feedback signal from the cold cathode fluorescent lamp, and maintaining a minimum overlap between the third switch and the first switch, A liquid crystal display system comprising: a feedback control loop circuit that maintains a predetermined minimum power to the cold cathode fluorescent lamp.   The liquid crystal display of claim 21, further comprising an input voltage source coupled to the first switch and the second switch for supplying current to the first switch and the second switch. system.   The liquid crystal display system according to claim 22, wherein the input voltage source is a power source. In a method for controlling power to a cold cathode fluorescent lamp in a liquid crystal display system,
Providing a pulse signal to the transistor for a conduction path to the primary transformer winding;
Generating a feedback signal from a cold cathode fluorescent lamp coupled to a secondary transformer winding indicating an electrical condition in the cold cathode fluorescent lamp;
Receiving the feedback signal from the cold cathode fluorescent lamp;
Adjusting the power to the cold cathode fluorescent lamp if the feedback signal indicates ignition of the cold cathode fluorescent lamp.   25. The method of claim 24, wherein the feedback signal indicates a voltage across the cold cathode fluorescent lamp, and ignition of the cold cathode fluorescent lamp is indicated when the voltage is below a predetermined threshold.   The method of claim 24, wherein the feedback signal indicates a current through the cold cathode fluorescent lamp, and ignition of the cold cathode fluorescent lamp is indicated when the current is greater than a predetermined threshold.   25. The method of claim 24, further comprising maintaining a predetermined minimum amount of power to the cold cathode fluorescent lamp when the return signal indicates no ignition. Providing a second pulse signal to a second transistor for a second conductive path to the primary transformer winding;
Providing a third pulse signal to a third transistor for the second conductive path to the primary transformer winding;
28. The method of claim 27, further comprising: maintaining a minimum overlap between the transistor and the third transistor. 25. The method of claim 24, further comprising shutting off power to the cold cathode fluorescent lamp when the feedback signal indicates no ignition for a predetermined length of time.

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