JP2005353244A - Word line control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress current caused to flow to a node of voltage VBB when a word line is active. <P>SOLUTION: When access is started, a signal RST_n releases a reset state, and when an address signal Xc is inputted, a node A makes a transition from VPP to the level of VSS and a node B becomes at the level of VPP. Since a timing signal ASD is not activated even though a block selection signal RBS is activated, a node C is at the level of VDD and a WL is connected to ground through NTRs (n channel type transistor) 11 and 12. That is, the WL makes a transition from VPP to the level of VSS. After that, when the timing signal ASD is activated and the node C is transited to the level of VSS, an NTR 7 is turned on, the NTR 11 is turned off and the WL is disconnected from ground potential. Since an NTR 9 is turned on, the WL is at the level of VBB. Current caused to flow to a node of VBB is reduced to current corresponding to an electric difference between VSS and VBB. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a word line control circuit for driving a word line of a memory cell of a semiconductor memory device, and more particularly to a word line control circuit for driving a word line of a memory cell of a semiconductor memory device mixed with logic in a system LSI. .

  In recent years, semiconductor processing technology has been miniaturized, and a system LSI in which logic and memory are integrated on a single chip has been developed. Various memories, such as SRAM and DRAM, have been developed as memories. In a system LSI in which a large-capacity memory is mixed with logic, a DRAM with a high degree of integration, that is, a small area per bit is mounted. However, the chip size is reduced, and it is advantageous in terms of yield and cost.

  However, in the conventional general-purpose DRAM chip manufacturing process, the manufacturing process of the memory capacitor portion of the DRAM is complicated. Therefore, when manufacturing a system LSI based on a CMOS process, a manufacturing process of a memory cell such as a general-purpose DRAM. It is accompanied by difficult process development to load a DRAM using a chip. Thus, a DRAM having a planar capacitor structure as a memory capacitor has been proposed and developed (for example, Patent Document 1). Hereinafter, the outline will be described with reference to FIG. FIG. 9 is a diagram for explaining a memory cell of a DRAM.

  In FIG. 9, both the access transistor 31 and the memory cell capacitor 32 are P-channel transistors. The gate electrode of the access transistor 31 is connected to the word line (WL) 33, and the drain electrode is connected to the bit line (BL) 34. The source electrode and the drain electrode of the memory cell capacitor 32 are commonly connected to the source electrode of the access transistor 31, and the cell plate potential VCP is applied to the gate electrode.

  Data is written to the memory cell capacitor 32 via the access transistor 31 by applying the potential of the write data to the BL 34 from a sense amplifier (not shown) and activating the WL 33 to turn on the access transistor 31. Further, data is read by activating WL33 and turning on the access transistor 31, thereby taking out the charge accumulated in the memory cell capacitor 32 to the BL34 via the access transistor 31 and inputting it to a sense amplifier (not shown). Get bit data. As described above, the memory cell shown in FIG. 9 operates as a DRAM.

  Here, in the memory cell shown in FIG. 9, since data (charge) written in the memory cell capacitor 32 is lost due to various leak currents as time elapses, a refresh operation must be performed. If the interval is short, the current consumption increases. Therefore, it is important to suppress the leakage current and widen the refresh operation interval. In particular, it is important to suppress leakage (off leakage) through the channel of the access transistor 31.

  Therefore, as shown in FIG. 9, the amplitude voltage of BL34 is in the range of power supply voltage VDDS to ground potential VSS, but the amplitude voltage of WL33 that controls the gate electrode of access transistor 31 is in the range of voltage VPP to voltage VBB. It is. Here, the voltage VPP is a voltage (VPP = VDD + Vtp1) obtained by adding a voltage Vtp1 of Vtp1 = 0.2V to 0.5V to the power supply voltage VDDS. By applying voltage VPP obtained by slightly boosting power supply voltage VDDS to the gate electrode of access transistor 31, off-leakage of access transistor 31 can be suppressed.

  Further, since the access transistor 31 is a P-channel transistor, the value near the absolute value of the threshold voltage of the access transistor 31 is set to Vtp2 (Vtp2 = 0.2V) when WL33 is active in order to read / write the ground potential VSS of BL34. ˜0.5 V), the voltage VBB is set to VBB = VSS−Vtp2. Thus, sufficient writing of the ground potential VSS level can be performed.

  Note that the voltage VPP and the voltage VBB are usually not generated from the outside of the chip, but are generated from the power supply voltage VDD and the ground potential VSS supplied from the outside. That is, the internal power supply includes a VPP generation circuit that generates a voltage VPP of VPP = VDD + Vtp1, and a VBB generation circuit that generates a voltage VBB of VBB = VSS−Vtp2.

  In other words, the word line control circuit receives the supply of the voltage VPP from the VPP generation circuit which is a positive power supply and the supply of the voltage VBB from the VBB generation circuit which is a negative power supply, and sets the voltage of the word line (WL33) of the memory cell. , A control circuit for driving in a voltage VPP to voltage VBB range, and various circuit configurations are used.

JP 2003-92364 A Japanese Patent Laid-Open No. 10-241361

  By the way, the node of the word line is connected to the gate electrodes of a plurality of memory access transistors, and further, the parasitic capacitance due to these wirings is added, resulting in a large capacitance. When the word line that does not access the memory cell is inactive, The battery is charged with the voltage VPP. Therefore, when the word line for accessing the memory cell is activated, when the word line is driven from the voltage VPP to the voltage VBB, a large discharge current flows through the VBB generation circuit that generates the voltage VBB. As a result, the generated voltage VBB becomes unstable, and there is a problem that the current consumption of the VBB generating circuit increases. Patent Document 2 discloses a method for reducing the current consumption of the VBB generation circuit when the word line is inactive.

  The present invention has been made in view of the above, and is provided with a mechanism that suppresses a current flowing to the node of the voltage VBB when the word line is activated so that the word line can be activated by the more stabilized voltage VBB. An object is to obtain a line control circuit.

  In order to achieve the above-described object, according to the present invention, a first voltage higher than a ground potential is applied to an access transistor in a memory cell of a semiconductor memory device in a standby state, and a ground voltage is applied to activate the access to the memory cell. When a second voltage lower than the potential is applied, the voltage level of the word line connected to the access transistor transitions from the first voltage to the ground potential level in response to the end of standby when activated. And transition control means for making a transition from the ground potential to the level of the second voltage in response to a predetermined timing signal generated thereafter.

  According to the present invention, the discharge current flowing through the circuit that generates the second voltage when the word line is activated becomes a current corresponding to the difference between the ground potential and the second voltage, and can be reduced. Accordingly, it is possible to prevent the voltage level of the word line at the time of activation from becoming unstable, and to reduce current consumption.

  According to the present invention, it is possible to prevent the voltage level of the word line at the time of activation from becoming unstable and to reduce the current consumption.

  Exemplary embodiments of a word line control circuit according to the present invention will be explained below in detail with reference to the drawings.

Embodiment 1 FIG.
1 is a circuit diagram showing a configuration of a word line control circuit according to a first embodiment of the present invention. In FIG. 1, address signals Xa and Xb are applied to input terminals of a two-input NAND circuit 1. The output terminal of the NAND circuit 1 is connected to the source electrode of an N-channel transistor (hereinafter referred to as “NTR”) 2. An address signal Xc is applied to the gate electrode of NTR2, and the back gate is connected to the ground (potential VSS). The drain electrode of NTR2 is connected to the drain electrodes of P-channel transistors (hereinafter referred to as “PTR”) 3 and 4 and the gate electrodes of PTR5 and NTR6. This connection line is hereinafter referred to as “node A”.

  The source electrode of PTR3 is connected to the power supply (voltage VPP) together with the back gate, and the word line reset signal RST_n is applied to the gate electrode. The source electrode of PTR4 is connected to the power supply (voltage VPP) together with the back gate, and the gate electrode is connected to the commonly connected drain electrodes of PTR5 and NTR6. The source electrode of PTR5 is connected to the power supply (voltage VPP) together with the back gate, and the source electrode of NTR6 is connected to the ground (potential VSS) together with the back gate.

  The commonly connected drain electrodes of PTR5 and NTR6 are connected to the source electrode of PTR7, the gate electrode of PTR10, and the gate electrode of NTR12. This connection line is hereinafter referred to as “node B”. A source electrode of the PTR 10 is connected to a power source (voltage VPP) together with a back gate.

  The back gate of PTR 7 is connected to the power supply (voltage VPP), and the drain electrode is connected to the drain electrode of NTR 8 and the gate electrode of NTR 9. The gate electrode of the PTR 7 is connected to a connection line between the output terminal of the NAND circuit 13 and the gate electrode of the NTR 11. This connection line is hereinafter referred to as “node C”.

  The drain electrode of PTR10 is connected to the drain electrode of NTR9, the gate electrode of NTR8, and the drain electrode of NTR11. A word line WL is connected to this connection end. The source electrode and back gate of NTR 8 and the source electrode and back gate of NTR 9 are commonly connected to a power supply (voltage VBB).

  The source electrode of NTR11 is connected to the drain electrode of NTR12. The back gate of the NTR 11 is connected to the ground (potential VSS) together with the back gate and the source electrode of the NTR 12. A row block selection signal RBS and a timing signal ASD are applied to the input terminal of the NAND circuit 13.

  Next, the operation of the word line control circuit according to the first embodiment configured as described above will be described with reference to FIGS. FIG. 2 is a waveform diagram for explaining the operation of the word line control circuit shown in FIG. Address signals Xa, Xb, and Xc are address signals generated by an address predecode circuit included in an array control circuit (not shown). In the standby state, both are at the ground potential VSS level. At the time of access, first, the address signals Xa and Xb are generated to rise to the power supply voltage VDD level, and then the address signal Xc is generated to rise to the power supply voltage VDD level.

  The word line reset signal RST_n is a reset signal generated by the array control circuit, and is at the ground potential VSS level at the time of resetting and at the voltage VPP level at the time of release. In addition, the row block selection signal RBS and the timing signal ASD according to this embodiment are control signals generated by the array control circuit.

  That is, the row block selection signal RBS is generated to select and designate a row block including a word line control circuit corresponding to a given address (Xa, Xb, Xc). The timing signal ASD is generated to determine the timing for transitioning the word line WL to the ground potential VSS level. Both are at the level of the ground potential VSS in the standby state and at the level of the power supply voltage VDD at the time of access.

  Now, in the standby state, the reset process by the word line reset signal RST_n is executed, so that the PTR 3 is in the ON operation state and the node A is precharged to the level of the voltage VPP. As a result, since the NTR 6 is in the ON operation state, the node B is at the level of the ground potential VSS. The PTR 10 is in an ON operation state, and the word line WL is at the level of the voltage VPP.

  In this state, both the row block selection signal RBS and the timing signal ASD are at the level of the ground potential VSS, so that the node C is at the level of the power supply voltage VDD. As a result, PTR7 is in the off operation state, NTR8 is in the on operation state, and NTR9 reliably maintains the off operation, so that the word line WL is set to the level of the voltage VPP. Although the NTR 11 is in the ON operation state, the NTR 12 is OFF because the node B is at the level of the ground potential VSS. Therefore, the word line WL and the ground (potential VSS) are not connected.

  When the access is started, first, the word line reset signal RST_n rises to the level of the voltage VPP, and the reset state is released. As a result, the PTR 3 performs an off operation. However, since the PTR 4 continues the on operation, the level of the node A is maintained at the level of the voltage VPP. After a predetermined timing, the address signals Xa and Xb are generated to rise to the level of the power supply voltage VDD, and the address signal Xc is generated to rise to the level of the power supply voltage VDD with a slight delay.

  As a result, since the node A transitions to the level of the ground potential VSS at the timing when the address signal Xc rises to the level of the power supply voltage VDD, the NTR 6 performs the off operation and the PTR 5 performs the on operation. As a result, the node B transitions to the level of the voltage VPP, and the PTR 10 performs the off operation.

  Here, the row block selection signal RBS rises to the level of the power supply voltage VDD at the timing when the word line reset signal RST_n rises to the level of the voltage VPP, but the timing signal ASD is the timing at which the address signal Xc rises to the level of the power supply voltage VDD. Thereafter, the level rises from the ground potential VSS level to the level of the power supply voltage VDD. Therefore, at the timing when the node B transitions to the level of the voltage VPP as described above, the level of the node C remains the level of the power supply voltage VDD.

  Therefore, the PTR 7 does not perform the on operation and maintains the off operation state, so that the voltage VPP of the node B is not transmitted to the gate electrode of the NTR 9 and the NTR 9 maintains the off operation state. That is, the word line WL is not connected to the power supply (voltage VBB). On the other hand, when the node B transitions to the level of the voltage VPP, the NTR 12 performs an on operation. Since the NTR 11 maintains the ON operation state, the word line WL is connected to the ground (potential VSS) via the NTR 11 and NTR 12 and transits from the voltage VPP to the level of the ground potential VSS.

  In the memory cell shown in FIG. 9, since the access transistor 31 is turned on even when WL33 is at the level of the ground potential VSS, data is sent to BL34 and input to the sense amplifier. That is, reading can be performed even when WL33 is at the level of the ground potential VSS.

  However, in a state where WL33 is at the level of the ground potential VSS, data at the VSS level cannot be written. This is because the threshold value during writing of the access transistor 31 is not exceeded. Therefore, in an array control circuit (not shown), the address signals Xa, Xb, and Xc are raised to the level of the power supply voltage VDD, and then the timing signal ASD is raised from the level of the ground potential VSS to the level of the power supply voltage VDD after a predetermined time has elapsed. I try to raise it.

  When the timing signal ASD rises to the level of the power supply voltage VDD, the node C falls to the level of the ground potential VSS, so that the PTR 7 is turned on and the NTR 11 is turned off. When the NTR 11 is turned off, the word line WL is disconnected from the ground potential VSS. At the same time, since the PTR 7 is turned on, the NTR 9 is turned on by the voltage VPP level of the node B, and the word line WL is connected to the power supply (voltage VBB) via the NTR 9 and transits to the level of the voltage VBB. . As a result, the word line WL is activated to the level of the voltage VBB, and sufficient writing at the ground potential VSS level is performed on the selected memory cell.

  Here, assuming that the capacity of the word line WL is Cw, the conventional word line control circuit discharges the charge Cw × (VPP−VBB) generated by the potential difference between the voltage VPP to the voltage VBB to the node of the voltage VBB. On the other hand, in the first embodiment, it is only necessary to discharge the charge Cw × (VSS−VBB) generated by the potential difference between the ground potential VSS to the voltage VBB to the node of the voltage VBB, so that the discharge current can be reduced. VBB can be further stabilized.

  However, in order to make this possible, the voltage VBB needs to be set in a range of -0.6V to -0.2V. This is because when the voltage VBB is on the minus side of −0.6 V, the drain electrode of the NTR 11 and the pn junction of the substrate become a forward bias, and a current flows from the substrate to the node of the word line. Further, since the node C is at the level of the ground potential VSS, it is necessary to set the potential difference between the ground potential VSS and the voltage VBB to be smaller than the threshold voltage Vth of the NTR 11 so that the NTR 11 is not turned on. is there.

  Therefore, according to the first embodiment, by appropriately setting the threshold voltage of NTR 11 driven by the value of voltage VBB and the voltage level of node C, voltage VBB is directly applied from voltage VPP when the word line is activated. In addition, the ground potential VSS in the middle is also adopted as the transition level, and at the time of reading and writing, the voltage VPP is temporarily changed to the ground potential VSS, and then the ground potential VSS is changed to the voltage VBB. Therefore, it is possible to reduce the discharge current for the circuit that generates the voltage VBB, and to stabilize the voltage VBB and reduce the current consumption.

Embodiment 2. FIG.
FIG. 3 is a circuit diagram showing a configuration of a word line control circuit according to the second embodiment of the present invention. In FIG. 3, the same reference numerals are given to components that are the same as or equivalent to the components shown in FIG. 1 (Embodiment 1). Here, the description will focus on the parts related to the second embodiment.

  That is, as shown in FIG. 3, in the second embodiment, the back gates of NTR11 and NTR12 are connected not to ground (potential VSS) but to the power supply (voltage VBB).

  Thus, if the back gate potential of NTR11 and NTR12 is set to the level of voltage VBB, the pn junction of the drain electrode of NTR11 is forward biased, so that the current flowing from the substrate toward the word line WL is reduced. Can be blocked. However, in order to realize this, since the node C is at the level of the ground potential VSS, the potential difference between the voltage VSS and the voltage VBB needs to be smaller than the threshold voltage of the NTR11.

Embodiment 3 FIG.
FIG. 4 is a circuit diagram showing a configuration of a word line control circuit according to Embodiment 3 of the present invention. In FIG. 4, the same or similar components as those shown in FIG. 1 (Embodiment 1) are denoted by the same reference numerals. Here, the description will be focused on the portion related to the third embodiment.

  As shown in FIG. 4, in the third embodiment, the potentials applied to the source electrodes and back gates of NTR8 and NTR9 are changed in the configuration shown in FIG. 1 (first embodiment). That is, the source electrodes of NTR8 and NTR9 are connected to the power supply (voltage VBB), but the back gates of NTR8 and NTR9 are connected to the ground (potential VSS) instead of the power supply (voltage VBB).

  In this way, if the NTR8 and NTR9 back gate potentials are set to the level of the ground potential VSS, the NTR substrates constituting the circuit are all at the ground potential VSS, so the VSS substrate and the VBB substrate are connected to each other. A triple well structure for electrical insulation is not required. Therefore, the process steps for creating the triple well structure can be omitted, and the manufacturing cost of the chip can be reduced.

  However, when the NTR8 and NTR9 back gate potentials are set to the level of the ground potential VSS, they are connected to the power supply of the voltage VBB, so that a current may flow in the pn forward direction between the source and drain. There is. In order to prevent this, the voltage VBB needs to be set to a plus side with respect to −0.6 V so as not to exceed the barrier threshold of the pn junction.

Embodiment 4 FIG.
FIG. 5 is a circuit diagram showing a configuration of a word line control circuit according to the fourth embodiment of the present invention. In FIG. 5, the same or similar components as those shown in FIG. 4 (Embodiment 3) are denoted by the same reference numerals. Here, the description will be focused on the portion related to the fourth embodiment.

  That is, as shown in FIG. 5, in the word line control circuit 18 according to the fourth embodiment, in the configuration shown in FIG. 4 (third embodiment), the source electrodes of NTR8 and NTR9 are not connected to the power source (voltage VBB). Rather, it is connected to the output terminal of the negative voltage setting circuit 20. The negative voltage setting circuit 20 generates a negative voltage setting signal (hereinafter referred to as “VNEGB”) under the control of the row block selection signal RBS.

  The negative voltage setting circuit 20 will be described. That is, in FIG. 5, the row block selection signal RBS is applied to each gate electrode of the PTR 21 and the NTR 22. The source electrode of the PTR 21 is connected to the power supply (voltage VDD) together with the back gate, and the source electrode of the NTR 22 is connected to the ground (potential VSS) together with the back gate. The drain electrodes of PTR21 and NTR22 are connected to the gate electrodes of PTR23 and NTR24.

  The source electrode of the PTR 23 is connected to the power supply (voltage VDD) together with the back gate, and the source electrode of the NTR 24 is connected to the power supply (voltage VBB) together with the back gate. The drain electrodes of PTR 23 and NTR 24 are connected to the gate electrode of NTR 25. A source electrode of the NTR 25 is connected to a power source (voltage VBB) together with a back gate. The drain electrode of NTR25 is connected to the drain electrode and base electrode of NTR26, constitutes the output end of VNEGB, and the source electrodes of NTR8 and NTR9 are connected. This connection line is referred to as a VNEGB node. The source electrode of the NTR 26 is connected to the ground (potential VSS), and the back gate is connected to the power supply (voltage VBB).

  Next, the operation will be described with reference to FIGS. FIG. 6 is a waveform diagram for explaining the operation of the word line control circuit shown in FIG. 5 and 6, in the standby state, the reset process is executed by the word line reset signal RST_n, so that the PTR 3 is in the ON operation state, and the node A is precharged to the level of the voltage VPP. As a result, since the NTR 6 is in the ON operation state, the node B is at the level of the ground potential VSS. The PTR 10 is in an ON operation state, and the word line WL is at the level of the voltage VPP.

  In this state, both the row block selection signal RBS and the timing signal ASD are at the level of the ground potential VSS, so that the node C is at the level of the power supply voltage VDD. As a result, PTR7 is in the off operation state, NTR8 is in the on operation state, and NTR9 reliably maintains the off operation, so that the word line WL is set to the level of the voltage VPP. Although the NTR 11 is in the on operation state, the NTR 12 is in the off operation when the node B is at the level of the ground potential VSS, so that the word line WL and the ground (potential VSS) are not connected.

  In the negative voltage setting circuit 20, when the row block selection signal RBS is at the level of the ground potential VSS, the PTR 21 is in an on operation state. As a result, the NTR 24 is turned on, the voltage VBB is applied to the gate electrode of the NTR 25, and the NTR 25 is turned off. That is, the VNEGB node is disconnected from the power supply (voltage VBB).

  When the access is started, as described in the first embodiment, first, the word line reset signal RST_n rises to the level of the voltage VPP, and the reset state is released. The row block selection signal RBS rises to the level of the power supply voltage VDD at the timing when the word line reset signal RST_n rises to the level of the voltage VPP. As a result, in the negative voltage setting circuit 20, the NTR 22 is turned on and the PTR 23 is turned on, so that the power supply voltage VDD is applied to the gate electrode of the NTR 25 and the NTR 25 is turned on. As a result, the VNEGB node is connected to the power supply (voltage VBB) via the NTR 25 and transits to the level of the voltage VBB.

  Thereafter, as described in the first embodiment, the address signals Xa and Xb rise to the level of the power supply voltage VDD and the address signal Xc rises to the level of the power supply voltage VDD with a slight delay in the array control circuit (not shown). Is generated. The word line WL is connected to the ground (potential VSS) via NTR11 and NTR12, and transits from the level of the voltage VPP to the level of the ground potential VSS. Further, the operation of raising the timing signal ASD to the level of the power supply voltage VDD is performed in the array control circuit (not shown), and the operation in which the word line WL is changed from the level of the ground potential VSS to the level of the voltage VBB is similarly performed. Is called.

  Thus, according to the fourth embodiment, when selected by the row selection signal, the word line WL is changed from the level of the ground potential to the level of the voltage VBB, and when not selected by the row selection signal, the word line WL is changed. It can be held at the level of ground potential. Therefore, the configuration shown in the fifth embodiment can be realized.

  Here, at the time of standby in the above operation process, the potential of the VNEGB node rises due to the off-leakage of the NTR 9 when the standby state continues. Since it is clamped, it does not rise above the potential of VSS + Vthn1.

  Therefore, if the potential of the VNEGB node is VSS + Vthn1, paying attention to the NTR8, the voltage applied between the gate and the source of the NTR8 is VPP− (VSS + Vthn1). On the other hand, in the case shown in FIG. 4, for example, the voltage applied between the gate and source of the NTR 8 during standby is VPP-VBB. Since this voltage level is higher than the level of the power supply voltage VDD, the configuration shown in FIG. 4 and the like may reduce the reliability of the transistors (NTR8 and NTR9).

  That is, in the fourth embodiment, VNEGB generated by the negative voltage setting circuit 20 having the configuration shown in FIG. 5 is applied to the source electrodes of NTR8 and NTR9, so that the gates and sources of NTR8 and NTR9 are connected during standby. Since the applied voltage can be reduced, the reliability of the transistors (NTR8, NTR9) can be improved.

Embodiment 5 FIG.
FIG. 7 is a block diagram showing a configuration of a word line control circuit sub-block according to the fifth embodiment of the present invention. FIG. 8 is a diagram showing a word line control circuit block configured by the word line control circuit sub-block shown in FIG. In the fifth embodiment, a more general configuration example in which the word line control circuit shown in the fourth embodiment is expanded is shown.

  In FIG. 7, in the word line control circuit sub-block 30, n word line control circuits 18 and VNEGB terminals (source electrodes of NTR8 and NTR9) of each of the n word line control circuits 18 are connected in parallel. And a negative voltage setting circuit 20. The row block selection signal RBS that controls the negative voltage setting circuit 20 rises to the power supply voltage VDD when the word line control circuit sub-block 30 is selected. That is, it activates. When not selected, it is at the level of the ground potential VSS.

  As described in the fourth embodiment, when the row block selection signal RBS is activated, VNEGB = VBB. Further, when not selected, it is clamped to VNEGB = VSS + Vthn1. Such VNEGB is applied to the VNEGB terminals of each of the n word line control circuits 18, that is, the source electrodes of NTR8 and NTR9 shown in FIG.

  In FIG. 8, the word line control circuit block 40 is configured by m word line control circuit sub-blocks 30 including n word line control circuits 18. A row block selection signal RBS corresponding to the row block selection signal RBS <0> to the row block selection signal RBS <m> is input to the m word line control circuit sub-blocks 30.

  When a word line control circuit sub-block 30 is selected, the corresponding row block selection signal RBS is activated, and the row block selection signal RBS corresponding to the other non-selected word line control circuit sub-block 30 is inactive. (Ground potential VSS). Only the VNEGB terminal of the word line control circuit 18 in the selected word line control circuit sub-block 30 is at the level of the voltage VBB.

  At this time, the activated word line control circuit 18 is only one of n in the selected word line control circuit sub-block 30, but in the selected word line control circuit sub-block 30. The VNEGB terminals of all the word line control circuits 18 are all at the level of the voltage VBB.

  Thus, according to the fifth embodiment, the source electrodes of the two transistors controlled when the voltage level of the word line is changed from the ground potential VSS to the level of the voltage VBB in each of the plurality of word line control circuits. In the word line control circuit that controls the selected word line when it is included in the block to which the memory cell to be accessed belongs according to the row block selection signal RBS, the voltage level of the word line is changed from the voltage VPP to the ground potential VSS. Until the period during which the transition operation is performed, the voltage level is set to a voltage level near the ground potential that is higher than the voltage VBB. Set and included in the block to which the memory cell that is not accessed belongs In the word line control circuit for controlling the word line can be set to a voltage level near higher ground than the voltage VBB.

  In each of the above-described embodiments, a sense amplifier activation signal can be used instead of the timing signal ASD. The array control circuit generates a sense amplifier activation signal so that the sense amplifier is activated after a predetermined timing after the word line WL is activated. There is no need to generate such a new timing signal ASD.

  As described above, the word line control circuit according to the present invention is useful for suppressing the current flowing through the node of the voltage VBB when the word line is activated.

1 is a circuit diagram showing a configuration of a word line control circuit according to Embodiment 1 of the present invention. FIG. It is a wave form diagram explaining operation | movement of the word line control circuit shown in FIG. It is a circuit diagram which shows the structure of the word line control circuit by Embodiment 2 of this invention. It is a circuit diagram which shows the structure of the word line control circuit by Embodiment 3 of this invention. It is a circuit diagram which shows the structure of the word line control circuit by Embodiment 4 of this invention. FIG. 6 is a waveform diagram for explaining the operation of the word line control circuit shown in FIG. 5. It is a block diagram which shows the structure of the word line control circuit subblock by Embodiment 5 of this invention. It is a figure which shows the word line control circuit block comprised by the word line control circuit subblock shown in FIG. It is a figure explaining the memory cell of DRAM.

Explanation of symbols

1,13 NAND circuit 2,6,8,9,11,12,22,24,25,26 NTR (N-channel transistor)
3, 4, 5, 10, 21, 23 PTR (P-channel transistor)
18 Word line control circuit 19 Negative voltage setting circuit 30 Word line control circuit sub-block 40 Word line control circuit block

Claims (9)

In the case where the access transistor in the memory cell of the semiconductor memory device is applied with a first voltage higher than the ground potential during standby, and a second voltage lower than the ground potential during activation for accessing the memory cell. ,
When activated, the voltage level of the word line connected to the access transistor is changed from the first voltage to the ground potential level in response to the end of standby, and in response to a predetermined timing signal generated thereafter. Transition control means for transitioning from a ground potential to the level of the second voltage;
A word line control circuit comprising: Sources of two transistors, which are final stage transistors that directly control the voltage level of the word line and are controlled when the transition control means changes the voltage level of the word line from the ground potential to the level of the second voltage. The potential of the electrode is set to a voltage level in the vicinity of the ground potential that is higher than the second voltage until the transition control means performs an operation of transitioning the voltage level of the word line from the first voltage to the ground potential. When the transition control means changes the voltage level of the word line from the ground potential to the level of the second voltage, a control signal for distinguishing between a block to which a memory cell to be accessed belongs and a block to which a memory cell not to be accessed is accessed Voltage setting means for setting the level of the second voltage to indicate that the memory cell belongs to the block
The word line control circuit according to claim 1, comprising: A plurality of word line control circuits according to claim 1;
A final stage transistor that directly controls the voltage level of the word line in each of the plurality of word line control circuits, wherein the transition control means transitions the voltage level of the word line from the ground potential to the level of the second voltage. Select the potential of the source electrodes of the two transistors controlled to be included in the block to which the memory cell to be accessed belongs according to a control signal that distinguishes between the block to which the memory cell to be accessed belongs and the block to which the memory cell that does not access belongs In the word line control circuit for controlling the word line, the ground is higher than the second voltage until the transition control means performs the operation of transitioning the voltage level of the word line from the first voltage to the ground potential. While setting the voltage level near the potential, the transition control means In a word line control circuit for controlling a word line included in a block to which a memory cell that is not accessed belongs by setting the voltage level of the first line to the level of the second voltage when transitioning from the ground potential to the level of the second voltage. Voltage setting means for setting the voltage level in the vicinity of the ground potential higher than the second voltage;
A word line control circuit comprising: The transition control means includes
Only when the predetermined timing signal is generated, the control signal for distinguishing between the block to which the memory cell to be accessed belongs and the block to which the memory cell to be accessed belongs indicates that the block to which the memory cell to be accessed belongs. Perform the transition to the two voltage level,
The word line control circuit according to any one of claims 1 to 3. In the transition control means, the means for making a transition from the first voltage to the level of the ground potential is:
A first transistor that performs an off operation during standby and performs an on operation until activation at the time of activation, and performs the on operation within a period until the predetermined timing signal is generated during standby and activation. A circuit in which a second transistor that is turned off after the signal is generated is arranged in series between the word line and the ground potential, and the potential of each back gate of the two transistors is the ground potential or the second potential. 4. The word line control circuit according to claim 1, wherein the word line control circuit is at a voltage level.   The voltage threshold value of the second transistor performing the off operation when the level of the word line transitions from the ground potential to the level of the second voltage is larger than the potential difference between the ground potential and the second voltage. The word line control circuit according to claim 5.   The potentials of the back gates of the two transistors that are the final stage transistors that directly control the voltage level of the word line and to which the second voltage is applied to the source electrode are the ground potential or the level of the second voltage. The word line control circuit according to claim 1, wherein:   4. The word line control circuit according to claim 2, wherein a potential of a back gate of the two transistors is a second voltage level. The word line control circuit according to claim 1, wherein the predetermined timing signal is a sense amplifier activation signal.

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