JP2005326793A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To appropriately set a current flowing in the light-emitting element of a display device. <P>SOLUTION: The drive current is supplied via drive TFT 202 and drive control TFT 204 to an organic EL element 201. The gate and drain of the drive TFT 202 are connected with each other by a reset TFT 203, and the gate of the drive TFT 202 is connected via a reset capacitor 207 and a selection TFT 205 to a date line 107. Also, the junction of the selection TFT 205 and the reset capacitor 207 is connected by a holding capacitor 206 to a fixed potential line 212. The data potential is set at the gate of the drive TFT 202, after the gate has been reset at its threshold voltage, by setting the data line 107 at the reset potential in a first half of one horizontal period and setting the same at the data potential in a second half. In addition, a display period is limited by only resetting, when the data are written about a pixel circuit of the other horizontal line. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an active matrix display device, and more particularly to a display element using a diode-type light-emitting element that emits light by a drive current.

  In recent years, computerization has progressed, and portable information terminals have been required to have processing capabilities comparable to those of personal computers. Along with this, video display devices are also required to have high definition and high quality, and thin, lightweight, high viewing angle, and low power consumption are desired.

  In order to meet this demand, development of a display device (display) in which thin film active elements (thin film transistors, thin film transistors, or simply TFTs) are formed in a matrix on a glass substrate, and electro-optical elements are formed on the thin film active elements has been developed. Has been done.

  The main substrate for forming active elements is a pattern in which a semiconductor film such as amorphous silicon or polysilicon is formed, patterned, and connected by metal wiring. Due to the difference in the electrical characteristics of the active elements, the former requires a driving IC (Integrated Circuit), and the latter has a feature that a driving circuit can be formed on a substrate.

  Currently, the liquid crystal display (Liquid Crystal Display or just LCD) widely used is the former amorphous silicon type for large-sized ones, but the latter polysilicon type is the mainstream for medium and small size. It is becoming.

  Only the polysilicon type is mass-produced as an electroluminescence type (organic EL) display that is self-luminous and has features such as thinness, light weight, and high viewing angle.

  In general, when an organic EL element is combined with a TFT, the current is controlled using its voltage-current control action. The current-voltage control action here refers to an action of controlling the current between the source and the drain by applying a voltage to the gate terminal of the TFT. By doing so, the emission intensity can be adjusted, and a desired gradation can be displayed.

  However, since such a configuration is adopted, the light emission intensity of the organic EL element is very sensitively influenced by the characteristics of the TFT. In particular, it has been confirmed that polysilicon TFTs, especially polysilicon TFTs formed by a low-temperature process called low-temperature polysilicon, have a relatively large difference in electrical characteristics between adjacent pixels. This is one of the major factors that degrade the quality, particularly the display uniformity within the screen.

  A conventional technique for improving this is disclosed in Patent Document 1. The prior art discloses means for correcting the threshold voltage of a polysilicon TFT 365 for driving an organic EL element as shown in FIG.

  The illumination line 340 and the auto-zero illumination line 330 are set to L level to turn on the TFTs 375 and 370, and the select line 320 is set to L level to set the data line 310 to a reference voltage higher than the maximum voltage of the data signal. As a result, the gate voltage of the TFT 365 is set to the threshold voltage of the TFT 365. As a result, the difference between the threshold voltage Vth and the reference voltage is charged in the capacitor 350, and the difference between the threshold voltage Vth and the power supply voltage + Vdd is charged in the capacitor 355.

  Next, the illumination line 340 and the auto-zero illumination line 330 are set to the H level, the TFTs 375 and 370 are turned off, and a data signal is set to the data line 340 in this state. As a result, the gate voltage of the TFT 365 is shifted. This gate voltage corresponds to the threshold voltage of the TFT 365, and the threshold voltage of the TFT 365 in each pixel can be compensated.

  Then, the illumination line 340 is set to L level, the TFT 375 is turned on, a current corresponding to the gate voltage at which the TFT 365 is set is supplied to the OLED 380, and the OLED 380 emits light. Further, even after the select line 320 becomes H level, the gate voltage of the TFT 365 is maintained as it is, and a current corresponding to the data signal flows to the OLED 380.

  That is, in the prior art shown in FIG. 12, the potential Vg applied to the gate terminal of the TFT 365 is expressed as Vg = Vth + Vd * Cc / (Cc + Cs). Here, Vth is a threshold voltage of the TFT 365, Vd is a gradation voltage, and Cc and Cs are capacitance values shown in FIG. Thus, since the threshold voltage Vth of the TFT 365 of each pixel is always added to Vg, even if Vth has a different value for each pixel, an offset can be given to Vg without changing the gradation voltage Vd. it can.

  Non-Patent Document 1 shows an example in which the circuit of FIG. 12 is applied to a display, and a QVGA (320 × 240) panel is prototyped.

Special table 2002-514320 Proceedings "SID99Digest", published in 1999, p. 438

  Here, in order to actually apply the conventional example of FIG. 12 to the display panel, the capacitors Cc and Cs need to hold the potential for one frame period (for example, about 16.7 ms), and therefore need a certain value. Become. For example, assuming that about 0.2 pF is assigned, Vg = Vth + 0.5 * Vd. In this case, only a dynamic range half of the input gradation voltage can be obtained.

  In other words, in the conventional technique, the dynamic range of the input gradation voltage is required to exceed the dynamic range of the drive TFT 365, and the power consumption of the video circuit increases.

  Further, variations in capacitance values due to the manufacturing process of Cc and Cs and the influence of parasitic capacitance cannot be ignored. In fact, when the capacitance is formed by n + doping, an error of about several percent will exist in the dose amount, and it is assumed that the parasitic capacitance also exists in the order of several fF.

  For example, assuming that the variation in capacitance value is ± 1% and the parasitic capacitance is 5 fF, when Vg is calculated, a difference of about 4% occurs, and the difference reaches a level that can be recognized by the eyes in a dark halftone. .

  Further, although the conventional example of FIG. 12 includes four TFTs in a pixel, each of them increases leakage current due to external light. Normally, the top gate type polysilicon TFT, unlike the bottom gate type, has an active layer that is not shielded by a light shielding layer or the like and is exposed to external light. Therefore, when used under a certain degree of illumination, the potential held in the capacitors Cc and Cs leaks and does not operate normally.

  The present invention provides an active matrix display array in which a pixel-type light-emitting element driven by current and a plurality of thin-film transistors that control the diode-type light-emitting element are used as one pixel circuit, and the pixel circuits are arranged in a matrix, and the matrix Are provided corresponding to each column, and supplies a data signal to a pixel circuit in the corresponding column, a data driver for controlling the supply of the data signal to the data line, and precharges the data line. A precharge circuit, a selection line provided corresponding to each row of the matrix and supplying a selection signal to the pixel circuit of the corresponding row; a selection driver supplying a selection signal to the selection line; the data driver; A display device comprising: a charge circuit; and a control circuit that controls a selection driver. The element circuit includes a storage capacitor having a fixed potential at one end, a non-control terminal connected to the non-fixed potential terminal of the storage capacitor, a non-control terminal connected to the data line, and a control terminal connected to the data line. A selection transistor connected to a selection line; a drive transistor for controlling a drive current to the diode-type light-emitting element; a reset transistor for diode-connecting the drive transistor; and the diode-type light emission connected in series to the drive transistor. A drive control transistor for controlling on / off of the drive current of the element, and a reset capacitor having one end connected to the control terminal of the drive transistor and the other end connected to a non-control terminal to which the holding capacitor of the selection transistor is connected And the selection driver separately selects the odd lines and the even lines. Characterized in that the Gosuru.

  The active matrix display array, the data driver, the precharge circuit, and the selection driver are preferably formed on a single glass substrate.

  Further, the selection period of the selection line is divided into two, and in the first period, the line for writing the video and one or more lines of odd or odd to which the line for writing the video does not belong are reset and selected. It is preferable to perform reset selection a plurality of times in one frame period by selecting video writing only for the line in which the video is written in the period.

  In addition, it is preferable that the ratio between the display period and the reset period can be changed in one frame period.

  Furthermore, it is preferable to have a current measurement circuit that measures the total current value flowing through the active matrix display array, and to change the ratio between the display period and the reset period according to the current value of the current measurement circuit. .

  Furthermore, it is preferable to change the number of times of the multiple reset selection according to the current value of the current measuring circuit.

  The data driver has two or more signal buses for each of RGB, and the control circuit has two or more video circuits for supplying a video signal to each of the two or more signal buses, and the video circuit Switching means for switching to which signal bus the video signal supplied from the video signal is supplied. The switching means switches the connection between the signal bus and the video circuit for each line, and the connection differs for each frame. It is preferable to switch as described above.

  The present invention also provides a diode-type light-emitting element that is current-driven, a drive transistor that controls supply of a drive current to the diode-type light-emitting element, a storage capacitor that holds a voltage at a control terminal of the drive transistor, An active matrix display array in which a pixel circuit including a selection transistor that controls supply of a data signal to the storage capacitor is arranged in a matrix, and a pixel in a corresponding column provided corresponding to each column of the matrix A data line for supplying a data signal or a reset signal to the circuit, a selection line provided corresponding to each row of the matrix and supplying a selection signal for controlling a selection transistor in the pixel circuit of the corresponding row, and the selection line In a display device having a selection driver that supplies the selection signal, from the selection driver, A selection signal for one horizontal period is sometimes output to a plurality of selection lines, and a selection signal is output for a pixel circuit to which one of the plurality of selection signals output by the selection driver is supplied. In this case, after the control terminal voltage of the driving transistor is reset, a data signal is supplied, and for the other pixel circuits, only the control terminal voltage of the driving transistor is reset.

  The data line is divided into two horizontal periods, the reset signal is supplied to the first half, the data signal is supplied to the second half, and both the first and second half selection signals are supplied to one selection line. It is preferable to perform control so that the selection signal is supplied to the other selection lines only in the first half.

  In addition, according to the present invention, one of the controlled ends is connected to the data line, the other is connected to one end of the reset capacitor, and the data line and the reset capacitor are connected in accordance with the selection signal of the selection line connected to the control end. A select transistor to be controlled, a holding capacitor having one end connected to the potential fixing line, and the other end connected to the select transistor reset capacitor side end, a control end connected to the other end of the reset capacitor, and a controlled end One of the driving transistors connected to the power supply line, a reset transistor for controlling whether or not the driving transistor is diode-connected, and one of the controlled ends connected to the other controlled end of the driving transistor A drive control transistor for turning on and off the current from the transistor and the other controlled end of the drive control transistor are connected to the drive control transistor. A diode-type light emitting element that emits light by current supplied through the transistor and the drive control transistor, and with the data line set to a reference voltage, the selection transistor and the reset transistor are turned on, and the drive control transistor is turned off Then, the threshold voltage of the driving transistor is set to the control terminal of the driving transistor, and then the reset transistor is turned off and the data voltage is set to the data line, so that the control terminal voltage of the driving transistor is set according to the data voltage. The diode-type light emitting element is caused to emit light by the current flowing through the drive transistor by the control terminal voltage shifted according to the data voltage by turning on the drive control transistor and then turning on the drive control transistor.

  According to one aspect of the present invention, the pixel circuit is configured not to generate the gate voltage Vg of the driving TFT that drives the organic EL element at the ratio of the two storage capacitance values. For this reason, the dynamic range of the input gradation voltage is not required to be wider than the dynamic range of the gate voltage of the driving TFT. In addition, it is less susceptible to variations in capacitance values.

  In addition, the control circuit can compensate the TFT off-leakage due to external light by resetting the threshold value of the driving TFT a plurality of times in one frame period, and can simultaneously change the ratio of the display period. The increase in current of the driving TFT can be canceled.

  Further, since the control terminal voltage of the driving transistor can be reset at an arbitrary timing, the display period of each pixel can be limited.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

“Embodiment 1”
FIG. 1 is an overall configuration diagram of an organic EL display according to this embodiment. Reference numeral 101 denotes an active matrix display array in which organic EL elements and TFTs are arranged in pixels arranged in a matrix, 102 denotes a data driver, 103 denotes a gate driver (selection driver), and 104 denotes a precharge circuit.

  107 is a data line for supplying the data potential from the data driver 102 or the precharge potential from the precharge circuit 104 to the pixel, 108 is a gate line (selection line) for supplying a gate selection potential from the gate driver, 109, 110 Are a first reset line and a second reset line for supplying a reset potential from the gate driver, respectively.

  For example, when a low-temperature polysilicon process is applied, these circuits can be formed on a glass substrate, and the display device 105 can be formed.

  A control circuit 106 supplies an analog video signal and a control signal to the data driver 102 via the data control bus 112, and supplies a control signal to the gate driver 103 via the gate control bus 113.

  Reference numeral 115 denotes a current measurement circuit that detects the amount of current flowing through the active matrix display array 101 that varies depending on the intensity of light emission luminance, and transmits the detected amount to the control circuit 106 via the signal line 116. The current measuring circuit 115 measures the total current flowing through the active matrix display array 101. Even if an ammeter is arranged between the active matrix display array 101 and the power source, the current measuring circuit 115 An ammeter may be arranged between the ground.

  The operation of such an organic EL display will be briefly described. The data driver 102 selects one data line 107 in one horizontal period and supplies a data potential in the second half of the one horizontal period. On the other hand, the precharge circuit 104 selects the same data line 107 as the data driver 102 and supplies a preset potential in the first half of one horizontal period.

  The gate driver 103 sequentially selects one gate line 108 every horizontal period and supplies a reset signal to the corresponding first reset line 109 and second reset line 110. As a result, the data write operation after the reset operation is performed for the pixel circuits in the corresponding row.

  In this embodiment, it is possible to set a row for performing only a reset, not a row for performing the data writing described above. In other words, the gate lines 108 in other rows can be selected only when the first half of the preset potential is supplied at the same time as the above-described rows. Therefore, by selecting such another row, only the pixel circuit in the row can be reset. Therefore, the display period can be arbitrarily set by setting the period after the above-described data writing until the resetting. Details of the operation will be described later.

  The configuration of the pixel circuit of the present invention arranged in a matrix in the active matrix display array 101 will be described with reference to FIG.

  201 is an organic EL element, 202 is a driving TFT that drives the organic EL element 201, 203 is a reset TFT that short-circuits the gate and drain of the driving TFT 202, and becomes a diode, and 204 is a drive control TFT that turns off the current flowing through the organic EL 201. is there.

  Reference numeral 205 denotes a selection TFT for controlling the supply of the data potential from the data line 107 into the pixel, 206 denotes a storage capacitor for holding the data potential of the data line 107, and 207 denotes a reset capacitance for holding the reset potential.

  Reference numeral 211 denotes a power supply line for supplying a current to the organic EL element 201, and 212 denotes a fixed potential line for fixing one terminal potential of the storage capacitor.

  The source terminal of the drive TFT 202 is connected to the power supply line 211, the drain terminal is connected to the source terminal of the drive control TFT 204 and the source terminal of the reset TFT 203, and the gate terminal is connected to one terminal of the reset capacitor 207 and the drain terminal of the reset TFT 203.

  The gate terminal of the reset TFT 203 is connected to the first reset line 109, the gate terminal of the drive control TFT 204 is connected to the second reset line 110, and the drain terminal of the drive control TFT 204 is connected to the anode of the organic EL element 201.

  The selection TFT 205 has a gate terminal connected to the gate line 108, a drain terminal connected to the data line 107, and a source terminal connected to one terminal of the holding capacitor 206 and one terminal of the reset capacitor 207.

  Note that the selection TFT 205, the drive TFT 202, the reset TFT 203, and the drive control TFT 204 are all p-channel TFTs. These TFTs 205, 203, and 204 may be n-channel.

  In such a pixel circuit, first, the gate line 108 and the first reset line 109 are set to the L level, and the second reset line 110 is shifted from the L level to the H level. As a result, the selection TFT 205 is turned on, the reset TFT 203 is turned on, and the drive control TFT 204 is shifted from on to off. Further, the voltage of the data line 107 is set to the precharge potential. Accordingly, the drive TFT 202 is diode-connected, and after flowing from the power supply line 211 to the organic EL 201 via the current drive TFT 202 and the drive control TFT 204, the drive control TFT 204 is turned off. When the reset TFT 203 is turned on and the drive TFT 202 is diode-connected, the gate voltage of the drive TFT 202 is set to a voltage lower than the power supply line 211 by the threshold voltage of the drive TFT 202. On the other hand, the other end of the reset capacitor 207 is set to a precharge potential, and the voltage of the difference between these is charged to the reset capacitor 207. Note that the storage capacitor 206 is charged with a difference between the fixed potential of the fixed potential line 212 and the precharge potential.

  Next, the reset lines 109 and 110 are set to the H level, the reset TFT 203 and the drive control TFT 204 are turned off, and then the data potential is supplied to the data line 107. As a result, the potential on the gate TFT 205 side of the reset capacitor 207 is set to the data potential, the storage capacitor 206 is charged with a voltage that is the difference between the data potential and the fixed potential, and this voltage is held by the storage capacitor 206. On the other hand, the gate voltage of the driving TFT 202 is shifted by the difference between the precharge potential and the data potential. For example, assuming that the gate voltage is Vg, the precharge voltage is Vpr, the data voltage is VD, the voltage of the power supply line 211 is VDD, and the threshold voltage of the driving TFT 24 is Vth, Vg = Vth− (Vpr−VD).

  In this way, since the gate voltage of the driving TFT 202 can be set to a voltage corresponding to the threshold voltage and data potential of the driving TFT 202, the second reset line is set to L level, the drive control transistor 204 is turned on, and 1 horizontal With the end of the period, the gate line 108 is set to the H level, and the gate TFT 205 is turned off. As a result, the drive TFT 202 is driven by the gate voltage set as described above, the drive current is supplied to the organic EL 201, and the organic EL 201 emits light by the drive current that compensates the threshold voltage of the drive TFT 202.

  The configuration of the data driver 102 and the precharge circuit 104 will be described with reference to FIG.

  Reference numeral 301 is a shift register, 302 is a video switch, 311 is a video signal line, and the data driver 102 in FIG.

  The shift register 301 sequentially shifts input pulses (for example, one H level) from the shift registers 1 to n in synchronization with a predetermined clock. A pulse obtained by shifting an input pulse to the shift registers 1 to n is output to the output terminal Hi (i = 1 to n), and the video switch 302 is controlled (sequentially turned on) by this pulse to correspond to the corresponding video signal. Output to the data line 107 and sample hold.

  The precharge circuit 104 includes a precharge switch 303, a precharge control line 312, and a precharge line 313. The precharge circuit 104 controls the precharge control line 312 to supply the precharge line 313. The charge potential can be charged to the data line 107 in one line at a time.

  That is, the input pulse is sequentially shifted to the shift registers 1 to n in one horizontal period, and the video signals from the RGB three video signal lines are sequentially supplied to the corresponding data lines 107 in the second half of the one horizontal line. In this example, the pixels are R (red), G (green), and B (blue) one column at a time, and data is written in parallel for the pixels in these columns. This data writing is performed in the latter half of one horizontal period. On the other hand, a precharge potential is written into these data lines 107 in the first half of the horizontal period. Therefore, the data potential is supplied to the pixels on the selected horizontal line after the precharge potential is supplied. Only the writing (resetting) of the precharge potential is performed for other horizontal lines, which will be described later.

  The configuration of the gate driver 103 will be described with reference to FIG.

  401 is a shift register, 402 is a gate enable circuit, 403 is a first reset enable circuit, 404 is a second reset enable circuit, 405 is a gate buffer, 406 is a first reset buffer, and 407 is a second reset buffer.

  E1 and E2 are odd-numbered and even-numbered gate enable control lines, respectively. R1 and R2 are a first reset control line and a second reset control line, respectively.

  The odd line gate enable circuits are connected to the gate enable control line E1, and the even line gate enable circuits are connected to the gate enable control line E2. The first reset enable circuits for all lines are connected to the first reset control line R1, and the second reset enable circuits for all lines are connected to the second reset control line R2.

  The enable circuits 402, 403, and 404 for each line are connected to each shift register output Vi (i = 0 to n), and the shift register output Vi and E1, E2, R1, and R2, respectively, 2 Control the reset line.

  The enable circuits 402, 403, and 404 are AND gates, and output H level only when both input signals are H level. Therefore, E1 is output from the enable circuit 402 to which the odd-numbered Vi is input when the corresponding Vi is at the H level, which is inverted by the gate buffer 405 and output to the gate line. Therefore, the selection TFT 205 of the pixel circuit is turned on while the gate enable control signal E1 is at the H level. On the other hand, the enable circuit 403 outputs R1 when Vi is at the H level, which is inverted by the first reset buffer 406 and supplied to the first reset line 109. Therefore, during the period when the first reset control signal R1 is at the H level, the first reset line 109 is at the L level, and the reset TFT 203 is turned on. Further, the enable circuit 404 outputs R2 when Vi is at the H level, and this is supplied from the second reset buffer 407 to the second reset line 110 with the same polarity. Therefore, when the corresponding Vi is at the H level, the first reset line 109 is at the L level during the period when the second reset control signal R2 is at the H level, and the drive control TFT 203 is turned on. Further, during the period in which the corresponding Vi is at the L level, the second reset line 110 is at the L level, and the drive control TFT 204 is turned on.

  The driving method of this embodiment will be described with reference to FIG.

  FIG. 5 is a diagram showing the display state of the frame period with time on the horizontal axis and lines on the vertical axis. As described above, in each line (horizontal scanning line), one frame period is divided into a display period for displaying video data and a reset period for resetting the driving TFT. That is, a fixed period of reset period is assigned after a fixed period of display period.

  First, video data is sequentially written from the first line, and for the line for which writing has been completed, the display period starts. Then, before completing the writing of the video data of all the lines after a predetermined period, reset the pixels of the horizontal line that has already passed the current according to the video data, and end the display period to the reset period. enter. In this embodiment, the resetting of the pixel, that is, the resetting of the driving TFT of the pixel is sequentially performed a plurality of times.

  In FIG. 5, paying attention to the section X-X ', video data is written in the k0th line, and the k1st line and the k2th line are reset.

  For example, consider a case where there are 480 horizontal lines in the vertical scanning direction, k0 is the 11th line, and the display period and the reset period are 50% each. In this case, Vk0 = V11 becomes H level in the eleventh horizontal scanning period. As a result, reset and data writing are performed on the pixels of the eleventh horizontal line, and the display period starts from the next twelfth horizontal scanning period. The display period is a 240 horizontal scanning period, and Vk0 = V11 becomes H level in the 252nd horizontal scanning period. In the 252nd horizontal scanning period, resetting and data writing are performed on the 252nd line, but only resetting is performed on the pixels on the 11th line. Therefore, the display by the pixels on the eleventh line is terminated by this reset, and enters the reset period. Thereafter, in any even horizontal scanning period (k1 line) between the 254th horizontal scanning period and the 10th horizontal scanning period of the next frame, the reset is performed once during the reset period by setting V11 to the H level. . It is also preferable to further increase the number of resets during this reset period.

  The control process shown in FIG. 5 of the data driver 102, the gate driver 103, and the precharge circuit 104 will be described in detail with reference to FIGS.

  In FIG. 6, 601 is an input pulse input to the shift register of the gate driver 103, 602 is a clock for shifting the input pulse 601, 603 is a shift pulse of the shift register output V1, and these pulses are sequentially shifted in the vertical scanning direction. And output to Vi. Note that the cycle of the clock 602 corresponds to the horizontal scanning period.

  Reference numeral 604 denotes a shift register output pulse of the k0th line, 605 denotes a shift register output pulse of the k1th line, 606 denotes a shift register output pulse of the k2th line, and they are all active in the X-X ′ section. As described above, in this example, both the output pulses 604, 605, and 606 are the start pulse of the display period in which the first pulse in the figure performs resetting and data writing, and the second pulse is the reset period in which only resetting is performed. The start pulse and the third are pulses for resetting again during the reset period.

  In FIG. 7, reference numeral 701 denotes output pulses of the shift register outputs Vk0, Vk1, and Vk2 in the section XX ′, reference numeral 702 denotes output pulses of the shift register outputs Vk0 + 1, Vk1 + 1, and Vk2 + 1 in the same section, and reference numeral 703 denotes an odd-numbered enable control line E1. , 704 is an even-numbered enable control line E2, 705 is a first reset control line R1, 706 is a second reset control line R2, 707 is a precharge control line, and 708 is a data potential of the data line 107.

  FIG. 8 is an operation table of the pixel circuit of FIG. 2, and shows the operation of the pixel according to each pulse level when the data driver 102, the gate driver 103, and the precharge circuit 104 are configured as shown in this embodiment. Yes.

  Based on the operation table of FIG. 8, the operation of the pixel in FIG. 7 will be described.

  In FIG. 7, if the input pulse 601 is input so that k0 is an odd number, k1, and k2 are even numbers, E1 is H level in the first half of the XX ′ section, R1 , R2 is at the H level and the precharge is enabled, the k0 line is the reset period from FIG. 8 (1). Further, since E2 shifts from the L level to the H level, the k1 and k2 lines are also the reset period from FIG. 8 (4).

  That is, in any of the lines k0, k1, and k2, Vi is at the H level, the gate line 108 and the first reset line 109 shift from the L level, and the second reset line 110 shifts from the L level to the H level. The gate potential of the driving TFT 202 is reset to the threshold voltage Vth.

  In the YX ′ section, which is the latter half of the XX ′ section, E1 and R2 are at the H level, R1 is at the L level, and precharge is disabled. Therefore, data writing is performed only for k0 from FIG. 8 (2). . That is, at k0, since E1 is also at the H level of Y-X ', the selection TFT 205 of the k0 line is on, and the data potential of the data line 107 is charged in the storage capacitor 206. On the other hand, in the k1 and k2 lines, since E2 is L level at Y-X ′, the corresponding selection TFT 205 is turned off, and the data potential of the data line 107 is not charged in the storage capacitor 206.

  Thus, in the section X-X ', the k0 line writes data after reset, and the k1 and k2 lines are only reset.

  When entering the section X′-X ″, from FIG. 8 (3), since the data is written in the k0 line as described above, the display of the written data is started. On the other hand, in the k1 and k2 lines, Since it is in the reset state, the reset period is continued.

  In the X′-X ″ section, the k0 + 1 line of the even line and the k1 + 1 and k2 + 1 of the odd line are the first half X′-Y ′ and are in the states shown in FIGS. 8 (4) and 8 (1), respectively. In the second half Y′−X ″, data is written only in the k0 + 1 line.

  By sequentially driving in this manner, a display period and a reset period can be provided in the frame period as shown in FIG.

  In the present embodiment, the reset is performed three times in one frame period in each line. However, when the reset period of one time cannot be sufficiently secured, it is desirable that the reset potential is further stabilized to stabilize the reset potential.

  Further, by controlling the pulse interval of the input pulse 601 (interval between the pulse for performing reset and data writing and the first pulse for performing only reset), the ratio between the display period and the reset period can be made variable. is there. FIG. 13 shows the relationship between the data voltage Vd and the luminance when the reset period is changed to 25%, 50%, and 75%. When the ratio of the reset period is increased, the display period is shortened, so that the same gradation characteristics can be maintained and the whole can be darkened.

  By using these functions together with the current measurement circuit 115, for example, it is possible to compensate for the leakage current of the TFT by external light as shown in FIG.

  In the pixel circuit of FIG. 2, the influence of the leakage current is due to the leakage of the selection TFT 204 and the change of the current characteristics of the driving TFT 202. The former causes the reset charge held in the holding capacitor 206 to flow out, so that the gradation voltage is changed with the passage of time. Further, since the latter acts so that the current of the driving TFT 204 flows more, the black level of the video is lifted and the display quality cannot be maintained. That is, the amount of current at the black level becomes large, and a certain level of luminance occurs.

  FIG. 14 is a diagram showing a configuration of a leakage current correction system when the display of the present embodiment is used under illumination. Reference numeral 1401 denotes a current value prediction circuit, 1402 denotes a comparison circuit, and 1403 denotes a reset period and reset count control circuit.

  In this system, since all current values flowing to the display array can be predicted from input data, the current value prediction circuit 1401 first predicts the current value. Then, the predicted current value and the current value from the current measurement circuit 115 are compared by the comparison circuit 1402, and the reset period and the number of resets are changed according to the difference between the predicted value and the detected current value.

  By increasing the number of resets by the control circuit 1403, the reset charge can be supplemented by reset charging many times even if leakage in the reset TFT 203 increases. Further, by increasing the reset period, the increase in current of the driving TFT 202 can be canceled.

  Actually, when the current difference is detected in the comparison circuit 1402, if it is immediately reflected in the display, it becomes flicker. Therefore, the current difference is controlled to have a hysteresis and reflected in the Schmitt trigger type. It is desirable.

  Further, these adjustment functions for the reset period and the number of resets may not be used as leakage current correction. For example, if the reset period is lengthened and the display period is shortened, light emission characteristics such as those of a cathode ray tube are reproduced in a pseudo manner, so that the moving image visibility can be improved. Therefore, it can be applied to a moving image application such as a TV by increasing the power supply voltage and increasing the current value corresponding to the shortened display period.

“Embodiment 2”
FIG. 9 shows an internal configuration of the data driver 102 according to the second embodiment. FIG. 9 shows an example devised to realize a higher-definition display. The video signal line 311 is divided into a first video signal line (R1, G1, B1) and a second video signal line (R2, G2). , B2) are extended to two video signal lines. Then, three (a total of six) lines of the two video signal lines are connected to the corresponding data lines 107 by signals Hi (i = 1 to n) from one shift register 1 to n. Accordingly, a video signal of twice as many pixels can be sampled and held by one pulse of the shift register, so that a panel with higher resolution can be driven.

  However, if there are two or more video signal lines 311, two or more video circuits for generating an analog video signal are required, and display variations occur in adjacent pixels due to variations in the gains of both. .

  FIG. 10 shows a circuit provided to suppress the display variation. Reference numeral 1001 denotes a first video circuit of two video circuits, and reference numeral 1002 denotes a second video circuit. Reference numeral 1003 denotes a first video switch connected to the first video signal line of the two video signal lines 311, and reference numeral 1004 denotes a second video switch connected to the second video signal line.

  The output of the video circuit 1001 is connected to the terminal 1 of the first and second video switches 1003 and 1004, and the output of the video circuit 1002 is connected to the terminal 2 of the first and second video switches 1003 and 1004. Therefore, in the first and second video switches 1003 and 1004, the first video signal and the second video signal can be alternately selected, and different video signals can be selected in both.

  FIG. 11 is a switching timing chart of the video switches 1003 and 1004. 1101 is an input pulse to be input to the shift register 401 of the gate driver 103, 1102 is a clock for shifting the input pulse 1101, 1103 is an input pulse to be input to the shift register 301 of the data driver 102, 1104 is a switch for switching the video switches 1103 and 1104 Signal 1105 is a video signal on the first video signal line, and 1106 is a video signal on the second video signal line.

  Switching is performed alternately at odd-numbered lines and even-numbered lines, and between odd-numbered frames and even-numbered frames at the timing of the switching signal 1104. In this way, since the signals of the video circuits 1001 and 1002 are alternately written to each pixel for each frame, the display variation is smoothed.

  In addition, flicker can be suppressed by switching line by line, and display variations can be made inconspicuous even if the output characteristics of the video circuits 1001 and 1002 are different. Note that this circuit may be incorporated in the control circuit 106 or formed on a glass substrate.

“Embodiment 3”
FIG. 15 shows a conventionally known pixel circuit, which includes a selection TFT 205, two TFTs such as a driving TFT 202, and one storage capacitor 206 in addition to the organic EL element 201. The source of the selection TFT 205 is connected to the data line 107, the drain is connected to the gate of the driving TFT 202, and the gate is connected to the gate line 108. Further, the gate of the driving TFT 202 is connected to the non-fixed potential end of the storage capacitor 206 whose other end is connected to the fixed potential line 212. The source of the driving TFT 202 is connected to the power supply line 211, and the drain is connected to the anode of the organic EL element 201. The cathode of the organic EL element 201 is connected to a cathode power source.

  Also in this circuit, as in the above-described embodiment, the precharge voltage is supplied to the data line 107 in the first half of one horizontal period, and data is written only in the horizontal scanning line in which writing is performed in the second half.

  In this embodiment, since there is no reset line, the enable circuits 403 and 404 in the circuit of FIG. 4 are unnecessary, and only the enable circuit 402 is provided. Also in FIG. 7, R1 and R2 are unnecessary.

  Even when such a circuit is used, the reset time can be varied as in the above-described embodiment.

  In the reset operation of the present invention, the pixel circuit is not limited to the pixel circuit of FIGS. 2 and 15, but various pixel circuits such as the pixel circuit shown in FIG. The present invention can also be applied to a pixel that sandwiches.

  Further, the configuration of the gate driver is not limited to FIG. For example, as shown in FIG. 16, three or more enable control lines may be used. That is, in the configuration of FIG. 16 using three enable control lines, the enable circuit 402 is connected to the same enable control line of any one of the three enable control lines E1, E2, E3 every three lines, and one of them is connected. It may be selected for video writing, and at least the remaining one may be selected for reset writing. Such a gate driver also achieves the same reset operation as described above.

1 is an overall configuration diagram of Embodiment 1. FIG. It is a figure which shows the structure of a pixel circuit. 2 is a diagram illustrating a data driver and a precharge circuit according to the first embodiment. FIG. It is a block diagram of a gate driver. It is a drive sequence explanatory drawing. It is a panel drive timing chart. It is a panel drive timing chart enlarged view. It is an operation | movement table which shows operation | movement of the pixel circuit of each row. It is a figure which shows the data driver and precharge circuit of Embodiment 2. It is a figure which shows the structure of a display variation smoothing circuit. It is a drive timing chart of a display variation smoothing circuit. It is a figure which shows the pixel circuit of a prior art example. It is a figure which shows the relationship between a reset period and a brightness | luminance. It is a figure which shows the structure of the control based on an electric current measured value. It is a figure which shows the other structural example of a pixel circuit. It is a figure which shows the other structural example of a gate driver.

Explanation of symbols

  101 active matrix display array, 102 data driver, 103 gate driver, 104 precharge circuit, 105 display device, 106 control circuit, 107 data line, 108 gate line, 109 first reset line, 110 second reset line, 112 data Control bus, 113 gate control bus, 115 current measurement circuit, 116 signal line, 201 organic EL element, 204 drive control TFT, 206 holding capacitor, 207 reset capacitor, 211 power supply line, 212 fixed potential line, 301 shift register, 302 video Switch, 310 data line, 311 video signal line, 312 precharge control line, 313 precharge line, 401 shift register, 402, 403, 404 rice Bull circuit, 405 a gate buffer 406 reset buffer, 1001, 1002 video circuit, 1003 and 1004 video switch, 1401 the current value predicting circuit, 1402 comparing circuit, 1403 a control circuit.

Claims (10)

An active matrix display array in which a pixel-type light-emitting element driven by current and a plurality of thin-film transistors that control the diode-type light-emitting element are used as one pixel circuit, and the pixel circuits are arranged in a matrix;
A data line provided corresponding to each column of the matrix and supplying a data signal to the pixel circuit of the corresponding column;
A data driver for controlling the supply of the data signal to the data line;
A precharge circuit for precharging the data line;
A selection line provided corresponding to each row of the matrix and supplying a selection signal to the pixel circuit of the corresponding row;
A selection driver for supplying a selection signal to the selection line;
A control circuit for controlling the data driver, precharge circuit, and selection driver;
In a display device having
The pixel circuit includes:
A holding capacitor with a fixed potential at one end;
A selection transistor having one non-control terminal connected to the non-fixed potential terminal of the storage capacitor, the other non-control terminal connected to the data line, and a control terminal connected to the selection line;
A drive transistor for controlling a drive current to the diode-type light emitting element;
A reset transistor that diode-connects the drive transistor;
A drive control transistor connected in series to the drive transistor for controlling on / off of a drive current of the diode-type light emitting element;
A reset capacitor having one end connected to the control terminal of the drive transistor and the other end connected to a non-control terminal to which the holding capacitor of the selection transistor is connected;
Have
The display driver according to claim 1, wherein the selection driver controls the selection lines separately for odd lines and even lines. The display device according to claim 1,
The display device, wherein the active matrix display array, the data driver, the precharge circuit, and the selection driver are formed on one glass substrate. The display device according to claim 1,
The selection period of the selection line is divided into two, and in the first period, the line for writing the video and one or more lines of odd or odd to which the line for writing the video does not belong are selected for reset, and the second period The display device is characterized in that reset selection is performed a plurality of times in one frame period by selecting video writing only for the video writing line. The display device according to claim 1,
A display device characterized in that a ratio of a display period and a reset period can be changed in one frame period. The display device according to claim 1,
further,
A current measurement circuit for measuring a total current value flowing through the active matrix display array;
A display device, wherein a ratio between the display period and the reset period is changed in accordance with a current value of the current measurement circuit. The display device according to claim 5,
Further, the display device is characterized in that the number of reset selections is changed according to the current value of the current measuring circuit. The display device according to claim 1,
The data driver has two or more signal buses for each of RGB,
The control circuit switches two or more video circuits for supplying video signals to each of the two or more signal buses, and switching means for switching to which signal bus the video signal supplied from the video circuit is supplied. Have
The display device characterized in that the connection between the signal bus and the video circuit is switched for each line by the switching means, and the connection is switched for each frame. Current-driven diode-type light-emitting element, drive transistor that controls supply of drive current to the diode-type light-emitting element, storage capacitor that holds the voltage of the control terminal of the drive transistor, and data signal to the storage capacitor An active matrix display array in which pixel circuits including a selection transistor for controlling the supply of the pixel transistors are arranged in a matrix,
A data line provided corresponding to each column of the matrix and supplying a data signal or a reset signal to the pixel circuit of the corresponding column;
A selection line which is provided corresponding to each row of the matrix and supplies a selection signal for controlling a selection transistor in the pixel circuit of the corresponding row;
A selection driver for supplying the selection signal to the selection line;
In a display device having
A selection signal for one horizontal period is simultaneously output from the selection driver to a plurality of selection lines,
For a pixel circuit to which one of a plurality of selection signals output by the selection driver is supplied, a data signal is supplied after resetting the control terminal voltage of the driving transistor when the selection signal is output,
A display device in which the control terminal voltage of the driving transistor is only reset for other pixel circuits. The display device according to claim 8, wherein
In the data line, one horizontal period is divided into two, a reset signal is supplied in the first half, a data signal is supplied in the second half,
A display device, characterized in that one selection line is supplied with both first and second half selection signals and the other selection line is supplied with only the first half selection signal. One of the controlled ends is connected to the data line, the other is connected to one end of the reset capacitor, and a selection transistor that controls connection of the data line and the reset capacitor according to a selection signal of the selection line connected to the control end;
A holding capacitor having one end connected to the potential fixing line and the other end connected to the selection transistor reset capacitor side end;
A driving transistor having a control terminal connected to the other end of the reset capacitor and one of the controlled terminals connected to a power supply line;
A reset transistor that controls whether or not the drive transistor is diode-connected;
A drive control transistor for turning on and off a current from a drive transistor in which one of the controlled ends is connected to the other controlled end of the drive transistor;
A diode-type light-emitting element that is connected to the other controlled end of the drive control transistor and emits light by a current supplied via the drive transistor and the drive control transistor;
Have
With the data line set to the reference voltage, the selection transistor and the reset transistor are turned on, the drive control transistor is turned off, the control terminal of the drive transistor is set to the threshold voltage of the drive transistor,
After that, the reset transistor is turned off and the data voltage is set to the data line to shift the control terminal voltage of the drive transistor according to the data voltage, and then the drive control transistor is turned on to shift according to the data voltage. A pixel circuit, wherein a diode-type light emitting element is caused to emit light by a current flowing in a driving transistor by the controlled control voltage.

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