JP2005250850A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device achieving a reduction in power consumption by allowing not to supply clock to or to not operate peripheral function modules avoid the need to operation without intervention of a program. <P>SOLUTION: The semiconductor integrated circuit device is provided with an address determination circuit 2 constantly monitoring an address signal outputted from a CPU and specifies a peripheral function module accessed by the address determination circuit 2. Based on a control signal 8, a clock control circuit 4 supplies no clock to the peripheral function modules except the accessed peripheral function module. Thus, power consumption on a clock path is reduced. Furthermore, The control signal 8 from the address determination circuit 2 is inputted to each of the peripheral function modules 6a-c to stop the circuit operation, including an address decoding for the peripheral function modules except the accessed peripheral function module. Thus, the power consumption here is also reduced. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit device including a plurality of peripheral function modules each having a circuit for realizing a specific function.

  In a conventional semiconductor integrated circuit device such as a microcomputer, when it is composed of a plurality of peripheral function modules such as a serial communication function and an AD conversion function, the clock is supplied to all the peripheral function modules in one place. I was going. For this reason, the clock is always supplied to all the peripheral function modules regardless of whether or not each peripheral function module is operating.

  In some semiconductor integrated circuit devices, in order to reduce power consumption, a control register for controlling whether or not to supply a clock is provided on one chip, and the setting of this register is changed by a program. When power consumption is desired, supply of clocks to all functional modules of the semiconductor integrated circuit device is stopped.

Further, a register for controlling use / non-use of the function module is provided in each function module, and the function module that is not used has taken measures such as stopping the operation by setting this register by a program.
JP-A-10-161766

  In a semiconductor integrated circuit device in which many peripheral function modules are integrated, it is necessary to supply a clock to every corner of the semiconductor integrated circuit device, so that the clock wiring length inside the semiconductor integrated circuit device becomes long and needs to be driven. There is a problem that the number of certain transistors increases and the load increases. For this reason, it has become necessary to configure the clock supply circuit using a transistor with very high driving capability and high power consumption. In addition, there is a problem of a new increase in power consumption due to insertion of a buffer for adjusting a delay time difference in the clock supply path to each module.

  For the above reasons, the power consumption of the semiconductor integrated circuit device has been increased. In the conventional semiconductor integrated circuit device, when a clock is always supplied from one clock supply circuit to all peripheral function modules, the clock is supplied to peripheral function modules that do not need to be operated. Wasteful power was consumed.

  Further, in the conventional semiconductor integrated circuit device, when the use / non-use of the peripheral function module is controlled by the register, it is necessary for the user to create software for explicitly setting these registers when creating the program. .

  The present invention solves such a conventional problem, and aims to reduce power consumption by preventing a peripheral function module that does not need to operate from being supplied with a clock or from being operated without the intervention of a program. An object of the present invention is to provide a semiconductor integrated circuit device that can be used.

  A first semiconductor integrated circuit device according to the present invention includes a CPU, a plurality of peripheral function modules each having a circuit that realizes a specific function, a clock supply circuit that outputs a clock supplied to the peripheral function module, and a CPU. An address determination circuit for inputting an output address signal and determining whether each of the plurality of peripheral function modules is a peripheral function module corresponding to the address signal, and a clock from the clock supply circuit, and an address determination circuit And a clock control circuit that outputs a clock to the peripheral function module corresponding to the address signal and does not output a clock to the peripheral function module not corresponding to the address signal.

  According to this configuration, the clock is supplied to the peripheral function module corresponding to the address signal, that is, the accessed peripheral function module, but the clock is not supplied to the peripheral function module that is not accessed. Therefore, it is possible to reduce power consumption on the clock path leading to the peripheral function module that is not accessed from the clock control circuit. In order to increase this effect, it is preferable to provide the clock control circuit integrally with the clock supply circuit or in the vicinity of the clock supply circuit.

  A second semiconductor integrated circuit device according to the present invention includes a CPU, a plurality of peripheral function modules each having a circuit that implements a specific function, a clock supply circuit that outputs a clock supplied to the peripheral function module, and a CPU. An address determination circuit that inputs an output address signal and determines whether each of the plurality of peripheral function modules is a peripheral function module corresponding to the address signal. Based on the determination result, the peripheral function module corresponding to the address signal performs control to enable the operation of the circuit in the peripheral function module, and the peripheral function module not corresponding to the address signal is input to the peripheral function. The operation of the circuit in the module is made impossible.

  According to this configuration, the operation of internal circuits such as address decoding in the peripheral function module in which access has occurred is started, but the internal circuits such as address decoding in peripheral function modules in which access has not occurred is stopped. Therefore, power consumption can be reduced.

  A third semiconductor integrated circuit device according to the present invention includes a CPU, a plurality of peripheral function modules each having a circuit that realizes a specific function, a clock supply circuit that outputs a clock supplied to the peripheral function module, and a CPU. An address determination circuit for inputting an output address signal and determining whether each of the plurality of peripheral function modules is a peripheral function module corresponding to the address signal, and a clock from the clock supply circuit, and an address determination circuit A clock control circuit that outputs a clock to the peripheral function module corresponding to the address signal and does not output a clock to the peripheral function module not corresponding to the address signal based on the determination result of the plurality of peripheral functions. The module inputs the determination result of the address determination circuit, and based on the determination result, the module Peripheral function module corresponding to the source signal performs control to enable operation of the circuit in the peripheral function module, and peripheral function module not corresponding to the address signal seems to be unable to operate the circuit in the peripheral function module. I have to.

  According to this configuration, the effects of both the first and second semiconductor integrated circuit devices can be obtained. That is, the clock supply is started only to the peripheral function module in which access has occurred, and the operation of internal circuits such as address decoding in the peripheral function module is started. Is not supplied, and internal circuits such as address decoding in the peripheral function module are stopped and power consumption can be greatly reduced.

  According to the present invention, a peripheral function module to be accessed can be specified by providing an address determination circuit without intervention of a program created by a user, and therefore, a clock is supplied to peripheral function modules other than the accessed peripheral function module. By avoiding this, it is possible to reduce the power consumed on the clock path from the clock supply circuit to each peripheral function module.

  Further, by stopping the circuit operation such as address decoding of peripheral function modules other than the accessed peripheral function module, the power consumed here can be reduced.

  As described above, it is possible to realize low power consumption while reducing the burden of creating a program for a user who desires low power consumption.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a basic configuration of a semiconductor integrated circuit device according to an embodiment of the present invention.

  The semiconductor integrated circuit device includes a CPU 1, a plurality of peripheral function modules 6 a to 6 c that realize various peripheral functions such as a timer function and a serial interface function, a clock supply circuit 3, an address determination circuit 2, and a clock control circuit 4. Etc. Although not shown, a clock (clock source signal 7) is directly supplied to the CPU 1 from the clock supply circuit 3.

  An address signal is input from the CPU 1 to the address determination circuit 2 and the peripheral function modules 6a to 6c. Based on this address signal, the CPU 1 specifies an operation control register (not shown) in each peripheral function module for causing each peripheral function module 6a-c to operate its desired peripheral function. The address determination circuit 2 constantly monitors access from the CPU 1 to each peripheral function module by monitoring an address signal. The address determination circuit 2 stores addresses of the peripheral function modules 6a to 6c in advance, and based on the addresses, determines which peripheral function module the address signal output from the CPU 1 is to access. Then, the determination result is output as a control signal 8 (8a to c). For example, in the case of an address signal for accessing the peripheral function module 6a, the control signal 8a is set in an active state (for example, high level), and the control signals 8b and 8c are set in an inactive state (for example, low level). c and output to the clock control circuit 4.

  One configuration example of the clock control circuit 4 is shown in FIG. In the clock control circuit 4, the clock source signal 7 is input from the clock supply circuit, and the clock (clock source signal 7) is supplied only to the peripheral function module accessed based on the control signal 8 (8a to 8c).

  FIG. 3 is a flowchart showing the operation of the semiconductor integrated circuit device. First, immediately after the resetting of the microcontroller, the state after the reset start of the flowchart of FIG. 3 is entered, and as an initial state, each module is not used, and the operation is stopped (S1). The supply of the clock is stopped. Therefore, all the control signals 8 (8a to 8c) output from the address determination circuit 2 are set in an inactive state. As a result, the clock source signal 7 output from the clock supply circuit 3 stops at the clock control circuit 4. As a result, power consumption in the wiring on the clock path from the clock control circuit 4 to the peripheral function modules 6a to 6c and the delay control buffers 5a to 5e is reduced. Further, the control signals 8a to 8c are also input to the peripheral function modules 6a to 6c, and the address decoding circuit and the like in each peripheral function module are stopped and the power consumption is reduced here.

  Next, during the program execution (S2) in the flowchart of FIG. 3, the execution of the user program is started, and the peripheral function module in the peripheral function module is operated so as to perform a desired operation with respect to the peripheral function module desired to be used in the user program. Accesses the operation control register. At this time, in order to access the operation control register of the peripheral function module from the CPU 1, the address of the operation control register of the peripheral function module is output as the address signal. The address determination circuit 2 constantly monitors this address value, automatically determines that the peripheral function module is used, and sends a control signal 8 to the clock control circuit 4 so as to start clock supply to the peripheral function module. Send (S3).

  The clock control circuit 4 receives this control signal 8 and starts supplying the clock to the peripheral function module. On the other hand, the clock supply to the peripheral function module that has not been accessed remains stopped. The control signal 8 for instructing the start of clock supply is also input to the peripheral function module, and the peripheral function module changes the state of the circuit such as address decoding in the module from the stopped state to the operating state. As a result, the address decoding circuit in the peripheral function module starts address decoding correctly, and it becomes possible to make a desired setting to the operation control register in the module (S4).

  As described above, the clock is supplied only to the peripheral function module by accessing the specific peripheral function module by the user program, and the address decoding circuit or the like in the peripheral function module starts operation.

  According to the present embodiment, since the peripheral function module to be accessed can be specified by providing the address determination circuit 2 without the intervention of a program created by the user, the control signal 8 that is the determination result of the address determination circuit 2 is displayed. On the basis of the above, by preventing the clock control circuit 4 from supplying a clock to peripheral function modules other than the peripheral function module to be accessed, conventionally, on the clock path from the clock supply circuit to each peripheral function module, Electric power consumed can be reduced. In order to make this effect larger, it is preferable to provide the clock control circuit 4 integrally with the clock supply circuit 3 or in the vicinity of the clock supply circuit 3.

  Further, the control signal 8 which is the determination result of the address determination circuit 2 is also input to each peripheral function module 6a to 6c, and the circuit operation such as address decoding of peripheral function modules other than the peripheral function module to be accessed is stopped. The power consumed here can also be reduced.

  The semiconductor integrated circuit device according to the present invention can realize low power consumption while reducing the burden on the user's program creation, and is useful as a semiconductor integrated circuit device including a plurality of peripheral function modules. .

1 is a block diagram of a semiconductor integrated circuit device according to an embodiment of the present invention. 1 is a configuration diagram of a clock control circuit in a semiconductor integrated circuit device according to an embodiment of the present invention. 4 is a flowchart showing an operation procedure in the semiconductor integrated circuit device according to the embodiment of the present invention.

Explanation of symbols

1 Central processing unit (CPU)
2 Address determination circuit 3 Clock supply circuit 4 Clock control circuit 5a to e Clock delay control buffer 6a to c Peripheral function module 7 Clock source signal 8 Control signal

Claims (3)

  A central processing unit (hereinafter referred to as a CPU), a plurality of peripheral function modules each having a circuit for realizing a specific function, a clock supply circuit for outputting a clock to be supplied to the peripheral function module, and an output from the CPU Input an address signal, and determine whether each of the plurality of peripheral function modules is a peripheral function module corresponding to the address signal, and input the clock from the clock supply circuit, A clock control circuit that outputs the clock to a peripheral function module corresponding to the address signal based on a determination result of the address determination circuit and does not output the clock to a peripheral function module not corresponding to the address signal; A semiconductor integrated circuit device.   CPU, a plurality of peripheral function modules each having a circuit that realizes a specific function, a clock supply circuit that outputs a clock to be supplied to the peripheral function module, an address signal output from the CPU, and the input An address determination circuit that determines whether each of the plurality of peripheral function modules is a peripheral function module corresponding to the address signal, and the plurality of peripheral function modules input a determination result of the address determination circuit, Based on the determination result, the peripheral function module corresponding to the address signal performs control to enable the operation of the circuit in the peripheral function module, and the peripheral function module not corresponding to the address signal is in the peripheral function module. A semiconductor integrated circuit device in which the operation of the circuit is impossible.   CPU, a plurality of peripheral function modules each having a circuit that realizes a specific function, a clock supply circuit that outputs a clock to be supplied to the peripheral function module, an address signal output from the CPU, and the input An address determination circuit that determines whether each of the plurality of peripheral function modules is a peripheral function module corresponding to the address signal, and a clock from the clock supply circuit, and based on a determination result of the address determination circuit A clock control circuit that outputs the clock to a peripheral function module corresponding to the address signal and does not output the clock to a peripheral function module not corresponding to the address signal, and the plurality of peripheral function modules Inputs the determination result of the address determination circuit, the determination result The peripheral function module corresponding to the address signal controls the operation of the circuit in the peripheral function module, and the peripheral function module not corresponding to the address signal operates the circuit in the peripheral function module. A semiconductor integrated circuit device made impossible.

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