JP2005168129A - Switching power supply circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a switching power supply circuit wherein production of vibration and noise can be prevented by controlling the switching operation period in the state of intermittent switching operation under light load, or voltage free from voltage dip can be supplied even when the load is abruptly changed from light load to heavy load. <P>SOLUTION: An error amplifier circuit 8 amplifies the error between an output voltage Vout inputted from an output voltage detection circuit 5 and a modulated reference voltage Vmod inputted from a reference voltage modulation circuit 7. The modulated reference voltage Vmod repeats high-voltage period TH at a first reference voltage VH and low-voltage period TL at a second reference voltage VL at intervals of Fm. When external load RR is light, control can be carried out so that switching operation is performed without fail with the timing of transition of the modulated reference voltage Vmod from the second reference voltage VL to the first reference voltage VH. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a switching power supply circuit that supplies power to a load having at least two states of a light load state and a heavy load state, and in particular, an operation cycle of an intermittent switching operation that occurs when the load is in a light load state. The present invention relates to a switching power supply circuit that can be controlled.

A switching power supply circuit disclosed in Patent Document 1 is shown in FIG. In the switching power supply circuit of FIG. 9, when the load is small and the voltage divided by the resistors R115 and R116 on the secondary side exceeds a certain value, the output of the comparator CoH102 with hysteresis becomes a low level, and the photocoupler The PC 102 turns off the output of the drive circuit 101 that drives the primary side main switching element Q102. Then, no power is supplied to the secondary side, and the voltage decreases with the discharge of the capacitor C114 that smoothes the output voltage. If the output of the comparator CoH102 is set to the high level when the voltage V100 on the secondary side falls below a certain value, the photocoupler PC102 turns on the output of the drive circuit 101 at this time, so that the main switching element The on / off operation of Q102 is resumed, and the secondary voltage rises. This is repeated to maintain intermittent oscillation (intermittent switching operation). An RCC (ringing choke converter) switching power supply circuit disclosed in Patent Document 2 is shown in FIG. In the switching power supply circuit of FIG. 10, when there is no output load, switching control of the main transistor 105 is intermittently performed at a predetermined intermittent oscillation (intermittent switching operation) frequency without depending on the primary-secondary transfer function. This is performed by the oscillation control circuit 118. Also, when a load is connected to the output of the switching power supply, the intermittent oscillation control operation of the main transistor 105 by the intermittent oscillation control circuit 118 is stopped, and the control method is switched to a stable output current and output voltage of the switching power supply. Change.
Japanese Patent Laid-Open No. 11-275857 (paragraphs 0021 to 0022, FIG. 1) Japanese Patent Laid-Open No. 2002-252973 (paragraphs 0011 to 0012, FIG. 1)

  However, in the switching power supply circuit disclosed in Patent Document 1, when the load is in a light load state, the main switching element Q102 enters an intermittent switching operation state, but this operation cycle cannot be controlled. In other words, it is difficult to design the capacity of the capacitor and the current consumption at the external load in advance so that the cycle of the intermittent switching operation becomes a predetermined cycle, and when the current consumption at the external load changes, the cycle of the intermittent switching operation Therefore, it is difficult to control the period to a predetermined value. Depending on the cycle of the intermittent switching operation, the transformer, the substrate, and the like may vibrate due to the magnetostrictive effect, but this is a problem because this vibration cannot be prevented by controlling the switching operation cycle. In particular, when the period of vibration due to the intermittent switching operation is close to the natural frequency of the transformer, the substrate, etc., there is a possibility that the vibration may vibrate with a large amplitude due to resonance. Further, when vibration occurs, noise may occur if the frequency of vibration is within the human audible range, but this noise is a problem because it cannot be prevented by controlling the switching operation cycle.

  In the switching power supply circuit disclosed in Patent Document 2, the intermittent switching control circuit 118 can set the intermittent switching operation frequency to a predetermined frequency that does not generate noise and vibration, but the circuit needs to be switched. When the load suddenly shifts from a light load state to a heavy load state, if the circuit cannot be switched in time, the output voltage may drop transiently, so-called voltage dip may occur.

  The present invention has been made to solve at least one of the problems of the prior art, and by controlling the switching operation cycle in the intermittent switching operation state when the load is light, vibration and noise are generated. It is an object of the present invention to provide a switching power supply circuit capable of preventing or supplying a voltage without a voltage dip even when the load changes suddenly from a light load state to a heavy load state.

  In order to achieve the above object, a switching power supply circuit according to claim 1 includes an error amplification circuit that amplifies an error voltage according to a reference voltage and an output voltage, and the output voltage is regulated within an allowable voltage range including the target voltage. The rated power supply circuit includes a reference voltage modulation circuit that outputs a modulation reference voltage that repeats a plurality of different reference voltages in a predetermined cycle to the error amplification circuit instead of the reference voltage.

  When the modulation reference voltage is stepped down from a high voltage to a low voltage, the output voltage is stepped down from a voltage value regulated according to the high voltage to a voltage value regulated according to the low voltage. This step-down speed is gentle when the load is light, and steep when the load is heavy, but in either case, the modulation reference voltage transitions from the low voltage to the high voltage again. The output voltage at the timing is a voltage value lower than the voltage value regulated according to the high voltage. Therefore, the switching operation is always started according to the timing at which the modulation reference voltage transitions from the low voltage to the high voltage, and the switching operation is performed at least once.

  In the case of a light load, when the modulation reference voltage is switched from a high voltage to a low voltage, the output voltage is maintained at a higher voltage than the modulation reference voltage, and the switching operation is not performed. Therefore, it is possible to localize the switching operation necessary for maintaining the output voltage within the allowable voltage range in a light load state in a period starting from the timing when the modulation reference voltage transitions from a low voltage to a high voltage. it can. Then, by controlling the modulation reference voltage switching period, the period in which the switching operation is performed can be controlled.

  A switching power supply circuit according to claim 2 includes an error amplification circuit that amplifies an error voltage according to a reference voltage and an output voltage, and the output voltage is regulated within an allowable voltage range including a target voltage. Provided with a feedback amount modulation circuit that outputs an output voltage obtained by modulating a plurality of different feedback amounts according to a modulation feedback amount that is repeated in a predetermined cycle as a modulation output voltage, and outputs the modulation output voltage to the error amplification circuit instead of the output voltage. It is characterized by.

  The feedback amount is the ratio of the voltage output to the error amplifier circuit with respect to the output voltage. When switching the feedback amount of the output voltage fed back to the error amplification circuit from the low feedback amount to the high feedback amount, the output voltage is changed from the high output voltage regulated according to the high feedback amount to the low feedback amount. Step down to the regulated low output voltage. This step-down speed is gentle when the load is light and steep when the load is heavy, but in either case, the feedback amount transitions from the high feedback amount to the low feedback amount again. The output voltage at the timing has a lower voltage value than the reference voltage. Therefore, the switching operation is always started according to the timing at which the feedback amount transitions from the high feedback amount to the low feedback amount, and the switching operation is performed at least once.

  A switching power supply circuit according to claim 3 includes an error amplification circuit that amplifies an error voltage according to a reference voltage and an output voltage, and the output voltage is regulated within an allowable voltage range including a target voltage. And an error voltage modulation circuit that modulates the output of the error amplification circuit in accordance with a modulation error feedback amount in which a plurality of different error feedback amounts are repeated in a predetermined cycle.

  The error feedback amount is the ratio of the voltage value input to the circuit that generates the control signal with respect to the output voltage value of the error amplifier circuit. A case will be described in which the control signal is generated from the control signal generation circuit when the output voltage value of the error amplification circuit is higher than the predetermined voltage value. When the error feedback amount is switched from the high feedback amount to the low feedback amount, the voltage value input to the control signal generation circuit also decreases, and the switching operation is not performed. Thereafter, the input voltage value to the control signal generation circuit increases as the output voltage of the switching power supply decreases. When the feedback amount is switched from the low feedback amount to the high feedback amount again, the input voltage value to the control signal generation circuit at the timing becomes a higher voltage value than the predetermined voltage value. Therefore, the switching operation is always started according to the timing when the feedback amount transitions from the low feedback amount to the high feedback amount, and the switching operation is performed at least once.

The predetermined cycle of switching the modulation reference voltage in claim 1, the predetermined cycle of switching the feedback amount of the output voltage in claim 2, and the predetermined cycle of repeating the error feedback amount in claim 3 are as follows:
Due to the magnetostrictive effect due to the switching operation of the switching power supply circuit, it is possible to set the cycle so that the transformer, the substrate and the like are not likely to vibrate. In particular, if the predetermined period is set so as not to approach the natural frequency of the transformer, the substrate, or the like, the occurrence of resonance can be prevented and vibration with a large amplitude can be prevented. Even when vibrations occur, the generation of noise can be prevented by setting a predetermined period so that the transformer, the substrate, etc. vibrate at a frequency that is outside the human audible range and does not generate noise. Since the control method of the switching power supply circuit is unchanged in both the light load state and heavy load state of the connected load, the output voltage is the reference even when the load suddenly changes to the heavy load state. Therefore, the output voltage with a small voltage dip can be obtained.

  A switching power supply circuit according to claim 4 is the switching power supply circuit according to any one of claims 1 to 3, wherein the reference voltage modulation circuit or the feedback amount modulation circuit and the error voltage modulation circuit are the reference voltage or A voltage dividing ratio switching circuit for switching a voltage dividing ratio for dividing the output voltage and the error voltage is provided.

  In the switching power supply circuit according to the fourth aspect, the voltage dividing ratio for dividing the reference voltage, the output voltage or the error voltage is switched by the voltage dividing switching circuit. Thereby, the voltage division ratio can be switched so that the reference voltage is divided into a plurality of different reference voltages. Further, the voltage division ratio can be switched so that the feedback amount for modulating the output voltage is set as a plurality of feedback amounts different from each other. Further, the voltage division ratio can be switched so that a plurality of different error feedback amounts are repeated in a predetermined cycle.

  The switching power supply circuit according to claim 5 is the switching power supply circuit according to any one of claims 1 to 3, wherein the predetermined period is a period in which the switching power supply circuit does not vibrate.

  The period in which the switching power supply circuit does not vibrate is, for example, a period deviating from the vicinity of the natural frequency. This can prevent the possibility of vibration with a large amplitude due to resonance.

  A switching power supply circuit according to a sixth aspect is the switching power supply circuit according to any one of the first to third aspects, wherein the predetermined period is a period outside the audible range.

  As a result, the frequency of vibration is outside the human audible range and can be set to a period that does not cause noise, and noise generation can be prevented.

  According to the present invention, it is possible to control the cycle of the intermittent switching operation of the switching power supply circuit by controlling the timing at which the switching operation is performed at a predetermined cycle at light load. Vibration can be prevented by setting the predetermined period to a period in which there is no possibility that the transformer, the substrate, or the like vibrates. Even when vibration occurs, the generation of noise can be prevented by setting the vibration frequency to a period that is outside the human audible range and does not generate noise.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the switching power supply circuit according to the present invention will be described below in detail with reference to FIGS. FIG. 1 shows a switching power supply circuit 1 of the present invention. The DC power supply 2 supplies an input voltage Vin and is connected to a bridge circuit 17 constituted by NMOS transistors M11 to M14. The positive electrode of DC power supply 2 is connected to the drains of transistors M11 and M12 via node N11, and the negative electrode of DC power supply 2 is connected to the sources of transistors M13 and M14 via node N12. The primary winding 4a of the transformer 4 is connected to a node N13 connecting the source of the transistor M11 and the drain of M13 and a node N14 connecting the source of the transistor M12 and the drain of M14. The upper end of secondary winding 4b is connected to node N7 via diode D3, and the lower end of secondary winding 4b is connected to node N7 via diode D4. Node N7 is connected to node N1 via coil L1. Connected. The intermediate tap N8 of the secondary winding 4b is connected to the node N2. A capacitor C1 is connected between the nodes N1 and N2. An external load RR is connected to the output terminals VO1 and VO2.

  Node N 1 is connected to the input terminal of output voltage detection circuit 5, and the output terminal of output voltage detection circuit 5 is connected to the input terminal of error amplification circuit 8. The reference voltage Vref output from the reference voltage supply unit 6 is input to the reference voltage modulation circuit 7. In the reference voltage modulation circuit 7, the input reference voltage Vref is modulated to the modulation reference voltage Vmod, and the modulated modulation reference voltage Vmod is input to the error amplification circuit 8. The output terminal of the error amplification circuit 8 and the output terminal of the triangular wave generation circuit 10 are connected to the input terminal of a PWM (Pulse Width Modulation) generation circuit 9. The output terminal of the PWM generation circuit 9 is connected to the input terminal of the MOSFET drive circuit 18, and the output terminal of the MOSFET drive circuit 18 is connected to the gates of the transistors M11 to M14. When the control signal Vctl output from the PWM generation circuit 9 is input to the MOSFET drive circuit 18, the MOSFET drive circuit 18 performs an operation of turning on the transistors M 11 and M 14 and turning off the transistors M 12 and M 13. The transistors M11 to M14 are controlled so as to repeat the operation of making M11 and M14 non-conductive and making the transistors M12 and M13 conductive, and a switching operation is performed. A circuit side including the primary winding 4a with the transformer 4 interposed therebetween is referred to as a primary side, and a circuit side including the secondary winding 4b is referred to as a secondary side.

  Consider a case where the external load RR is a type of load that switches between a light load state and a heavy load state. Specifically, for example, a power steering motor of an automobile is exemplified. The power steering motor is in a heavy load state when the steering wheel is turned, but is in a light load state without being driven during straight travel. Even when the steering is not turning at the time of stopping, it is in a light load state. Other examples include a wiper motor and a power window motor. Considering the case where these loads are fed from a switching power supply circuit, they are fed by an intermittent switching operation by the switching power supply circuit in a light load state. Noise due to vibration of components such as transformers may be generated, and noise countermeasures from the switching power supply circuit are particularly important when there is no engine noise during driving, road noise due to tires, wind noise, etc. Therefore, control of intermittent switching operation in a light load state is desired.

  In the switching power supply circuit 1 according to the present embodiment, the case where the external load RR is in a light load state will be described with reference to FIGS. In FIG. 1, in the switching power supply circuit 1, a difference voltage between the modulation reference voltage Vmod and the output voltage Vout is error-amplified by the error amplifier circuit 8. Here, the modulation reference voltage Vmod is a reference voltage having a first reference voltage VH, a second reference voltage VL, a target voltage V0, and a voltage range VR (FIG. 2). The modulation reference voltage Vmod has a cycle Fm and repeats a high voltage period TH that is the first reference voltage VH and a low voltage period TL that is the second reference voltage VL. The values of the first reference voltage VH, the second reference voltage VL, the voltage range VR, and the target voltage V0 are determined so as to be within the rated voltage of the switching regulator and the external load. For example, when the external load RR is an in-vehicle power steering motor and the modulation reference voltage is set within the allowable voltage range of 43.5 ± 1.5 (V), the target voltage V0 = 43.5 (V) The voltage range VR = 3.0 (V), the first reference voltage VH = 45.0 (V), and the second reference voltage VL = 42.0 (V).

  In the error amplification circuit 8, the output voltage Vout input from the output voltage detection circuit 5 and the modulation reference voltage Vmod input from the reference voltage modulation circuit 7 are error amplified. The error amplified voltage is input from the error amplification circuit 8 to the PWM generation circuit 9 as an error amplification voltage Verr1. The error amplifying operation is performed by amplifying the output voltage Vout with respect to the reference voltage Vref with a predetermined amplification factor using the reduced voltage width of the output voltage Vout as an error voltage. The triangular wave signal TS output from the triangular wave generation circuit 10 is also input to the PWM generation circuit 9. A comparison operation between the error amplification voltage Verr1 and the triangular wave signal TS performed in the PWM generation circuit 9 will be described. As shown in FIG. 2, when the modulation reference voltage Vmod shifts from the second reference voltage VL to the first reference voltage VH at time T0, the output voltage Vout becomes lower than the modulation reference voltage Vmod, so that the error amplification voltage Verr1 increases. (FIG. 2, arrow Y3), while the error amplification voltage Verr1 is higher than the voltage of the triangular wave signal TS, the high-level control signal Vctl is output (FIG. 2, area A2), and the bridge circuit 17 is switched to the switching operation state. . When the bridge circuit 17 is in the switching operation state, power is supplied to the secondary side, and the output voltage Vout increases, so that the error amplification voltage Verr1 decreases. When the output voltage Vout is regulated to the first reference voltage VH, the voltage value of the error amplification voltage Verr1 becomes equal to or lower than the triangular wave signal TS, so that the control signal Vctl becomes low level.

  Next, when the modulation reference voltage Vmod shifts from the first reference voltage VH to the second reference voltage VL at time T1, the output voltage Vout becomes a value sufficiently higher than the modulation reference voltage Vmod, so that the error amplification voltage Verr1 decreases ( Arrow Y4). Thereafter, the switching operation of the bridge circuit 17 is not performed (FIG. 2, area A3), and the output voltage Vout decreases due to the current consumption by the external load RR in the light load state without supplying power from the primary side. The light load state refers to a state in which an electrical device such as a motor or a circuit is in a non-operating state or a restricted operating state, and a drive current or an operating current does not flow or is restricted. In addition to the standby current of the device or circuit, the current consumption in the light load state is configured. Therefore, the current consumption in the light load state is small, and the slope at which the output voltage Vout decreases with the passage of time is limited and gentle. If the length of the low voltage period TL is determined so that the decreasing output voltage Vout does not fall below the second reference voltage VL, the control signal Vctl is maintained at a low level in the low voltage period TL. The switching operation by the bridge circuit 17 in the low voltage period TL is not performed.

  When the modulation reference voltage Vmod shifts from the second reference voltage VL to the first reference voltage VH at time T2, the error amplification voltage Verr1 rises (arrow Y5) and the error amplification voltage Verr1 becomes the triangular wave signal TS. A high level control signal Vctl is output during a period higher than the voltage (region A5), and the switching operation of the bridge circuit 17 is performed. Thereafter, the same operation is repeated at the cycle Fm.

  Therefore, when the external load RR is light load, the switching operation is reliably performed at the timing of switching the modulation reference voltage Vmod from the second reference voltage VL to the first reference voltage VH (region A2). Control can be performed so that the switching operation is not performed (region A3) until the next switching operation timing (region A5). That is, the timing at which the switching operation is performed can be controlled to the period Fm. In the present embodiment, by setting the high voltage period TH and the low voltage period TL within the period Fm, it is necessary to maintain the state in which the output voltage Vout is regulated within the range of the voltage range VR including the target voltage V0. Switching operation (that is, power supply) can be started according to the timing (time T0, time T2) when the modulation reference voltage is switched to the high voltage period TH, and can be localized in the high voltage period TH. Therefore, the cycle of the switching operation can be controlled by controlling the switching cycle of the modulation reference voltage Vmod. It should be noted that the number of times and the period in which the switching operation is performed in the region A2 and the region A5 vary depending on the external load RR and the configuration of the switching power supply circuit 1.

  The vibration can be prevented by setting the period Fm to a period in which the transformer, the substrate, and the like are not likely to vibrate due to the magnetostrictive effect. In particular, if the period Fm is set so as not to approach the natural frequency of the transformer, the substrate, or the like, the occurrence of resonance can be prevented and vibration with a large amplitude can be prevented. Even when vibration occurs, generation of noise can be prevented by setting the period Fm so that the transformer, the substrate, etc. vibrate at a frequency that is outside the human audible range and does not generate noise. For example, the period Fm is set so that vibration occurs at a frequency of several tens of hertz near the lower limit of the human audible range, or the period Fm is set so that vibration occurs at a frequency of 20 kHz or more, which is the upper limit. If it does, generation | occurrence | production of noise can be prevented. Then, unlike the conventional switching power supply circuit, the cycle Fm is not affected and changed by various parameters such as the capacitance of the capacitor C1 and current consumption in the external load RR, and the cycle Fm can be kept constant. it can.

  The length of the low voltage period TL is determined so that the output voltage Vout that decreases in the low voltage period TL does not fall below the second reference voltage VL when switching to the next high voltage period TH. Thereby, it is possible to prevent the switching operation from being performed in the low voltage period. For example, in FIG. 3A, when the load amount at the time of the light load of the external load RR is large and the slope at which the output voltage Vout decreases in the low voltage period TL1 is large, the output voltage Vout is set to the second reference at time T9. It is necessary to set the low voltage period TL1 so as not to fall below the voltage VL. At this time, in order to set the output voltage Vout so as not to fall below the second reference voltage VL at time T9 while keeping the cycle Fm at a constant value, the high voltage period TH1 may be set long. As a result, the switching power supply circuit 1 can be controlled so that the switching operation is not performed in the low voltage period TL1 from the time T8 to the time T9, and the switching operation is surely started at the times T7 and T9. That is, the high voltage period TH1 and the low voltage period TL1 are set within the period Fm, and the switching operation is started in accordance with the timing at which the modulation reference voltage is switched from the second reference voltage VL to the first reference voltage VH. Can be localized in the high voltage period TH1. Further, as shown in FIG. 3B, when the load amount of the external load RR at the time of light load is small and the slope at which the output voltage Vout decreases in the low voltage period TL2 is small, the high voltage period TH2 is the high voltage period. The low voltage period TL2 can be set longer by setting the time shorter than TH1. Note that the length of the high voltage period TH2 is preferably equal to or longer than the time TT required for the output voltage Vout to be regulated to the first reference voltage VH, but even if the high voltage period TH2 is shorter than the time TT, The low voltage period TL may be set so that the modulation reference voltage Vmod is switched from the second reference voltage VL to the first reference voltage VH before the output voltage Vout reaches the second reference voltage VL.

  Next, the operation of the switching power supply circuit 1 when the external load RR shifts from the light load state to the heavy load state will be described. In FIG. 4, the external load RR is in a light load state during a period from time T0a to time T1b, and the switching power supply circuit 1 performs the same operation as in FIG. When the external load RR shifts from the light load state to the heavy load state at time T1b, the output voltage Vout rapidly decreases to the second reference voltage VL or less (region A6), but the output voltage Vout is less than the second reference voltage VL. Then, the error amplification voltage Verr1 rises to start the switching operation, and power is supplied, so that the occurrence of voltage dip can be suppressed. In the period from time T1b to time T2a, the output voltage Vout is regulated to the second reference voltage VL. During this time, the control signal Vctl is output at the frequency of the triangular wave signal TS and the normal switching operation is performed, so that power is continuously supplied to the secondary side (region A7). When the modulation reference voltage Vmod shifts from the second reference voltage VL to the first reference voltage VH at time T2a, the output voltage Vout is regulated to the first reference voltage VH, and then the normal switching operation is performed at the frequency of the triangular wave signal TS. Is done.

  That is, since the switching power supply circuit 1 does not switch the control method regardless of the load state of the external load RR, the output voltage Vout is changed to the modulation reference voltage Vmod even when transitioning from the light load state to the heavy load state at time T1b. Can be regulated with good followability. Therefore, even when the load suddenly changes to the heavy load state, the output voltage Vout with a small voltage dip can be output.

  FIG. 5 shows a configuration example of the reference voltage modulation circuit 7 according to the present invention. The reference voltage modulation circuit 7 is a circuit that modulates the reference voltage Vref input from the reference voltage supply unit 6 and outputs the modulated reference voltage Vmod to the error amplification circuit 8. The oscillation circuit 12, the voltage division ratio switching circuit 15, Is provided. The output terminal of the reference voltage supply unit 6 is connected to the node N4 via the load R1. Further, node N4 is connected to ground voltage Vss via load R2, to ground voltage Vss via load R3 and NMOS transistor M2, and to the input terminal of error amplifier circuit 8. The voltage value of the node N4 is output to the error amplifier circuit 8 as the modulation reference voltage Vmod. The output node N5 of the oscillation circuit 12 is connected to the gate of the transistor M2. In oscillation circuit 12, power supply voltage Vcc is connected to ground voltage Vss through load R4, node N6, and load R5. Node N6 is connected to the + terminal of comparator 13, and is also connected to node N5 via load R6. Node N5 is connected to node N10 via load R7, node N9, and load R8. Node N10 is connected to the negative terminal of comparator 13 and to ground voltage Vss via capacitor C2. Node N5 is connected to node N9 via NMOS transistor M3 and to the gate of transistor M3 via inverter. The output voltage Vcmp of the comparator 13 is the high level power supply voltage Vcc when the voltage V (+) input to the + terminal is higher than the − terminal, and the voltage V (−) input to the − terminal. ) Is higher than the + terminal, the ground voltage Vss is at a low level.

  FIG. 7 shows a timing chart of the reference voltage modulation circuit 7. At time T10, the output voltage Vcmp transitions to the low level ground voltage Vss. The low-level output voltage Vcmp is input to the gate of the transistor M2, and the transistor M2 is turned off. At this time, the voltage of the node N4 becomes a voltage value (first reference voltage VH) divided by the loads R1 and R2 of the voltage dividing ratio switching circuit 15, and the voltage value of the node N4 is the error reference circuit Vmod as the modulation reference voltage Vmod. (Arrow Y6). Since node N5 is connected to ground voltage Vss, and node N6 is connected to power supply voltage Vcc via load R4 and to ground voltage Vss via loads R5 and R6, the resistance divided value of node N6 is low. The divided voltage value VPL of the level is input to the + terminal of the comparator 13. The low-level output voltage Vcmp is inverted to high level by the inverter 14 and input to the gate of the transistor M3, and the transistor M3 is turned on. Then, since the load R7 is bypassed, the resistance value between the nodes N5 and N10 becomes the resistance value of the load R8 alone and is in a low resistance state. At this time, since the capacitor C2 is discharged, the negative terminal voltage V (−) of the comparator 13 decreases, and when it decreases below the positive terminal voltage V (+), the high voltage period TH3 ends at time T11. Note that since the resistance value between the nodes N5 and N10 is in the low resistance state and the time constant is small, the high voltage period TH3 can be shorter than the low voltage period TL3 described later.

  When the voltage V (−) falls below the voltage V (+) at time T11, the output voltage Vcmp of the comparator 13 is set to the high level power supply voltage Vcc (arrow Y7), and the high level output voltage Vcmp is the gate of the transistor M2. The transistor M2 is turned on. At this time, the voltage of the node N4 becomes a voltage value (second reference voltage VL) divided by the loads R2 and R3 and the load R1 connected in parallel of the voltage dividing ratio switching circuit 15, and the voltage value of the node N4 is modulated. The reference voltage Vmod is output to the error amplifier circuit 8 (arrow Y8). Node N5 is connected to power supply voltage Vcc, and node N6 is connected to power supply voltage Vcc via loads R4 and R6, and to ground voltage Vss via load R5. Therefore, the resistance divided value of node N6 is high. The divided voltage value VPH of the level is input to the + terminal of the comparator 13. The high-level output voltage Vcmp is inverted to a low level by the inverter 14 and then input to the gate of the transistor M3, so that the transistor M3 is turned off. Then, since the load R7 is not bypassed, the resistance value between the nodes N5 and N10 becomes a combined resistance value of the loads R8 and R7, and is in a high resistance state. At this time, since the capacitor C2 is charged, the minus terminal voltage V (−) of the comparator 13 rises, and when it rises above the plus terminal voltage V (+), the low voltage period TL3 ends at time T12. Note that since the resistance value between the nodes N5 and N10 is in a high resistance state and the time constant is large, the low voltage period TL3 can be longer than the above-described high voltage period TH3.

  After time T12, the same operation as at time T10 is repeated. With the above operation, the reference voltage modulation circuit 7 modulates the reference voltage Vref input from the reference voltage supply unit 6 and outputs the modulated reference voltage Vmod to the error amplification circuit 8. Note that the period lengths of the high voltage period TH3 and the low voltage period TL3 can be set as appropriate as described with reference to FIGS. That is, by combining the resistance values of the loads R7 and R8 and the capacitance value of the capacitor C2, it is possible to set the high voltage period TH3 and the low voltage period TL3 according to the load at the time of light load. The values of the first reference voltage VH and the second reference voltage VL of the modulation reference voltage Vmod are set to be within the rated voltage of the connected external load RR by combining the resistance values of the loads R1 to R3. Is possible.

  Further, other configuration examples of the oscillation circuit 12 in FIG. 5 are shown in FIGS. The oscillation circuit 12a in FIG. 6A includes a diode D1 instead of the NMOS transistor M3 and the inverter 14 in the oscillation circuit 12. In the oscillation circuit 12a, when the capacitor C2 is discharged, the load R7 is bypassed and the time constant is small, and when charging, the load R7 is not bypassed and the time constant is large. Therefore, the low voltage period TL3 is longer than the high voltage period TH3. can do. Then, by appropriately combining the resistance values of the loads R4 to R8 and the capacitance value of the capacitor C2, the time ratio between the low voltage period TL3 and the high voltage period TH3 within a range where the low voltage period TL3 is longer than the high voltage period TH3. Can be set to a predetermined value. In addition, the oscillation circuit 12b in FIG. 6B includes a diode D2 connected in the opposite direction to the diode D1 instead of the diode D1 in the oscillation circuit 12a. In the oscillation circuit 12b, the low voltage period TL3 can be shorter than the high voltage period TH3. Then, by appropriately combining the resistance values of the loads R4 to R8 and the capacitance value of the capacitor C2, the time ratio between the low voltage period TL3 and the high voltage period TH3 within a range where the low voltage period TL3 is shorter than the high voltage period TH3. Can be set to a predetermined value.

  6C has a circuit configuration in which the load R7, the NMOS transistor M3, and the inverter 14 are omitted when the transistor configuration of the buffer of the comparator 13 in the oscillation circuit 12 is an open drain configuration. When the capacitor C2 is discharged, discharging is performed through the path of the node N10, the load R8, the node N5, and the comparator 13, and when charging the capacitor C2, the path of the power supply voltage Vcc, the load R4, the load R6, the node N5, the load R8, and the node N10 is discharged. In this case, charging is performed in a higher resistance state and a time constant is larger than that during discharging. Therefore, the low voltage period TL3 can be longer than the high voltage period TH3. Then, by appropriately combining the resistance values of the loads R4, R5, R6, and R8 and the capacitance value of the capacitor C2, the low voltage period TL3 and the high voltage period TH3 are within the range where the low voltage period TL3 is longer than the high voltage period TH3. Can be set to a predetermined value.

  The present invention is not limited to the above-described embodiment, and it goes without saying that various improvements and modifications can be made without departing from the spirit of the present invention. In the present embodiment, the reference voltage modulation circuit 7 is provided between the reference voltage supply unit 6 and the error amplification circuit 8, and modulates the reference voltage Vref and outputs it as the modulation reference voltage Vmod to the error amplification circuit 8. It is not restricted to this form. For example, in FIG. 5, the reference voltage modulation circuit 7 may be used as a feedback amount modulation circuit, and the feedback amount modulation circuit may be connected between the output voltage detection circuit 5 and the error amplification circuit 8. The feedback amount modulation circuit operates to modulate the output voltage Vout input from the output voltage detection circuit 5 to a modulated output voltage Vum reduced by a predetermined feedback amount and output the modulated output voltage Vout to the error amplification circuit 8. At this time, as shown in FIG. 5 and FIG. 8, at the timing (FIG. 8, time T20) when the low voltage period TLO is switched to the high voltage period THO, the transistor M2 (FIG. 5) is turned on to reduce the feedback amount. Since the feedback amount is used, the voltage value of the modulation output voltage Vouum output to the error amplifying circuit 8 sharply decreases, and the error amplifying circuit 8 detects a large error voltage and starts the switching operation of the bridge circuit 17. (Area A9). When the modulation output voltage Vum is regulated to the reference voltage Vref, if the transistor M2 (FIG. 5) is turned off and the feedback amount is increased to be the second feedback amount (time T21), the error amplifier circuit 8 Since the voltage value of the output modulation output voltage Vou increases steeply, the error amplifying circuit 8 does not detect the error voltage, and the bridge circuit 17 maintains the state where the switching operation is stopped in the low voltage period TLO. Vout gradually decreases. As described above, the output voltage Vout alternately repeats the high voltage period THO regulated to the first output voltage VHO and the low voltage period TLO in which the voltage drops due to the consumption current of the external load at a predetermined cycle. As a result, the feedback amount transitions from the second feedback amount to the first feedback amount, and the switching operation is surely started according to the timing when the modulation output voltage V.sub.um decreases (region A9). It is possible to control the switching operation not to be performed until the operation timing, and the timing at which the switching operation is performed can be controlled to the period FO.

  In FIG. 5, the reference voltage modulation circuit 7 may be used as an error voltage modulation circuit, and the error voltage modulation circuit may be connected between the error amplification circuit 8 and the PWM generation circuit 9 (FIG. 1). At this time, the error voltage modulation circuit operates to output the error amplification voltage Verr1 input from the error amplification circuit 8 to the PWM generation circuit 9 as the modulation error amplification voltage Vem1 modulated by the modulation error feedback amount. Here, the error feedback amount is a ratio of a voltage value input to the PWM generation circuit 9 that generates the control signal with respect to the error amplification voltage Verr1 of the error amplification circuit. The modulation error feedback amount is a feedback amount that repeats a plurality of different error feedback amounts at a predetermined cycle. The PWM generation circuit 9 outputs a high-level control signal Vctl while the modulation error amplification voltage Vem1 is higher than the voltage of the triangular wave signal TS. When the error feedback amount is switched from the high feedback amount to the low feedback amount, the modulation error amplification voltage Vem1 decreases and becomes a value lower than the voltage of the triangular wave signal TS. Therefore, the control signal Vctl is not output and power is not supplied to the secondary side. . Then, the modulation error amplification voltage Vem1 increases as the output voltage Vout decreases. When the feedback amount is switched again from the low feedback amount to the high feedback amount, the modulation error amplification voltage Vem1 rises at the switching timing and has a period during which the voltage value is high with respect to the triangular wave signal TS. Therefore, the switching operation is always started according to the timing at which the error feedback amount transitions from the low feedback amount to the high feedback amount, and the switching operation is performed at least once.

  In the present embodiment, the first reference voltage VH and the second reference voltage VL in FIG. 2 use the upper limit value and the lower limit value within the allowable voltage range, but are not limited to this form. The first reference voltage VH and the second reference voltage VL may be any voltage level as long as they are within the allowable voltage range. Also in FIG. 8, the first output voltage VHO and the second output voltage VLO may be at any voltage level as long as they are within the allowable voltage range.

  In the present embodiment, the output voltage Vout or the reference voltage Vref is directly input to the error amplifier circuit 8 without being divided. However, the present invention is not limited to this form, and is input to the error amplifier circuit 8 in a divided state. It goes without saying that it may be done.

  In this embodiment, the modulation reference voltage Vmod or the modulation output voltage Vum is switched between the high voltage value and the low voltage value at a predetermined period Fm or FO. However, the present invention is not limited to this form. For example, an intermediate voltage value may be added to the high voltage value and the low voltage value, and these voltage values may be switched at a predetermined period Fm or FO. The intermediate voltage value is not limited to one and may be a plurality of values. For example, a configuration may be adopted in which a load and NMOS transistors are provided so that the voltage dividing ratio switching circuit 15 can be switched to a voltage division of three or more, and a plurality of oscillation circuits are provided corresponding to the respective NMOS transistors. At this time, if the resistance value of each oscillation circuit and the capacitance of the capacitor are appropriately adjusted, the period for switching to each divided voltage value can be set to a predetermined value.

  In the present embodiment, the primary side of the switching power supply circuit 1 in FIG. 1 includes the bridge circuit 17 configured by the NMOS transistors M11 to M14. However, the present invention is not limited to this configuration. Needless to say, it may be configured to have a transistor for the above purpose.

It is a figure which shows the switching power supply circuit 1 of this invention. It is a figure which shows operation | movement when the external load RR in the switching power supply circuit 1 of this invention is a light load state. It is a figure which shows the output voltage Vout in the switching power supply circuit 1 of this invention. It is a figure which shows operation | movement when the external load RR transfers to a heavy load state in the switching power supply circuit 1 of this invention. 3 is a diagram illustrating a configuration example of a reference voltage modulation circuit 7. FIG. It is a figure which shows the structural example of an oscillation circuit. 6 is a timing chart of the reference voltage modulation circuit 7. FIG. It is a figure which shows operation | movement of a switching power supply circuit provided with a feedback amount modulation circuit. It is a figure which shows the conventional switching power supply circuit. It is a figure which shows the power supply circuit of the conventional ringing choke converter switching system.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Switching power supply circuit 4 Transformer 5 Output voltage detection circuit 6 Reference voltage supply part 7 Reference voltage modulation circuit 8 Error amplification circuit 9 PWM generation circuit 10 Triangular wave generation circuit 17 Bridge circuit RR External load Vctl Control signal Vref Reference voltage Vmod Modulation reference voltage Vout Output voltage Verr1 Error amplification voltage Vcmp Output voltage Fm, FO Period TH, TH1, TH2, TH3 High voltage period TL, TL2, TL2, TL3 Low voltage period

Claims (6)

In a power supply circuit including an error amplification circuit that amplifies an error voltage according to a reference voltage and an output voltage, and the output voltage is regulated within an allowable voltage range including a target voltage,
A switching power supply circuit comprising: a reference voltage modulation circuit that outputs a modulation reference voltage that repeats a plurality of different reference voltages at a predetermined period to the error amplification circuit instead of the reference voltage. In a power supply circuit including an error amplification circuit that amplifies an error voltage according to a reference voltage and an output voltage, and the output voltage is regulated within an allowable voltage range including a target voltage,
A feedback amount modulation that outputs the modulated output voltage to the error amplifying circuit instead of the output voltage, wherein the output voltage is modulated according to a modulated feedback amount in which a plurality of different feedback amounts are repeated in a predetermined cycle. A switching power supply circuit comprising a circuit. In a power supply circuit that includes an error amplification circuit that amplifies an error voltage according to a reference voltage and an output voltage, and the output voltage is regulated within an allowable voltage range including a target voltage,
A switching power supply circuit comprising: an error voltage modulation circuit that modulates an output of the error amplification circuit according to a modulation error feedback amount in which a plurality of different error feedback amounts are repeated in a predetermined cycle.   The reference voltage modulation circuit, the feedback amount modulation circuit, or the error voltage modulation circuit includes a voltage dividing ratio switching circuit that switches a voltage dividing ratio for dividing the reference voltage, the output voltage, or the error voltage. The switching power supply circuit according to any one of claims 3 to 3.   The switching power supply circuit according to any one of claims 1 to 3, wherein the predetermined period is a period in which the switching power supply circuit does not vibrate. The switching power supply circuit according to any one of claims 1 to 3, wherein the predetermined period is a period outside the audible range.

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