JP2005073335A - Switching power supply circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To attain a high power conversion efficiency as a complex resonance converter comprising a synchronous rectification circuit while reducing the circuit scale and the cost through simplification of circuitry. <P>SOLUTION: A complex resonance converter is provided, on the secondary thereof, with a winding voltage detection system synchronous rectification circuit. A gap length of a power insulation transformer PIT is set at about 1.5 mm, and a coupling factor is lowered to about 0.8. The numbers of turns of the primary winding N1 and secondary windings N2A and N2B are set such that the induction voltage level per one turn (T) of the secondary winding becomes 2V/T. Since flux density in the core of the power insulation transformer PIT becomes lower than a specified level, secondary rectification current is kept in continuous mode even under heavy load conditions. When an inductor Ld is inserted into each rectification current passage on the secondary, reverse current being induced in the rectification current by the back-emf of the inductor is suppressed and reactive power is reduced furthermore. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a switching power supply circuit provided as a power supply for various electronic devices.

As a switching power supply circuit, a circuit using a switching converter such as a flyback converter or a forward converter is widely known. Since these switching converters have a rectangular switching operation waveform, there is a limit to suppression of switching noise. Further, it has been found that there is a limit to improving the power conversion efficiency due to its operating characteristics.
Various switching power supply circuits using resonant converters have been proposed and put into practical use. The resonant converter can easily obtain high power conversion efficiency, and low noise is realized by making the switching operation waveform sinusoidal. In addition, there is an advantage that it can be configured with a relatively small number of parts.

  The circuit diagram of FIG. 8 shows an example of a conventional switching power supply circuit including a resonant converter. In the power supply circuit shown in this figure, a partial voltage resonance circuit is combined with a separately excited current resonance type converter.

  In the power supply circuit shown in this figure, first, a full-wave rectifying / smoothing circuit including a bridge rectifying circuit Di and one smoothing capacitor Ci is provided for the commercial AC power supply AC. Then, by the full-wave rectification operation of the bridge rectifier circuit Di and the smoothing capacitor Ci, a rectified and smoothed voltage Ei (DC input voltage) is obtained at both ends of the smoothing capacitor Ci. The rectified and smoothed voltage Ei is at a level corresponding to the same magnification as the AC input voltage VAC.

  As shown in the figure, as the current resonance type converter for switching by inputting the DC input voltage, two switching elements Q1, Q2 by MOS-FETs are connected by half bridge coupling. Damper diodes DD1 and DD2 formed of body diodes are connected in parallel with each other between the drains and sources of the switching elements Q1 and Q2, respectively, in the direction shown in the drawing.

  A partial resonance capacitor Cp is connected in parallel between the drain and source of the switching element Q2. A parallel resonance circuit (partial voltage resonance circuit) is formed by the capacitance of the partial resonance capacitor Cp and the leakage inductance L1 of the primary winding N1. A partial voltage resonance operation in which voltage resonance occurs only when the switching elements Q1, Q2 are turned off is obtained.

  In this power supply circuit, in order to switch the switching elements Q1 and Q2, for example, an oscillation / drive circuit 2 using a general-purpose IC is provided. The oscillation / drive circuit 2 includes an oscillation circuit and a drive circuit circuit. Then, a drive signal (gate voltage) having a required frequency is applied to each gate of the switching elements Q1 and Q2 by the oscillation circuit and the drive circuit. Thereby, the switching elements Q1 and Q2 perform the switching operation so as to be alternately turned on / off at a required switching frequency.

The insulating converter transformer PIT transmits the switching outputs of the switching elements Q1 and Q2 to the secondary side. One end of the primary winding N1 of the insulation transformer PIT is connected to a connection point (switching output point) between the source of the switching element Q1 and the drain of the switching element Q2 through a series connection of the primary side parallel resonant capacitor C1. Thus, the switching output is transmitted.
The other end of the primary winding N1 is connected to the primary side ground.
Here, depending on the capacitance of the series resonance capacitor C1 and the leakage inductance L1 of the insulating converter transformer PIT including the primary winding N1, a primary side series resonance circuit for making the operation of the primary side switching converter a current resonance type is formed. To do.

According to the above description, the primary side switching converter shown in this figure has the operation as the current resonance type by the primary side series resonance circuit (L1-C1) and the part by the partial voltage resonance circuit (Cp // L1) described above. A voltage resonance operation is obtained.
That is, the power supply circuit shown in this figure adopts a form in which a resonance circuit for making the primary side switching converter a resonance type is combined with another resonance circuit. In this specification, such a switching converter is referred to as a composite resonance type converter.

  Although illustration explanation here is omitted, the structure of the insulating converter transformer PIT includes, for example, an EE type core in which an E type core made of a ferrite material is combined. Then, after dividing the winding part between the primary side and the secondary side, the primary winding N1 and the secondary windings (N2A, N2B) to be described below are connected to the central magnetic leg of the EE core. Wrapped.

  As the secondary winding of the insulating converter transformer PIT, secondary windings N2A and N2B which are divided into two parts by winding a center tap are wound. An alternating voltage corresponding to the switching output transmitted to the primary winding N1 is excited in these secondary windings N2A and N2B.

  In this case, the center taps of the secondary windings N2A and N2B are connected to the secondary side ground. Then, a full-wave rectifier circuit composed of rectifier diodes DO1 and DO2 and a smoothing capacitor CO is connected to the secondary windings N2A and N2B as shown in the figure. As a result, the secondary side DC output voltage EO is obtained as the voltage across the smoothing capacitor CO. The secondary side DC output voltage EO is supplied to a load side (not shown) and is also branched and inputted as a detection voltage for the control circuit 1 described below.

  The control circuit 1 supplies a detection output corresponding to the level change of the secondary side DC output voltage EO to the oscillation / drive circuit 2. The oscillation / drive circuit 2 drives the switching elements Q1 and Q2 such that the switching frequency is varied according to the input detection output of the control circuit 1. Thus, the level of the secondary side DC output voltage is stabilized by varying the switching frequency of the switching elements Q1, Q2.

  FIG. 9 shows operation waveforms when the power supply circuit having the circuit configuration shown in this figure is adapted to load conditions as a low voltage and large current. The operation waveform shown in FIG. 9 is obtained by performing measurement under the conditions of AC input voltage VAC = 100V and load power Po = 100W. Further, the state of the low voltage and large current here is a state where the secondary side DC voltage Eo = 5V and the primary side series resonance current Io = 25 A which is the switching current of the primary side switching converter.

Further, in order to obtain the experimental result based on the operation waveform shown in FIG. 9, the following conditions and selection of component elements in the power supply circuit are performed.
First, the number of turns of the secondary windings N2A and N2B and the primary winding N1 is set so that the induced voltage level per 1T (turn) of the secondary winding is 5 V / T. Specifically, the secondary winding N2A = N2B = 1T and the primary winding N1 = 30T.
A gap of about 1.0 mm is formed with respect to the central magnetic leg of the EE type core of the insulating converter transformer PIT. Thus, a coupling coefficient of about 0.85 is obtained by the primary winding N1 and the secondary windings N2A and N2B.
The primary side series resonant capacitor C1 = 0.068 μF and the partial voltage resonant capacitor Cp = 330 pF are selected, and 50 A / 40 V Schottky diodes are selected as the rectifier diodes Do1 and Do2.

In the waveform diagram shown in FIG. 9, the voltage V1 across the switching element Q2 corresponds to the on / off state of the switching element Q2. In other words, the rectangular wave is clamped at the 0 level during the period T2 when the switching element Q2 is turned on and at the predetermined level during the period T1 when the switching element Q2 is turned off. Then, as shown in the period T2, the switching current IDS2 flowing through the switching element Q2 // damper diode DD2 becomes negative by flowing through the damper diode DD2 at the time of turn-on. A waveform flows from the drain to the source of the element Q2 and is turned off in the period T1 and becomes 0 level.
The switching element Q1 performs switching by alternately turning on / off the switching element Q2. Therefore, the switching current IDS1 flowing through the switching element Q1 // damper diode DD1 has a waveform whose phase is shifted by 180 ° with respect to the switching current IDS2.

  The primary side series resonance current Io flowing through the primary side series resonance circuit (C1-L1) connected between the switching output points of the switching elements Q1, Q2 and the primary side ground is a combination of the switching current IDS1 and the switching current IDS2. A sine wave component corresponding to the waveform as a resonance current of the primary side series resonance circuit (C1-L1) and a sawtooth wave component generated by the exciting inductance of the primary winding N1 are combined to form a waveform.

The load power Po = 100 W, which is the measurement condition at this time, is a heavy load condition close to the maximum as the load condition supported by the power supply circuit shown in FIG. Under conditions that tend to be heavy loads in the power range, the secondary side rectified current is in discontinuous mode.
That is, the secondary winding voltage V2 generated in the secondary winding N2A is a waveform that is clamped at a predetermined absolute value level only during a period in which the primary side series resonance current Io flows in a sine wave shape as shown in FIG. The period during which the sawtooth wave component due to the excitation inductance flows as the primary side series resonance current Io is 0 level. A waveform obtained by inverting the secondary winding voltage V2 is generated in the secondary winding N2B.
For this reason, the rectified current I1 flowing through the rectifier diode Do1 and the rectified current I2 flowing through the rectifier diode Do2 flow only in the periods DON1 and DON2 in which the primary side series resonance current Io flows in a sine wave shape, and in other periods Do not flow together. That is, the secondary side rectified current is discontinuous and flows into the smoothing capacitor.

  The forward voltage drop of the rectifier diodes Do1 and Do2 which are Schottky diodes is 0.6V. In the secondary side operation as described above, the rectified currents I1 and I2 are correspondingly 35 Ap as shown in the figure. Since it becomes a high level, the conduction loss by these rectifier diode elements becomes remarkable, and the power loss increases. As an actual measurement result, the DC → DC power conversion efficiency is about 82% when the DC input voltage (rectified smoothing voltage Ei) = 100V.

Therefore, as a technique for reducing the conduction loss of the rectified current on the secondary side, a synchronous rectifier circuit is known in which rectification is performed by a low on-resistance MOS-FET. An example of such a synchronous rectifier circuit is shown in FIG.
In FIG. 10, only the secondary side configuration of the insulating converter transformer PIT is shown. The configuration on the primary side is the same as in FIG. Further, as the constant voltage control method, a switching frequency control method is employed in which the switching frequency of the primary side switching converter is variably controlled according to the level of the secondary side DC output voltage Eo.
Also, the power supply circuit adopting the secondary side configuration shown in FIG. 10 has the same low voltage and large current (VAC = 100 V, load power Po = 100 W, Eo = 5 V, Io = 25 A) as in FIG. It shall correspond to the condition.

  Also in this case, as the secondary winding, one ends of the secondary windings N2A and N2B having the same number of turns are connected by the center tap, and the center tap output is connected to the positive terminal of the smoothing capacitor Co. . The other end of the secondary winding N2A is connected to the secondary side ground (the negative terminal side of the smoothing capacitor Co) via the drain → source of the N-channel MOS-FET Q3. Similarly, the other end of the secondary winding N2B is also connected to the secondary side ground (the negative terminal side of the smoothing capacitor Co) via the drain → source of the N-channel MOS-FET Q4. That is, in this case, the MOS-FETs Q3 and Q4 are inserted in series on the negative electrode side in each rectified current path of the secondary windings N2A and N2B. Body diodes DD3 and DD4 are connected to the drain and source of the MOS-FETs Q3 and Q4, respectively.

The driving circuit for driving the MOS-FET Q3 has a gate resistor Rg1 connected between the connection point between the secondary winding N2B and the drain of the MOS-FET Q4 and the gate of the MOS-FET Q3, and the gate of the MOS-FET Q3. And a secondary side ground, a resistor R11 is connected.
Similarly, the driving circuit for driving the MOS-FET Q4 has a gate resistor Rg2 connected between the connection point between the secondary winding N2A and the drain of the MOS-FET Q3 and the gate of the MOS-FET Q4, and also the MOS-FET Q4. A resistor R12 is connected between the gate and the secondary side ground.

In the MOS-FET, when an ON voltage is applied to the gate, the drain-source is equivalent to a simple resistor, so that current flows in both directions. If this is to function as a rectifying element on the secondary side, a current must flow only in the direction in which the positive terminal of the smoothing capacitor Co is charged. When a current flows in the opposite direction, a discharge current flows from the smoothing capacitor Co to the insulating converter transformer PIT side, and power cannot be effectively transmitted to the load side. Further, the MOS-FET generates heat and noise due to the reverse current, resulting in switching loss on the primary side.
The drive circuit described above is a circuit for switching and driving the MOS-FETs Q3 and Q4 so that the current flows only in the direction of charging the positive terminal of the smoothing capacitor Co based on detecting the voltage of the secondary winding. It is.

The waveform diagram of FIG. 11 shows the operation when the load power Po = 100 W as the power supply circuit (the primary side is the same as FIG. 8) adopting the secondary side configuration shown in FIG. As described above, the load power Po = 100 W in this case is almost the maximum load condition.
In this figure, the voltage V1 across the switching element Q2 and the secondary winding voltage V2 obtained across the secondary windings N2A-N2B corresponding to this are at the same timing as in FIG. . The secondary winding voltage V2 shown in FIG. 11 has a polarity when viewed from the connection point side between the secondary winding N2A and the gate resistance Rg2, and the connection between the secondary winding N2B and the gate resistance Rg1. When viewed from the point side, the polarity is reversed.
When the secondary winding voltage V2 having the polarity shown in this figure is clamped at a predetermined negative level, the driving circuit for the MOS-FET Q4 has a gate resistance Rg2 and a resistance R12 with respect to the gate of the MOS-FET Q4. Thus, an operation is performed so as to apply an ON voltage of a level set by the above.
Similarly, when the MOS-FET Q3 drive circuit (gate resistor Rg1, resistor R11) reaches a period in which the secondary winding voltage (V2) having a polarity opposite to that shown in FIG. Therefore, the on-voltage is applied to the gate of the MOS-FET Q3.

  As a result, positive rectified currents I1 and I2 flow in the MOS-FETs Q3 and Q4 in the periods DON1 and DON2, respectively, as illustrated. The rectified currents I1 and I2 flowing during the period in which the illustrated secondary winding voltage V2 is clamped positive / negative are 35 Ap as in the case of the circuit of FIG. 8 (rectified currents I1 and I2 in the waveform diagram of FIG. 9). It is. However, the MOS-FETs Q3 and Q4 have a low on-resistance, and the conduction loss of the rectified current can be made extremely low as compared with the rectifier diodes Do1 and Do2 using Schottky diodes. Further, as can be understood from the fact that the drive circuit is composed only of resistance elements, the winding voltage detection method has an advantage that the drive circuit system has a simple configuration.

However, under the condition of a heavy load (load power Po = 100 W) as in the case corresponding to FIG. 11, the secondary side rectified current is also in the discontinuous mode in this power supply circuit. This is also indicated in FIG. 11 by the periods DON1 and DON2 being discontinuous.
In this discontinuous mode, even if the charging current to the smoothing capacitor Co becomes 0 level as the rectified currents I1 and I2, current flows in the same direction in the primary winding N1 of the insulating converter transformer PIT. This is because the exciting inductance component of the primary winding N1 flows with the same polarity as the immediately preceding timing as the primary side series resonance current Io in the period other than the periods DON1 and DON2 in the waveform diagram of FIG. pointing. Therefore, in practice, since the polarity of the voltage induced in the secondary windings N2A and N2B is not reversed, the MOS-FETs Q3 and Q4 are maintained in the on state without being completely turned off. As a result, as shown in the figure, currents in the reverse direction flow as the rectified currents I1 and I2 outside the periods DON1 and DON2. The rectified currents I1 and I2 in the reverse direction other than the periods DON1 and DON2 generate reactive power. At this time, the level of the rectified currents I1 and I2 is relatively high at 8 Ap. It will be big.
As described above, when the winding voltage detection method is adopted as the synchronous rectification circuit, although the conduction loss of the rectification current is reduced, the reactive power is generated as described above, so that the power conversion efficiency is effectively improved as a whole. Currently, it is difficult to plan.

The waveform diagram of FIG. 12 shows the operation of the power supply circuit having the secondary side configuration shown in FIG. 10 under a light load condition.
Even in the actual power supply circuit shown in FIG. 10, constant voltage control is performed by switching frequency control as described in the configuration of the power supply circuit shown in FIG. 8, but the secondary side DC output becomes a light load condition. When the voltage rises, the secondary side DC output voltage is lowered by increasing the switching frequency, thereby operating to stabilize.
In such a light load state, the secondary winding voltage V2 is inverted at substantially the same timing with respect to the voltage V1 across the switching element Q2 shown in FIG. The next-side rectified currents I1 and I2 flow so that the smoothing capacitor Co is continuously charged without a pause period between the periods DON1 and DON2. That is, it becomes a continuous mode. At this time, there is no period during which the rectified currents I1 and I2 in the reverse direction flow as shown in the operation at the time of heavy load in FIG. 14, and no reactive power is generated accordingly.
As described above, the power supply circuit having the configuration in which the secondary rectifier circuit system is replaced with the synchronous rectifier circuit based on the winding voltage detection method still has a problem in that the power conversion efficiency is lowered under heavy load.

Therefore, as a technique for solving the problem of generation of reactive power due to a rectified current in the reverse direction as shown in FIG. 11, a synchronous rectifier circuit based on a rectified current detection method is known. This rectified current detection method is a technique for turning off the MOS-FET before the rectified current charged in the smoothing capacitor Co becomes 0 level.
An example of the configuration of a synchronous rectifier circuit based on this rectified current detection method is shown in FIG. In this figure, a configuration by half-wave rectification is shown in order to simplify the description.

As a rectified current detection method, a current transformer TR is provided to detect a current flowing through the secondary winding N2. The primary winding Na of the current transformer is connected to the end of the secondary winding N2 and the drain of the MOS-FET Q4. The source of the MOS-FET Q4 is connected to the negative terminal of the smoothing capacitor Co.
A resistor Ra is connected in parallel to the secondary winding Nb of the current transformer, and the diodes Da and Db are connected in parallel so that the forward voltage directions are opposite to each other. Form. A comparator 20 is connected to the parallel connection circuit. The reference voltage Vref is input to the inverting input of the comparator 20. Note that the connection point between the reference voltage Vref and the inverting input of the comparator 20 is connected to the end of the parallel connection circuit on the side where the anode of the diode Da and the cathode of the diode Db are connected. The non-inverting input of the comparator 20 is connected to the end of the parallel connection circuit on the side where the cathode of the diode Da and the anode of the diode Db are connected.
In this case, the output of the comparator 20 is amplified by the buffer 21 and applied to the gate of the MOS-FET Q4.

The operation of the circuit having the configuration shown in FIG. 13 is shown in FIG.
When the voltage induced in the secondary winding N2 becomes larger than the voltage (Eo) across the smoothing capacitor Co, first, the smoothing capacitor Co is charged in the direction from the anode to the cathode of the body diode of the MOS-FET Q4. The rectified current Id begins to flow. Since this rectified current Id flows through the primary winding Na of the current transformer, a voltage Vnb corresponding to the rectified current Id flowing through the primary winding Na is induced in the secondary winding Nb of the current transformer. The comparator 20 compares the reference voltage Vref with the voltage Vnb, and outputs an H level when the voltage Vnb exceeds the reference voltage Vref. This H level output is applied as an ON voltage from the buffer 21 to the gate of the MOS-FET Q4 to turn on the MOS-FET Q4. Thereby, the rectified current Id flows in the drain → source direction of the MOS-FET Q4. In FIG. 14, it is shown as a rectified current Id that flows due to positive polarity.

  As the time elapses, the level of the rectified current Id decreases. In response to this, when the voltage Vnb becomes lower than the reference voltage Vref, the comparator 20 inverts the output. By outputting this inverted output through the buffer 21, the gate capacitance of the MOS-FET Q4 is discharged, and the MOS-FET Q4 is turned off. At this time, the remaining rectified current Id flows through the body diode DD4 in a short time.

With such an operation, the MOS-FET Q4 is turned off at a timing before the rectified current Id becomes 0 level. As a result, as shown in FIG. 11, during the period in which the rectified current is discontinuous, the reverse current does not flow through the MOS-FET and reactive power is not generated, and the power conversion efficiency is increased accordingly.
For example, the DC-to-DC power conversion efficiency when the secondary side configuration of the power supply circuit shown in FIG. 8 is a synchronous rectification circuit based on the rectification current detection method of full-wave rectification based on the configuration shown in FIG. As a result of measurement under the same conditions as in FIG. 9 and FIG. 11, the measurement result was improved to about 90%.

JP 2003-111401 A

However, in the above-described synchronous rectification circuit of the rectification current detection method, as can be seen from FIG. 13, at least one set of current transformers and one output of the current transformer correspond to one MOS-FET. A relatively complicated drive circuit system for driving is required. As a result, the circuit configuration becomes complicated, which results in inconveniences such as a reduction in manufacturing efficiency, an increase in cost, and an increase in circuit board size.
In particular, when the secondary side is provided with a synchronous rectification circuit of a rectification current detection method based on the configuration of the primary side switching converter shown in FIG. 13, it is necessary to provide a full-wave rectification circuit on the secondary side. . Therefore, two sets of the above-described current transformer and driving circuit system are required corresponding to each of the MOS-FETs Q3 and Q4, and the above-described problem is further increased.
Thus, the winding voltage detection method and the rectified current detection method are disadvantageous in terms of power conversion efficiency due to reactive power, but the circuit configuration is simple. The rectified current detection method is advantageous in terms of power conversion efficiency because reactive power does not occur, but has a trade-off relationship that the circuit configuration becomes complicated.
Therefore, a power supply circuit including a synchronous rectifier circuit is required to adopt a configuration that is as simple as possible and can eliminate an increase in loss due to reactive power.

Therefore, in the present invention, in view of the above problems, the switching power supply circuit is configured as follows.
That is, first, switching means formed with a switching element that performs switching so as to intermittently input DC input voltage, drive means for switching driving the switching element, and switching output of the switching means as primary It transmits from the side to the secondary side, and includes at least a primary winding and an insulating converter transformer around which the secondary winding is wound.
A primary side resonance circuit for making the operation of the switching means resonant is formed by at least the leakage inductance component of the primary winding of the insulating converter transformer and its own capacitance, so that a predetermined primary side circuit is formed. A primary-side resonant capacitor connected to the part, a capacitance of a partial resonant capacitor connected in parallel to at least one of the switching elements forming the switching means, and a primary winding of the insulating converter transformer A primary side partial voltage resonance circuit which is formed by a leakage inductance component of the line and performs a partial voltage resonance operation during a turn-off period of the switching element forming the switching means, and is induced in the secondary winding of the insulating converter transformer Full-wave rectification of alternating voltage By charging the rectification current on the secondary side smoothing capacitor, so that and a synchronous rectification circuit adapted to obtain a secondary side DC output voltage as a voltage across the secondary side smoothing capacitor.
In such a configuration, first, the magnetic flux density of the insulating converter transformer is changed to a value that flows into the synchronous rectifier circuit by the full-wave rectification operation regardless of fluctuations in the load condition connected to the secondary side DC voltage. The secondary side rectified current is set to be a predetermined mode or less so as to be in a continuous mode.
Furthermore, as the synchronous rectifier circuit, the tap output obtained by center tapping the secondary winding of the insulating converter transformer is connected to the positive terminal of the smoothing capacitor,
A first field effect transistor connected in series between one end of the secondary winding on the non-center-tap side and the secondary side ground; and a side of the secondary winding that is not center-tapped And a second field effect transistor connected in series between the other end of the first electrode and the secondary side ground.
A gate voltage for turning on the first field-effect transistor by detecting a secondary winding voltage corresponding to a half-wave period in which the first field-effect transistor should pass a rectified current with a resistance element And a second winding voltage corresponding to a half-wave period in which the second field-effect transistor is to pass a rectified current, is detected by a resistance element, and the second field-effect transistor detects the second winding voltage. And a second driving circuit configured to output a gate voltage for turning on the field effect transistor.
In addition, between one end of the secondary winding on the non-center-tap side and the first field effect transistor, and the other end on the non-center-tap side of the secondary winding. And an inductor element having a required inductance inserted in series between the first field effect transistor and the second field effect transistor.

In the switching power supply circuit having the above configuration, the primary side switching converter is configured as a complex resonance type converter in which a partial voltage resonance circuit is combined with the resonance type converter, and the secondary side has a winding voltage detection system. A full-wave rectification synchronous rectification circuit is provided.
The magnetic flux density of the insulating converter transformer is set to be equal to or lower than a predetermined value, so that the secondary side rectified current is always in the continuous mode regardless of the load fluctuation. If the secondary side rectified current is in the continuous mode, reactive power due to the occurrence of reverse current in the rectified current during the discontinuous period of the secondary side rectified current, which is a problem in the synchronous rectifier circuit based on the winding voltage detection method, is generated. Can be reduced.
In addition, an inductor element having a required inductance is inserted in series between the secondary winding and each field effect transistor as described above. Depending on the inductor element, the reverse current generated in the rectified current is suppressed by the counter electromotive force when the current flows therethrough. That is, this further reduces the reactive power caused by the reverse current flowing.

Therefore, the present invention does not generate reactive power corresponding to the discontinuous period of the secondary side rectified current even though the winding voltage detection type synchronous rectifier circuit is provided. The power conversion efficiency can be improved to the same extent as when a synchronous rectifier circuit is provided. In addition, since the circuit configuration itself of the synchronous rectification circuit is the winding voltage detection method, a simpler configuration than the rectification current detection method can be adopted.
That is, according to the present invention, as a composite resonance type converter including a synchronous rectifier circuit, it is possible to achieve both high power conversion efficiency, reduction in circuit scale by simplification of the circuit, and reduction in cost. In particular, it is advantageous when the power supply circuit is used under such a condition that a low voltage and a large current are used.

  FIG. 1 shows a configuration example of a switching power supply circuit as an embodiment of the present invention. The power supply circuit shown in this figure employs a configuration in which a partial voltage resonance circuit is combined with a current resonance type converter using a half-bridge coupling method by a separate excitation type as a basic configuration on the primary side.

In the power supply circuit shown in this figure, first, a noise filter is formed by filter capacitors CL and CL and a common mode choke coil CMC with respect to the commercial AC power supply AC.
Further, as shown in the figure, a rectifier circuit portion Di composed of rectifier diodes DA and DB and a voltage doubler rectifier circuit composed of two smoothing capacitors Ci1 and Ci2 are provided in the subsequent stage of such a noise filter. Depending on the voltage doubler rectifier circuit, a level rectified smoothed voltage Ei (DC input voltage) corresponding to twice the AC input voltage VAC is generated as the voltage across the smoothing capacitors Ci1 to Ci2.

  As in the power supply circuit shown in this figure, under conditions where the load requires a relatively large current, the level of current flowing through the circuit on the primary side switching converter side also increases. Thereby, switching loss etc. increase and power conversion efficiency falls. Thus, in this way, by using a voltage doubler rectifier circuit for the rectifier circuit system that generates the DC input voltage, the rectified and smoothed voltage Ei at a level corresponding to the AC voltage equal to the AC input voltage VAC is obtained by, for example, normal full-wave rectification. Compared with the case of supplying, the level of the current flowing in the circuit of the primary side switching converter can be reduced to about ½. Thereby, the switching loss by the primary side switching converter is reduced.

  As shown in the figure, the current resonance type converter for switching (intermittently) by inputting the DC input voltage includes a switching circuit in which two switching elements Q1 and Q2 by MOS-FETs are connected by half bridge coupling. Damper diodes DD1 and DD2 are connected in parallel between the drains and sources of the switching elements Q1 and Q2. The anode and cathode of the damper diode DD1 are connected to the source and drain of the switching element Q1, respectively. Similarly, the anode and cathode of the damper diode DD2 are connected to the source and drain of the switching element Q2, respectively. The damper diodes DD1 and DD2 are body diodes provided in the switching elements Q1 and Q2, respectively.

  A partial resonance capacitor Cp is connected in parallel between the drain and source of the switching element Q2. A parallel resonance circuit (partial voltage resonance circuit) is formed by the capacitance of the partial resonance capacitor Cp and the leakage inductance L1 of the primary winding N1. A partial voltage resonance operation in which voltage resonance occurs only when the switching elements Q1, Q2 are turned off is obtained.

  In this power supply circuit, an oscillation / drive circuit 2 is provided to drive the switching elements Q1, Q2 in a switching manner. The oscillation / drive circuit 2 includes an oscillation circuit and a drive circuit, and for example, a general-purpose IC can be used. Then, a drive signal (gate voltage) having a required frequency is applied to the gates of the switching elements Q1 and Q2 by the oscillation circuit and the drive circuit in the oscillation / drive circuit 2. Thereby, the switching elements Q1 and Q2 perform the switching operation so as to be alternately turned on / off at a required switching frequency.

The insulating converter transformer PIT is provided to transmit the switching outputs of the switching elements Q1 and Q2 to the secondary side.
One end of the primary winding N1 of the insulation transformer PIT is connected to a connection point (switching output point) between the source of the switching element Q1 and the drain of the switching element Q2 through a series connection of the primary side parallel resonant capacitor C1. By being connected, a switching output is transmitted.
The other end of the primary winding N1 is connected to the primary side ground.

  Here, the insulating converter transformer PIT generates a required leakage inductance L1 in the primary winding N1 of the insulating converter transformer PIT by a structure described later. Then, depending on the capacitance of the series resonance capacitor C1 and the leakage inductance L1, a primary side series resonance circuit for making the operation of the primary side switching converter the current resonance type is formed.

According to the above description, the primary side switching converter shown in this figure has the operation as the current resonance type by the primary side series resonance circuit (L1-C1) and the part by the partial voltage resonance circuit (Cp // L1) described above. A voltage resonance operation is obtained.
That is, the power supply circuit shown in this figure has a configuration as a complex resonance type converter in which a resonance circuit for making the primary side switching converter a resonance type is combined with another resonance circuit.

An alternating voltage corresponding to the switching output transmitted to the primary winding N1 is excited in the secondary winding of the insulating converter transformer PIT.
In the case of the present embodiment, as shown in the figure, the secondary windings of the insulating converter transformer PIT are the secondary winding N2A and the secondary winding N2B having the same winding direction as the primary winding N1, respectively. Is provided.
These secondary windings N2A and N2B are each divided into two winding portions as shown in the figure by being center-tapped. Here, the winding portion including the winding start end portion of the secondary winding N2A is referred to as a winding portion N2A1, and the winding portion including the winding end end portion is referred to as a winding portion N2A2. The winding portion including the winding start end portion of the secondary winding N2B is the winding portion N2B1, and the winding portion including the winding end end portion is the winding portion N2B2.

In the secondary windings N2A and N2B in this case, the winding portions N2A1, N2A2, N2B1, and N2B2 have the same predetermined number of turns.
The secondary windings N2A and N2B are provided with a full-wave rectification synchronous rectification circuit including N-channel MOS-FETs Q3 and Q4 as rectification elements. For these MOS-FETs Q3 and Q4, for example, a low breakdown voltage trench structure is selected to obtain a low on-resistance.

The center tap outputs of the secondary windings N2A and N2B are connected to the positive terminal of the smoothing capacitor Co.
The winding start ends of the secondary windings N2A and N2B are connected to the secondary side ground (the negative terminal side of the smoothing capacitor Co) via the inductor Ld1 → the drain of the MOS-FET Q3 → the source.
The winding end ends of the secondary windings N2A and N2B are connected to the secondary side ground (the negative terminal side of the smoothing capacitor Co) via the inductor Ld2 → the drain of the MOS-FET Q4 → the source.
Body diodes DD3 and DD4 are connected to the drain and source of the MOS-FETs Q3 and Q4, respectively.

According to such a connection form, the MOS-FET Q3 is inserted in series in the rectified current path including the winding part N2A1 and the winding part N2B1 of the secondary windings N2A and N2B. Further, in the rectified current path including the winding part N2A2 and the winding part N2B2 of the secondary windings N2A and N2B, the MOS-FET Q4 is inserted in series.
At this time, in the rectified current path including the winding part N2A1 and the winding part N2B1, an inductor Ld1 is provided between each winding start end of the secondary windings N2A and N2B and the drain of the MOS-FET Q3. It will be inserted in series. Similarly, in the rectified current path including the winding part N2A2 and the winding part N2B2, an inductor Ld2 is inserted in series between the winding end ends of the secondary windings N2A and N2B and the drain of the MOS-FET Q4. Is done.

A drive circuit for driving the MOS-FET Q3 is formed by connecting a gate resistor Rg1 between the winding end of the secondary winding N2A and the gate of the MOS-FET Q3.
Similarly, a drive circuit for driving the MOS-FET Q4 is formed by connecting a gate resistor Rg2 between the winding start end of the secondary winding N2B and the gate of the MOS-FET Q4.
That is, in this case, the MOS-FET Q3 is turned on by detecting the alternating voltage excited by the winding part N2A2 and the winding part N2B2 by the gate resistance Rg1, respectively. The alternating voltage excited in the part N2A1 and the winding part N2B1 is detected by the gate resistance Rg2 and is rendered conductive.

In the MOS-FET, when an ON voltage is applied to the gate, the drain-source is equivalent to a simple resistor, so that current flows in both directions. If this is to function as a rectifying element on the secondary side, a current must flow only in the direction in which the positive terminal of the smoothing capacitor Co is charged. When a current flows in the opposite direction, a discharge current flows from the smoothing capacitor Co to the insulating converter transformer PIT side, and power cannot be effectively transmitted to the load side. Further, the MOS-FET generates heat and noise due to the reverse current, resulting in switching loss on the primary side.
Based on detecting the voltage of the secondary winding, the drive circuit described above is configured so that only the current in the direction in which the positive terminal of the smoothing capacitor Co is charged (that is, in this case, the source → drain direction) flows. A circuit for switching and driving the FETs Q3 and Q4. That is, the circuit configuration of the synchronous rectifier circuit in this case employs a configuration in which the MOS-FETs Q3 and Q4 are driven on / off in synchronization with the rectified current by the winding voltage detection method.

  In this case, the Schottky diode Dg1 and the Schottky diode Dg2 are connected in parallel to the gate resistors Rg1 and Rg2, respectively, which form the drive circuit system of the MOS-FET Q3 and the MOS-FET Q4. I am doing so. These Schottky diodes Dg1 and Dg2 form a path for discharging the accumulated charges of the gate input capacitances of the MOS-FETs Q3 and Q4 when they are turned off, as will be described later.

In this case, a Zener diode Dz1 and a Zener diode Dz2 are inserted between the gate and source of the MOS-FET Q3 as shown in the figure, and similarly, a Zener diode Dz3 and Zener diode are inserted between the gate and source of the MOS-FET Q4. Although the diode Dz4 is inserted, an overvoltage protection circuit for the MOS-FETs Q3 and Q4 is formed by these Zener diodes.
As such a zener diode Dz, a zener potential (breakdown potential) having a potential corresponding to the withstand voltage level of the MOS-FETs Q3 and Q4 is selected. As a result, as the gate-source potential of the MOS-FETs Q3 and Q4 rises above the withstand voltage level, these Zener diodes Dz are turned on to protect the MOS-FETs Q3 and Q4.
For example, as the Zener diode Dz in this case, one having a Zener potential = ± 20V is selected. Further, for example, the zener diodes Dz1 and Dz2 and the zener diodes Dz3 and Dz4 are provided so as to be built in the MOS-FET Q3 and the MOS-FET Q4, respectively.

Further, as described above, in the power supply circuit shown in FIG. 1, the inductor Ld1 is inserted between the winding start end of the secondary winding N2A and the drain of the MOS-FET Q3. Similarly, an inductor Ld2 is inserted between the winding start end of the secondary winding N2B and the drain of the MOS-FET Q4.
In the present embodiment, as these inductors Ld1 and Ld2, for example, a relatively low inductance of about 0.6 μH is set.

Here, in order to obtain such a low inductance, it is conceivable to use bead cores as shown in FIG. 3 as the inductors Ld1 and Ld2.
That is, as shown in FIG. 3, the lead wire is inserted through a bead core in which a magnetic material such as an amorphous magnetic material or a ferrite material is formed in a cylindrical shape. And the bead core which penetrated the lead wire in this way is mounted on a printed circuit board as one inductor element.

Alternatively, in the present embodiment, in order to obtain low inductance as the inductors Ld1 and Ld2, these inductors Ld1 and Ld2 are formed as shown in FIGS. 4A and 4B, for example. It is supposed to be.
First, FIG. 4A shows another example in which the above-described bead core is used as the inductors Ld1 and Ld2.
In this case, the bead core made of a magnetic material such as an amorphous magnetic material or a ferrite material as described above is inserted through the lead wire as the drain electrode terminal of the MOS-FETs Q3 and Q4 soldered to the printed board as shown in the figure. Provide. And inductor Ld1, Ld2 is formed with the inductance of such a bead core.
If the bead core is directly provided on the lead wire of the drain electrode in this way, it is not necessary to mount the component element as the bead core as shown in FIG. 3 on the substrate, and the space of the substrate can be saved. .

FIG. 4B shows an example in which the wiring pattern of the printed circuit board on which the MOS-FETs Q3 and Q4 are mounted is formed in a spiral shape.
In this case, the copper foil pattern to be wired to the drain electrodes of the MOS-FETs Q3 and Q4 on the printed circuit board is formed in a spiral shape as shown in the figure, and the required inductance as the inductors Ld1 and Ld2 is obtained by this spiral shape. It is what you get.
This has the advantage that the inductor Ld can be formed simultaneously with the manufacture of the printed wiring board.

Returning to FIG.
Depending on the synchronous rectifier circuit having the above-described circuit configuration, an operation of charging the rectified current obtained by rectifying the smoothing capacitor Co by full-wave rectification can be obtained.
That is, in one half cycle of the alternating voltage excited on the secondary side, the current flowing through the winding portions N2A1 and N2B1 is charged to the smoothing capacitor Co, respectively. Further, in the other half cycle of the alternating voltage, the current flowing through the winding portions N2A2 and N2B2 is charged to the smoothing capacitor Co, respectively. As a result, a full-wave rectification operation is obtained in which the smoothing capacitor Co is charged in a period in which the alternating voltage is positive / negative.
The secondary side DC output voltage Eo as shown in the figure is obtained as the voltage across the smoothing capacitor Co. The secondary side DC output voltage Eo is supplied to a load side (not shown) and is also branched and input as a detection voltage for the control circuit 1 described below.

The control circuit 1 supplies a detection output corresponding to the level change of the secondary side DC output voltage Eo to the oscillation / drive circuit 2. The oscillation / drive circuit 2 drives the switching elements Q1 and Q2 such that the switching frequency is varied according to the input detection output of the control circuit 1. By changing the switching frequency of the switching elements Q1 and Q2, the power transmitted from the primary winding N1 to the secondary windings N2A and N2B from the insulating converter transformer PIT changes. It operates so as to stabilize the level of the voltage Eo.
For example, when the secondary side DC output voltage Eo decreases due to a heavy load tendency, the secondary side DC output voltage Eo is increased by controlling the switching frequency to be increased. On the other hand, when the secondary side DC output voltage Eo rises due to the tendency of light load, the secondary side DC output voltage Eo is lowered by controlling the switching frequency to be lowered. Let

  In this embodiment, under the circuit configuration of the power supply circuit shown in this figure, it is made to correspond to the load condition of low voltage and large current. Here, it is assumed that the state of the low voltage and large current is a state where the secondary side DC voltage Eo = 5V and the primary side series resonance current Io = 20 A which is the switching current of the primary side switching converter.

On the premise of such conditions, as the power supply circuit shown in FIG. 1, required parts are configured and selected as follows.
First, the insulating converter transformer PIT has the structure shown in FIG.
As shown in this figure, the insulating converter transformer PIT includes an EE type core in which E type cores CR1 and CR2 made of a ferrite material are combined so that their magnetic legs face each other.
And the bobbin B formed with the shape which divided | segmented so that it might mutually become independent about the winding part of a primary side and a secondary side, for example with a resin etc. is provided. The primary winding N1 is wound around one winding portion of the bobbin B. Further, the secondary winding (N2A, N2B) is wound around the other winding portion. By attaching the bobbin B on which the primary side winding and the secondary side winding are wound in this way to the EE type cores (CR1, CR2), the primary side winding and the secondary side winding are different from each other. By the winding area, the center magnetic leg of the EE core is wound. In this way, the structure of the insulating converter transformer PIT as a whole is obtained. In this case, the size of the EE type core is, for example, EER-35.

  For the central magnetic leg of the EE type core, a gap G having a gap length of about 1.5 mm is formed as shown in the figure. Thereby, as the coupling coefficient k, for example, a loosely coupled state with k = 0.8 or less is obtained. That is, as a conventional example, the state is more loosely coupled than the insulating converter transformer PIT of the power supply circuit shown in FIG. The gap G can be formed by making the central magnetic legs of the E-type cores CR1 and CR2 shorter than the two outer magnetic legs.

  In addition, the number of turns of the primary winding N1 and the secondary windings N2A and N2B so that the induced voltage level per 1T (turn) of the secondary winding is lower than that of the power supply circuit shown in FIG. Set the number of turns. For example, when the primary winding N1 = 80T and the secondary winding N2A = N2B = 6T (winding portion N2A1 = N2A2 = N2B1 = N2B2 = 3T), induction per 1T (turn) of the secondary winding The voltage level is 2 V / T or less.

  By setting the number of turns of the insulating converter transformer PIT, the primary winding N1, and the secondary windings (N2A, N2B), the magnetic flux density in the core of the insulating converter transformer PIT is reduced, as shown in FIG. The leakage inductance in the insulating converter transformer PIT increases compared to the power supply circuit.

  In addition, 0.015 μF was selected for the primary side series resonant capacitor C1. Further, for MOS-FETs Q3 and Q4 forming the secondary side synchronous rectifier circuit, 30 A / 20 V is selected, and the on-resistance is 2.5 mΩ.

  Operation waveforms of the power supply circuit shown in FIG. 1 having such a configuration are shown in FIGS. FIG. 5 shows the operation when the AC input voltage VAC = 100 V and the load power Po = 100 W, and FIG. 6 shows the operation when the AC input voltage VAC = 100 V and the load power Po = 25 W. In the corresponding load power range of the power supply circuit shown in FIG. 1, the load power Po = 100 W is a heavy load condition, and the load power Po = 25 W is a light load condition.

In the waveform diagram shown in FIG. 5, the voltage V1 across the switching element Q2 corresponds to the on / off state of the switching element Q2. In other words, the rectangular wave is clamped at the 0 level during the period T2 when the switching element Q2 is turned on and at the predetermined level during the period T1 when the switching element Q2 is turned off. Then, as shown in the period T2, the switching current IDS2 flowing through the switching element Q2 // damper diode DD2 becomes negative by flowing through the damper diode DD2 at the time of turn-on. A waveform flows from the drain to the source of the element Q2 and is turned off in the period T1 and becomes 0 level.
The switching element Q1 performs switching by alternately turning on / off the switching element Q2. For this reason, the switching current flowing through the switching element Q1 // damper diode DD1 also has a waveform whose phase is shifted by 180 ° with respect to the switching current IDS2, although not shown. The voltage across the switching element Q1 also has a waveform whose phase is shifted by 180 ° with respect to the voltage V1 across the switching element Q2.

  The primary side series resonance current Io flowing through the primary side series resonance circuit (C1-L1) connected between the switching output points of the switching elements Q1, Q2 and the primary side ground is composed of the switching current IDS1 and the switching current IDS2. Will be. Thereby, as shown in the figure, the primary side series resonance current Io is sinusoidal. Comparing this waveform with the waveform of the primary side series resonance current Io of the conventional power supply circuit shown in FIG. 8 (see FIG. 9), the primary side series resonance current Io of the present embodiment is that of the primary winding N1. It can be seen that the sawtooth wave component generated by the excitation inductance is hardly included. This is because the coupling coefficient of the insulating converter transformer PIT is made more loosely coupled, so that the exciting inductance of the primary winding N1 is relatively reduced by the amount of increase in the leakage inductance L1 of the primary winding N1. It depends.

Then, in response to the waveform of the primary side series resonance current Io being obtained, the voltage V2 obtained at the winding portion N2A1 of the secondary winding N2A corresponds to the period of the primary side series resonance current Io. The waveform is a waveform clamped at an absolute value level corresponding to the secondary side DC output voltage Eo.
The voltage V2 is shown as a potential obtained at the winding portion N2A1, but a potential is also generated with an equivalent waveform in the winding portion N2B2 in the secondary winding N2B. In this case, a potential equivalent to the voltage V2 is generated in the winding portion N2A2 and the winding portion N2B2.
Here, as can be seen from comparison with the voltage V2 shown in FIG. 9, the voltage V2 shown in FIG. 5 obtains a waveform that similarly becomes 0 level at the timing when the primary side series resonance current Io becomes 0 level. . That is, as the voltage V2 in this case, the zero cross timing overlaps with the zero cross timing of the primary side series resonance current Io (see time points t1, t2, and t3 in the figure).

Then, in the secondary side synchronous rectifier circuit based on the voltage detection method, the voltage V2 (windings N2A1, N2B1) is detected by the drive circuit composed of the resistor Rg2, and an on-level gate voltage is output to the MOS-FET Q4. To do.
In this case, as shown in the figure, the voltage V2 has a waveform having a positive peak level at a time point t1, and thereafter, the voltage level is lowered and becomes a zero level at a time point t2. The gate-source voltage VGS4 generated between the gate and source of the MOS-FET Q4 is a period during which the voltage V2 is maintained at a level corresponding to a predetermined level determined as the gate-source potential of Q4 (period t1 in the figure). On-td1), an on-voltage is generated. That is, the period t1 to td1 becomes the ON period DON2 of the MOS-FET Q4.
The period from the time td1 to the time t2 when the period DON2 ends is the dead time of the MOS-FET Q4, and the rectified current flows through the body diode DD4 of Q4 during the period td1 to t2 which is the dead time. This is also indicated by the potential of the period td1-t2 in the illustrated gate-source voltage VGS4.
As a result, the rectified current I4 flowing through the MOS-FET Q4 flows over a period of time t1 to t2 as shown in the figure. That is, as the rectified current I4, at the time points t1 and t2, the primary side series resonance current Io is overlapped with the timing when it becomes 0 level, and thus becomes continuous with the primary side series resonance current.

Similarly, the drive circuit composed of the resistor Rg1 detects a voltage generated in the winding portions N2A2 and N2B2 that is equivalent to the voltage V2, and outputs an on-level gate voltage to the MOS-FET Q3. The
That is, in this case, the gate-source voltage VGS3 generated between the gate and the source of the MOS-FET Q3 is equal to or higher than the voltage V2 generated on the windings N2A2 and N2B2 side corresponding to a predetermined level as the gate-source potential. In the period (period t2 to td2 in the figure) during which the ON voltage is generated, this period t2 to td2 becomes the ON period DON1 of the MOS-FET Q3.
Similarly, the dead time of the MOS-FET Q3 is from the time td2 to the time t3 when the period DON1 ends, and a rectified current flows through the body diode DD3 of Q3 during the period td2 to t3.
As a result, the rectified current I3 flowing through the MOS-FET Q3 also flows between the time point t2 and the time point t3, which is the zero cross timing of the primary side series resonance current Io, as shown in the figure, and the primary side series resonance current It will flow continuously with Io.

The charging current Ic to the smoothing capacitor flows according to a waveform as shown in the figure in which these rectified currents I3 and I4 are combined. That is, as the rectification operation, it is understood that a full-wave rectification operation is obtained in which the smoothing capacitor Co is charged in each period in which the voltage generated in the secondary windings N2A and N2B is positive / negative.
As described above, the voltage V2 generated in the secondary winding in this case becomes 0 level as the primary side series resonance current Io becomes 0 level, so that the voltage V2 is continuous with the primary side series resonance current. Will be. Further, since the voltage V2 continues as described above, the rectified current I3 and the rectified current I4 also continue as described above. Therefore, the charging current Ic for the smoothing capacitor Co also flows continuously. .
That is, in this embodiment, even when the load is controlled so as to reduce the switching frequency, the continuous mode is obtained as the secondary side rectified current. In this case, the rectified currents I3 and I4 are 28 Ap, which is lower than, for example, the rectified currents I1 and I2 shown in FIG. This is because, for example, the conduction period of the rectified current is longer than that in the prior art within a period corresponding to an equivalent switching frequency.

  In this way, the continuous mode is obtained even under heavy load conditions. As can be understood from the above description, the coupling coefficient of the insulating converter transformer PIT is reduced to about 0.8 by setting the gap length. The primary winding N1 and the secondary winding N2A (winding section) are made so that the induced voltage level per turn of the secondary winding is lowered to about 2 V / T, for example. N2A1, N2A2) and secondary winding N2B (windings N2B1, N2B2) have been set with the number of turns (turns), thereby reducing the magnetic flux density generated in the core of the insulating converter transformer PIT to below the required level. Is obtained.

Further, in FIG. 5, it can be seen that the rectified currents I3 and I4 in this case are not supplied with reverse currents, as can be seen from the conventional rectified currents I1 and I2 shown in FIG.
That is, in the prior art, a reverse current of 8 Ap flows in the rectified currents I1 and I2, and this causes power loss. Is.
In the present embodiment, such reverse currents are not generated in the rectified currents I3 and I4, as shown in FIG. It depends.
That is, by inserting the inductor in the rectified current path in this way, a counter electromotive force is generated in the inductor when the rectified current flows. As the back electromotive force is generated in this manner, the reverse current that is supposed to be generated when the MOSFETs Q3 and Q4 are turned off is suppressed.
As described above, in the present embodiment, 0.6 μH is set as these inductors Ld1 and Ld2, thereby making it possible to prevent the generation of reverse currents in the rectified currents I3 and I4.

Here, as described above, since the synchronous rectification circuit uses a low on-resistance and low breakdown voltage MOS-FET as a rectifying element, the conduction loss is reduced as compared with the case where a diode element is used as the rectifying element. be able to.
However, when the secondary side rectified current flows in the discontinuous mode and the winding voltage detection method is adopted as the synchronous rectifier circuit, the MOS-FET remains on even when the charging current to the smoothing capacitor Co becomes 0 level. As a result, a reverse current flows, which generates reactive power.
In order to eliminate this reactive power, a rectification current detection type synchronous rectification circuit is employed. However, the rectified current detection method requires a drive circuit system including a current transformer and a comparator, and the circuit configuration is complicated and increases in scale.

On the other hand, in the present embodiment, the secondary side rectification current is set to the continuous mode even under heavy load, so that the current discontinuity period as described above is invalid even in the synchronous rectification circuit based on the voltage detection method. Electric power can be reduced. Further, in this case, as described above, the inductors Ld1 and Ld2 are inserted into the respective rectified current paths on the secondary side, so that the reverse current does not flow in the rectified current, thereby further reducing the reactive power. I am trying.
For this reason, the present embodiment adopts a voltage detection system configuration as a synchronous rectifier circuit, thereby suppressing an increase in circuit scale as a simple circuit configuration, and further avoiding an increase in cost, while still maintaining current. This solves the problem of reduction in power conversion efficiency due to reactive power in the discontinuous period.

In FIG. 5, as the gate-source voltages VGS3 and VGS4, negative potentials of -9V are generated at the timing when the MOS-FETs Q3 and Q4 are turned off, respectively. This is because the Schottky diodes Dg1 and Dg2 are inserted in parallel with the resistors Rg1 and Rg2, respectively, between the gates of the MOS-FETs Q3 and Q4 and the secondary winding as described above.
By inserting the Schottky diodes Dg1 and Dg2 in this way, when the MOS-FETs Q3 and Q4 are turned off, the charges stored in the gate input capacitances (Ciss) of these MOS-FETs Q3 and Q4 are converted into the Schottky diodes Dg1 and Dg2. It can be made to flow through as it is pulled out.
That is, in this case, the charge of the gate input capacitance is discharged through the path of Schottky diode Dg (Dg1, Dg2) → secondary winding N2 → smoothing capacitor Co, respectively. Then, by discharging the charge of the input capacitance in this way, the voltage drop time at the turn-off time in the MOS-FETs Q3 and Q4 can be reduced.
If the voltage drop time when the MOS-FET is turned off can be reduced in this way, these MOS-FETs Q3 and Q4 can be reliably turned off to obtain better switching characteristics.

FIG. 6 shows the operation of the circuit shown in FIG. 1 at light load (when Po = 25 W).
In the power supply circuit shown in FIG. 1, as understood from the above description, constant voltage control by switching frequency control is performed to stabilize the secondary side DC output voltage Eo. This constant voltage control operates to stabilize the secondary DC output voltage by lowering the secondary DC output voltage by increasing the switching frequency when the secondary DC output voltage rises under light load conditions. To do.
In such a light load state, the secondary winding voltage V2 can be obtained at substantially the same timing with respect to the voltage V1 across the switching element Q2 shown in the figure, and the secondary side charging is accordingly performed. The current Ic (rectified currents I3 and I4) also flows so as to be continuously charged in the smoothing capacitor Co without a pause period as shown in the figure.
From this, it can be understood that the power supply circuit shown in FIG. 1 is in a continuous mode even at a light load.

  Next, FIG. 7 shows a comparison between the power supply circuit shown in FIG. 1 having the configuration described so far and the power supply circuit of FIG. DC) characteristics. Here, the characteristic of the power supply circuit in FIG. 1 is indicated by a solid line, and the characteristic of the power supply circuit in FIG. 8 is indicated by a broken line.

According to FIG. 7, the AC → DC power conversion efficiency (ηAC → DC) is higher in the circuit shown in FIG. 1 over the range of load power Po = 0 W to 100 W than the power supply circuit shown in FIG. I understand that. In the circuit shown in FIG. 8, ηAC → DC = 82% when the load power Po = 100 W, whereas in the power supply circuit shown in FIG. 1, ηAC → DC = 90.8% when the load power Po = 100 W. A result of about 8.8% improvement is obtained. Moreover, as AC input power according to this, a result of 10.9 W reduction when the load power Po = 100 W was obtained.
Further, when the load power Po = 25 W, ηAC → DC is improved by about 13%. At this time, the AC input power is reduced by 4.7 W.

Further, in FIG. 7, the AC → DC power conversion efficiency in the case where the inductor Ld (Ld1 = Ld2 = 0.6 μH) is not inserted into each rectified current path is indicated by a one-dot chain line. As can be seen by comparing the characteristic indicated by the alternate long and short dash line with the characteristic of the circuit of FIG. 1 indicated by the solid line, in this case, the load power Po = 0W to 100W is obtained in the case of the circuit of FIG. ΗAC → DC increases over the range of.
Therefore, the reactive power can be further reduced in the present example in which the inductor Ld is inserted rather than the configuration in which the discontinuous mode at the time of heavy load is eliminated by increasing the leakage inductance of the insulating converter transformer PIT. You can see that

The characteristics of the power conversion efficiency shown in FIG. 7 are equivalent to the case where a synchronous rectification circuit of a rectification current detection method is adopted on the secondary side (see FIG. 13) with respect to the primary side configuration shown in FIG. It becomes. That is, as described above, the AC → DC power conversion efficiency when the rectified current detection method of FIG. 13 is adopted is about ηAC → DC = 90%, whereas in this example, ηAC → DC = 90. .8%, almost equivalent AC-to-DC power conversion efficiency.
However, as described above, in the power supply circuit shown in FIG. 1, the circuit configuration can be further simplified by adopting the winding voltage detection method as the configuration of the synchronous rectification circuit. .

The present invention is not limited to the configuration of the power supply circuit described so far.
For example, the detailed configuration of the winding voltage detection type synchronous rectifier circuit according to the present invention may be changed as appropriate. Further, for example, as the switching element of the primary side switching converter, an element other than the MOS-FET may be employed as long as it is an element that can be used in a separate excitation type such as an IGBT (Insulated Gate Bipolar Transistor). Also, the constants of the component elements described above may be changed according to actual conditions.
In addition, the present invention can be configured to include a self-excited current resonance converter. In this case, for example, a bipolar transistor can be selected as the switching element. Furthermore, the present invention can also be applied to a current resonance type converter in which four stone switching elements are full-bridge coupled.
Further, as a rectifier circuit for obtaining a DC input voltage by inputting a commercial AC power supply, for example, a configuration other than a voltage doubler rectifier circuit can be considered.
Furthermore, in the embodiment, the secondary winding of the insulating converter transformer PIT is divided into two parts, and for example, only one secondary winding is provided as shown in FIG. The structure to wear may be taken.
However, at this time, if the number of turns as the secondary winding increases, the DC resistance value generated there increases accordingly. Therefore, according to the present example in which the secondary winding is divided into two as described above, the direct current resistance can be reduced as compared with the case where one secondary winding is provided, thereby reducing the power loss. Can do.

It is a circuit diagram which shows the structural example of the switching power supply circuit as embodiment of this invention. It is a figure which shows the structural example of the insulation converter transformer as embodiment. It is a figure which illustrates the structure of the inductor inserted in the secondary side rectification current path | route in the switching power supply circuit as embodiment. It is a figure which shows another example as a structure of the inductor inserted in the secondary side rectification current path | route in the switching power supply circuit as embodiment. It is a wave form diagram which shows the operation | movement at the time of heavy load of the power supply circuit shown in FIG. It is a wave form diagram which shows the operation | movement at the time of light load of the power supply circuit shown in FIG. It is a figure which shows the characteristic of the switching frequency, the primary side series resonance current level, and AC-> DC power conversion efficiency with respect to the load fluctuation | variation of the power supply circuit shown in FIG. It is a circuit diagram which shows the structure of the power supply circuit as a conventional. It is a wave form diagram which shows the operation | movement at the time of heavy load of the power supply circuit shown in FIG. FIG. 9 is a circuit diagram showing a configuration on the secondary side when a winding voltage detection type synchronous rectifier circuit is provided as the power supply circuit shown in FIG. 8. It is a wave form diagram which shows the operation | movement at the time of heavy load at the time of taking the structure of the secondary side shown in FIG. It is a wave form diagram which shows the operation | movement at the time of light load at the time of taking the structure of the secondary side shown in FIG. It is a circuit diagram which shows the basic structural example of the synchronous rectification circuit by a rectification current detection system. It is a wave form diagram which shows the operation | movement of the synchronous rectifier circuit shown in FIG.

Explanation of symbols

  1. Control circuit, 2. Oscillation / drive circuit, Di bridge rectifier circuit, Ci smoothing capacitor, Q1, Q2 switching element, DD1, DD2 damper diode, C1 primary side series resonance capacitor, Cp partial voltage resonance capacitor, PIT isolation converter transformer, N1 Primary winding, N2A, N2B Secondary winding, N2A1, N2A2, N2B1, N2B2 winding, Q3, Q4 MOS-FET, DD3, DD4 body diode, Rg1, Rg2 gate resistance, Dg1, Dg2 Schottky diode, Co (Secondary side) Smoothing capacitor, Ld1, Ld2 inductor

Claims (6)

Switching means formed with a switching element that performs switching so as to intermittently input DC input voltage;
Driving means for switching and driving the switching element;
The switching output of the switching means is transmitted from the primary side to the secondary side, and an insulating converter transformer around which at least the primary winding and the secondary winding are wound,
At least a predetermined part on the primary side is formed by forming a primary side resonance circuit for making the operation of the switching means resonant by the leakage inductance component of the primary winding of the insulating converter transformer and its own capacitance. A primary resonant capacitor connected to
Of the switching elements forming the switching means, the switching means is formed by a capacitance of a partial resonance capacitor connected in parallel to at least one switching element and a leakage inductance component of a primary winding of the insulating converter transformer, A primary side partial voltage resonance circuit that performs a partial voltage resonance operation during a turn-off period of the switching element forming
Full-wave rectification of the alternating voltage induced in the secondary winding of the insulating converter transformer and charging the secondary side smoothing capacitor with the rectified current, the secondary side DC output as the voltage across the secondary side smoothing capacitor A synchronous rectifier circuit adapted to obtain a voltage, and
The magnetic flux density of the isolation converter transformer is such that the secondary side rectified current flowing in the synchronous rectifier circuit is in a continuous mode by the full-wave rectification operation regardless of fluctuations in the load condition connected to the secondary side DC voltage. Is set to be below a predetermined level,
The synchronous rectifier circuit is
While connecting the tap output obtained by center tapping the secondary winding of the insulating converter transformer to the positive terminal of the smoothing capacitor,
A first field effect transistor connected in series between one end of the secondary winding that is not center-tapped and a secondary side ground;
A second field effect transistor connected in series between the other end of the secondary winding that is not center-tapped and the secondary side ground;
A secondary winding voltage corresponding to a half-wave period in which the first field effect transistor should pass a rectified current is detected by a resistance element, and a gate voltage for turning on the first field effect transistor is output. A first drive circuit adapted to:
A secondary winding voltage corresponding to a half-wave period in which the second field effect transistor should pass a rectified current is detected by a resistance element, and a gate voltage for turning on the second field effect transistor is output. A second drive circuit adapted to:
Further, between one end of the secondary winding that is not center-tapped and the first field effect transistor, and the other end of the secondary winding that is not center-tapped Inductor elements with required inductances inserted in series with the second field effect transistor, respectively,
A switching power supply circuit. In order to set the magnetic flux density of the insulating converter transformer below a certain value, the coupling coefficient between the primary side and the secondary side is set below a predetermined value by setting the gap length formed in the insulating converter transformer to a predetermined value or more.
The switching power supply circuit according to claim 1. In order to keep the magnetic flux density of the insulating converter transformer below a certain level, the number of turns of the primary winding and the secondary winding so that the induced voltage level per turn in the secondary winding is below the required level. Is set,
The switching power supply circuit according to claim 1. A constant voltage control means adapted to perform constant voltage control on the secondary side DC output voltage by variably controlling the switching frequency of the switching means according to the level of the secondary side DC output voltage. Prepare
The switching power supply circuit according to claim 1. The inductor element is formed of a cylindrical magnetic body that passes through the lead wire of the drain electrode of the first and second field effect transistors.
The switching power supply circuit according to claim 1. The inductor element is formed by spiraling the wiring pattern on the printed wiring board.
The switching power supply circuit according to claim 1.

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