JP2005071203A - Microprocessor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology capable of reducing malfunction of a microprocessor. <P>SOLUTION: Peripheral I/Os 30 and 31 operate on the basis of a peripheral clock PCLK outputted from a clock generation part 5. A CPU 1 notifies the clock generation part 5 of a change request to a frequency of the peripheral clock PCLK, and the clock generation part 5 changes a frequency of the peripheral clock PCLK on the basis of the change request. An interruption generation part 4 notifies the CPU 1 of an interruption request when the change of frequency of the peripheral clock PCLK in the clock generation part 5 is completed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a microprocessor.

  Conventionally, there has been proposed a microprocessor that incorporates peripheral I / O such as a timer and a serial I / O port and can change the frequency of a clock supplied to the peripheral I / O. A technique relating to a microprocessor is disclosed in Patent Document 1.

JP-A-8-249082

  In the conventional microprocessor, when the frequency of the clock supplied to the peripheral I / O is changed, there is a time difference from when the CPU requests the change of the frequency to when it is actually changed. Therefore, the peripheral I / O may be operated before the frequency is switched, which may cause the microprocessor to malfunction. In addition, since the frequency of the clock supplied to the peripheral I / O is variable, a clock having a frequency outside the operation specifications of the peripheral I / O is input to the peripheral I / O due to a defect in the execution program of the CPU. The frequency of the clock supplied to the peripheral I / O may be changed during the operation of the peripheral I / O, which may cause the microprocessor to malfunction.

  Accordingly, the present invention has been made in view of the above-described problems, and an object thereof is to provide a technique capable of reducing malfunction of a microprocessor.

  A first microprocessor according to the present invention includes a CPU having an interrupt function, a clock generation unit that outputs a clock with variable frequency, a peripheral I / O that operates based on the clock and is accessed from the CPU, An interrupt generator, wherein the clock generator changes the frequency of the clock based on a change request from the CPU, and the interrupt generator completes the change of the clock frequency in the clock generator Then, an interrupt request is notified to the CPU.

  According to a second microprocessor of the present invention, a CPU, a clock generation unit that outputs a clock with variable frequency, an operation based on the clock, and an acknowledgment signal for an access request from the CPU are sent to the CPU. The CPU includes a peripheral I / O for outputting and a clock change completion determination unit, and the CPU receives the confirmation response signal from the peripheral I / O when the access request is notified to the peripheral I / O. The following operation is performed later, the clock generation unit changes the frequency of the clock based on a change request from the CPU, and the clock change completion determination unit changes the frequency of the clock in the clock generation unit A busy signal indicating the inside and a completion signal indicating the completion of the change of the frequency of the clock in the clock generation unit are output to the peripheral I / O. Peripheral I / O, when the busy signal is the access request from the CPU in a state that is entered, after the input of the completion signal, and outputs the acknowledgment signal.

  The third microprocessor of the present invention includes a CPU, a clock generation unit that outputs a clock with variable frequency, a peripheral I / O that operates based on the clock, and the peripheral I / O of the clock. A clock supply control unit that controls supply of the clock, the clock generation unit changes the frequency of the clock based on a change request from the CPU, and the clock supply control unit is configured to change the clock in the clock generation unit. Detection circuit for detecting whether or not the frequency to be changed coincides with a predetermined frequency, and detecting whether or not to supply the clock to the peripheral I / O based on the detection result of the detection circuit Based on the result, it is controlled whether or not the clock is supplied to the peripheral I / O.

  The fourth microprocessor of the present invention includes a CPU, a clock generation unit that outputs a clock with variable frequency, a peripheral I / O that operates based on the clock, and the peripheral I / O from the CPU. An access control unit that controls access to the clock, wherein the clock generation unit changes the frequency of the clock based on a change request from the CPU, and the access control unit changes the clock in the clock generation unit It has a detection circuit for detecting whether or not the previous frequency matches a predetermined frequency, and controls whether to permit access to the peripheral I / O from the CPU based on the detection result of the detection circuit. .

  The fifth microprocessor of the present invention includes a clock generation unit that outputs a clock with a variable frequency, a peripheral I / O that operates based on the clock, and a change request for the frequency of the clock. And a clock change control unit that controls whether or not to permit notification of the change request to the clock generation unit, and the clock change control unit includes the peripheral I / O in the control. When O is not operating, the notification of the change request to the clock generation unit is permitted. When the peripheral I / O is operating, the notification of the change request to the clock generation unit is not permitted. The clock generation unit changes the frequency of the clock based on the change request.

  According to a sixth aspect of the present invention, there is provided a clock generation unit that outputs a clock with variable frequency, a peripheral I / O that operates based on the clock, a change request for the frequency of the clock, A CPU that outputs first information indicating a frequency change destination to the clock generation unit; and a clock change control unit that controls whether or not to permit notification of the change request to the clock generation unit. The clock change control unit includes a detection circuit that detects whether or not a frequency indicated by the first information matches a predetermined frequency, and the change to the clock generation unit is performed based on a detection result of the detection circuit. Whether or not to permit notification of the request is controlled, and the clock generation unit changes the frequency of the clock based on the first information and the change request.

  According to the first microprocessor of the present invention, an interrupt request is notified to the CPU after the frequency of the clock input to the peripheral I / O is changed. Thereby, the CPU can recognize that the change of the clock frequency in the clock generation unit has been completed. Accordingly, by accessing the peripheral I / O after the CPU receives the interrupt request from the interrupt generation unit, the CPU can be prevented from accessing the peripheral I / O before the clock frequency is changed. As a result, malfunction of the microprocessor can be prevented.

  According to the second microprocessor of the present invention, when an access request from the CPU is notified during the change of the clock frequency in the clock generation unit, the peripheral I / O is changed after the change of the clock frequency is completed. O outputs an acknowledgment signal to the CPU. Therefore, it is possible to prevent the CPU from accessing the peripheral I / O again while changing the clock frequency. As a result, it is possible to reduce the peripheral I / O from operating when the clock frequency is not changed. As a result, malfunction of the microprocessor can be reduced.

  Further, according to the third microprocessor of the present invention, by adopting an inappropriate frequency for the peripheral I / O, for example, a frequency outside the operation specifications of the peripheral I / O, as the predetermined frequency in the detection circuit, Even if the frequency of the clock is changed to an inappropriate frequency due to a defect in the execution program of the CPU, a clock having the inappropriate frequency is not input to the peripheral I / O. Therefore, malfunctions of peripheral I / O can be reduced, and malfunctions of the microprocessor can be reduced.

  Further, according to the fourth microprocessor of the present invention, by adopting an inappropriate frequency for the peripheral I / O, for example, a frequency outside the operation specifications of the peripheral I / O, as the predetermined frequency in the detection circuit, Even if the CPU tries to access the peripheral I / O in a state where a clock having an inappropriate frequency is input due to a defect in the execution program of the CPU, it can be prevented from being actually accessed. As a result, since the peripheral I / O to which the clock having an inappropriate frequency is input is not operated, the malfunction of the microprocessor can be reduced.

  Further, according to the fifth microprocessor of the present invention, a change request for the clock frequency is not notified to the clock generation unit during the operation of the peripheral I / O. Therefore, the clock frequency is not changed during the operation of the peripheral I / O. Therefore, malfunctions of peripheral I / O can be reduced, and malfunctions of the microprocessor can be reduced.

  Further, according to the sixth microprocessor of the present invention, by adopting an inappropriate frequency for the peripheral I / O, for example, a frequency outside the operation specifications of the peripheral I / O, as the predetermined frequency in the detection circuit, Even if the CPU tries to change the clock frequency to an inappropriate frequency due to a defect in the execution program of the CPU, the change request is not notified to the clock generation unit. Therefore, the clock frequency is not changed to an inappropriate frequency. As a result, malfunctions of peripheral I / O can be reduced, and malfunctions of the microprocessor can be reduced.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of a microprocessor 100 according to Embodiment 1 of the present invention. As shown in FIG. 1, the microprocessor 100 according to the first embodiment includes a CPU 1 having an interrupt function, an address decoder 2, a peripheral I / O unit 3, an interrupt generation unit 4, and a clock generation unit 5. And.

  The CPU 1 operates based on the CPU clock CCLK output from the clock generation unit 5 and controls the operations of the peripheral I / O unit 3 and the clock generation unit 5. The CPU 1 outputs an I / O access request signal AREQ and a write enable signal WEN to the address decoder 2 and the clock generation unit 5, respectively. The write valid signal WEN is a high level signal.

  The peripheral I / O unit 3 includes peripheral I / Os 30 and 31, and each peripheral I / O 30 and 31 operates based on the peripheral clock PCLK output from the clock generation unit 5. The peripheral I / Os 30 and 31 are, for example, serial I / O ports, parallel I / O ports, timers, and the like, and have control register groups 30a and 31a, respectively. The control register groups 30a and 31a are composed of a plurality of registers, and the operation of the peripheral I / Os 30 and 31 is controlled by the CPU 1 writing data into the registers.

  For example, when the peripheral I / O 30 is a timer, the peripheral I / O 30 counts the peripheral clock PCLK from the clock generation unit 5 and performs a timer operation. The control register group 30a at this time includes a register for instructing start or stop of a timer operation, a register for setting a count time, and the like. For example, when the peripheral I / O 31 is an asynchronous serial I / O port, the peripheral I / O 31 uses the peripheral clock PCLK from the clock generation unit 5 as a sampling clock at the time of data reception or based on the peripheral clock PCLK. To determine the communication speed. The control register group 31a at this time includes a register for starting transmission and allowing reception, a register for setting a communication speed, and the like.

  The clock generation unit 5 includes a clock selection circuit 50, a D flip-flop (hereinafter referred to as “D-FF”) 51, and a register 52, and outputs the peripheral clock PCLK and the CPU clock CCLK in a variable frequency. The register 52 is written with data by the CPU 1 and outputs the written data as data FDATA0. The D-FF 51 takes in the data FDATA0 in synchronization with the rising edge of the clock DCLK output from the clock selection circuit 50, and outputs it as data FDATA1.

  FIG. 2 is a block diagram showing the configuration of the clock selection circuit 50. As shown in FIG. 2, the clock selection circuit 50 includes selectors 50a and 50b, multipliers 50c to 50e, and frequency dividers 50f to 50h. A system clock SCLK is input from the outside of the microprocessor 100 to each of the multipliers 50c to 50e. The multiplier 50c quadruples the frequency of the system clock SCLK and outputs it to the selector 50a, and the multiplier 50d doubles the frequency of the system clock SCLK and outputs it to the selector 50a. The multiplier 50e increases the frequency of the system clock SCLK by 1, that is, outputs the system clock SCLK to the selector 50a as it is.

  The data FDATA1 includes a multiplication ratio selection signal SELA that indicates a multiplication ratio in the clock selection circuit 50 and a division ratio selection signal SELB that indicates a division ratio in the clock selection circuit 50. The selector 50a includes a multiplication ratio selection signal. Based on SELA, one of the input clocks is selected and output. Specifically, when the multiplication ratio selection signal SELA indicates the multiplication ratio “4”, the output of the multiplier 50 c is selected, and when the multiplication ratio “2” is indicated, the output of the multiplier 50 d is selected. When the ratio “1” is indicated, the output of the multiplier 50e is selected. Thus, the multiplication ratio in the clock selection circuit 50 is determined by the clock selected by the selector 50a.

  The frequency divider 50f outputs the clock output from the selector 50a to the selector 50b as it is. The frequency divider 50g halves the frequency of the clock output from the selector 50a and outputs it to the selector 50b. The frequency divider 50h increases the frequency of the clock output from the selector 50a to ¼ times and selects it. Output to 50b. The selector 50b selects any one of the input clocks based on the frequency division ratio selection signal SELB included in the data FDATA1, and outputs the selected clock as the peripheral clock PCLK. Specifically, when the frequency division ratio selection signal SELB indicates the frequency division ratio “1”, the output of the frequency divider 50f is selected, and when the frequency division ratio “1/2” indicates the frequency divider 50g. When the frequency division ratio “1/4” is indicated, the output of the frequency divider 50h is selected. Thus, the frequency division ratio in the clock selection circuit 50 is determined by the clock selected by the selector 50b.

  The frequency divider 50f outputs the clock output from the selector 50a as it is as the CPU clock CCLK, and the frequency divider 50h increases the frequency of the clock output from the selector 50a by a factor of 1/4 and outputs it as the clock DCLK. .

  Since the clock generation unit 5 is configured as described above, the multiplication ratio or the division ratio in the clock selection circuit 50 can be changed by changing the data set in the register 52 by the CPU 1, thereby generating the clock. The frequencies of the CPU clock CCLK, the peripheral clock PCLK, and the clock DCLK output from the unit 5 can be changed. The frequency of the peripheral clock PCLK is obtained by multiplying the frequency of the system clock SCLK by the multiplication ratio and the frequency division ratio in the clock selection circuit 50. The frequency of the CPU clock CCLK is selected by the system clock SCLK. The multiplication ratio in the circuit 50 is multiplied. The frequency of the clock DCLK is obtained by multiplying the frequency of the system clock SCLK by 1/4, which is the least common multiple of the division ratios that can be set by the clock selection circuit 50.

  The interrupt generation unit 4 includes comparators 40 and 41, an interrupt generation circuit 42, and D-FFs 43 and 44. The comparator 40 compares the data FDATA 0 and 1 with each other, and outputs a High level signal if they match, and a Low level signal if they do not match. The D-FF 44 takes in and outputs the output of the comparator 40 in synchronization with the rising edge of the clock DCLK. The D-FF 43 takes in and outputs the output of the D-FF 44 in synchronization with the rising edge of the clock DCLK. The comparator 41 compares the outputs of the D-FFs 43 and 44 with each other, and outputs a high level signal to the interrupt generation circuit 42 if they match, and a low level signal to the interrupt generation circuit 42 if they do not match. The interrupt generation circuit 42 outputs an interrupt request signal IREQ to the CPU 1 when the output level of the comparator 41 changes. When the CPU 1 receives the interrupt request signal IREQ, it performs an interrupt process.

  The address decoder 2 outputs I / O selection signals PSEL0 and PSEL1 to the peripheral I / O unit 3, and when receiving the I / O access request signal AREQ from the CPU 1, reads the value of the address bus ABUS at that time. . Based on the read address value, one of the I / O selection signals PSEL0 and PSEL1 is set to a high level. Specifically, when the read address value indicates the address of the peripheral I / O 30, the I / O selection signals PSEL 0 and 1 are set to the high level and the low level, respectively, to indicate the address of the peripheral I / O 31. In this case, the I / O selection signals PSEL0 and PSEL1 are set to Low level and High level, respectively.

  An I / O selection signal PSEL0 is input to the peripheral I / 30, and an acknowledgment signal (hereinafter referred to as “acknowledgment signal ACK0”) is output when the signal changes from Low level to High level. The peripheral I / O 31 receives an I / O selection signal PSEL1, and outputs a confirmation response signal (hereinafter referred to as “confirmation response signal ACK1”) when the signal changes from a low level to a high level. Acknowledgment signals ACK0 and 1 output from the peripheral I / Os 30 and 31, respectively, are output to the CPU 1 as confirmation signals ACK.

  As described above, when either one of the I / O selection signals PSEL0 and PSEL1 becomes High level, the peripheral I / O unit 3 outputs the confirmation response signal ACK, which is input to the CPU1.

  Next, the operation of the microprocessor 100 when setting data in the control register groups 30a and 31a of the peripheral I / O unit 3 will be described. Here, the operation when data is set in the control register group 30a of the peripheral I / O 30 will be typically described.

  When setting predetermined data in a register in the control register group 30a built in the peripheral I / O 30, the CPU 1 outputs an I / O access request signal AREQ to the address decoder 2 and performs setting. The register address is output to the address bus ABUS. At the same time, the set data is output to the data bus DBUS. When the address decoder 2 receives the I / O access request signal AREQ, the address decoder 2 reads the value of the address bus ABUS and sets the I / O selection signal PSEL0 to the high level. As described above, when the I / O selection signal PSEL0 becomes High level, the access request from the CPU 1 is notified to the peripheral I / O 30.

  When the I / O selection signal PSEL0 becomes High level, the peripheral I / O 30 outputs the confirmation response signal ACK0 for the access request from the CPU1, and this is input to the CPU1 as the confirmation response signal ACK. At the same time, the value of the address bus ABUS is read, and the data of the data bus DBUS is written into the register indicated by the value.

  As described above, data is set in the control register group 30a of the peripheral I / O 30. When the CPU 1 receives the confirmation response signal ACK, the CPU 1 determines that access to the peripheral I / O 30 has been accepted, and starts the next operation.

  Next, the operation of the microprocessor 100 when changing the frequency of the peripheral clock PCLK output from the clock generator 5 will be described. FIG. 3 is a timing chart showing the operation of the microprocessor 100 at this time. In the first embodiment, as an example, a case will be described in which the multiplication ratio in the clock selection circuit 50 is constant, and the frequency of the peripheral clock PCLK is changed by changing the division ratio there. Specifically, the frequency division ratio in the clock selection circuit 50 is changed from “1” to “1/2” to change the frequency of the peripheral clock PCLK once, and then the frequency division ratio is changed from “1/2” to “1/2”. The operation of the microprocessor 100 when changing to 1/4 "and changing the frequency of the peripheral clock PCLK again will be described. In the following description, the multiplication ratio in the clock selection circuit 50 is always “1”, and the selector 50a always selects the output of the multiplier 50e.

  At time t1 shown in FIG. 3, the CPU 1 outputs a write enable signal WEN to the register 52 to notify the clock generation unit 5 of a change request for the frequency of the peripheral clock PCLK (hereinafter referred to as “change request CR”). . At the same time, the CPU 1 outputs data including information indicating the frequency change destination (hereinafter referred to as “change destination information VI”) to the data bus DBUS. This data is called “change data VD”.

  The change data VD includes, as the change destination information VI, the value of the frequency division ratio set in the clock selection circuit 50, here the value “1/2”, and the value of the multiplication ratio set in the clock selection circuit 50. ing. As described above, in the first embodiment, since the multiplication ratio is not changed when changing the frequency of the peripheral clock PCLK, the value of the multiplication ratio included in the change data VD is “1”.

  When the register 52 receives the write enable signal WEN, the register 52 writes the change data VD to itself via the data bus DBUS. Then, the written change data VD is output as data FDATA0. In this way, as shown in FIG. 3, at time t1, the value of the frequency division ratio set in the register 52 changes from “1” to “1/2”, and the value of the data FDATA0 changes. . Note that “× 1”, “× 1/2”, and “× 1/4” shown in the column indicating the data set in the register 52 or the output data of the D-FF 51 in FIG. This means the value of the frequency division ratio included in the data.

  At time t1, the D-FF 51 holds the previous value of the data FDATA0. Therefore, when the value of the data FDATA0 changes, the data FDATA0 and 1 do not match each other, and at time t1, the output of the comparator 40 is High. Transition from level to low level. After that, when the clock DCLK rises at time t2, the D-FF 51 captures and outputs the changed data FDATA0, so that the change data VD set in the register 52 at time t1 is supplied to the clock selection circuit 50 as data FDATA1. Entered. Of the change data VD, data indicating the division ratio is input to the selector 50b as the division ratio selection signal SELB, and data indicating the multiplication ratio is input to the selector 50a as the multiplication ratio selection signal SELA. Since the frequency division ratio selection signal SELB at this time indicates the frequency division ratio “1/2”, the selector 50b selects and outputs the output of the frequency divider 50g. As a result, as shown in FIG. 3, at time t2, the frequency of the peripheral clock PCLK is changed from 1 to 1/2 the frequency of the system clock SCLK.

  As described above, in the clock generation unit 5 according to the first embodiment, the frequency of the peripheral clock PCLK is changed at the rising timing of the clock DCLK. The output of the frequency divider 50h that divides the output of the selector 50a by the division ratio of the least common multiple of the division ratio that can be set by the clock selection circuit 50 is employed as the clock DCLK. This is to prevent a clock with an abnormal duty from being input to the peripheral I / O unit 3 when the frequency of the peripheral clock PCLK is changed.

  When the data FDATA1 changes at time t2, the data FDATA0 and 1 become coincident with each other, and the output of the comparator 40 transitions from the Low level to the High level. At the same time, the output of the D-FF 44 transitions from a high level to a low level. At this time, since the output of the D-FF 43 is at the high level, the output of the comparator 41 transitions from the high level to the low level. When the output level of the comparator 41 changes, the interrupt generation circuit 42 outputs an interrupt request signal IREQ to the CPU 1, and the CPU 1 performs an interrupt process.

  Here, as shown in FIG. 3, the output of the comparator 41 changes at substantially the same timing as the timing at which the frequency of the peripheral clock PCLK is changed. The interrupt generation circuit 42 detects a change in the output level of the comparator 41 and outputs an interrupt request signal IREQ. Therefore, the CPU 1 receives an interrupt request after the change of the frequency of the peripheral clock PCLK is completed.

  As described above, the interrupt generation unit 4 according to the first embodiment detects completion of the frequency change of the peripheral clock PCLK in the clock generation unit 5 and notifies the CPU 1 of the interrupt request.

  The CPU 1 recognizes that the frequency of the peripheral clock PCLK has been changed by receiving an interrupt request from the interrupt generation unit 4, and then accesses the peripheral I / O 30 and the peripheral I / O 31 to operate them. .

  Next, at time t <b> 11 shown in FIG. 3, the CPU 1 outputs the write enable signal WEN to the register 52 again. At the same time, the CPU 1 outputs change data VD including new change destination information VI to the data bus DBUS. The change data VD at this time includes a division ratio value “1/4” and a multiplication ratio value “1” as the change destination information VI.

  Upon receiving the write enable signal WEN, the register 52 writes the change data VD to itself via the data bus DBUS, and outputs the written change data VD as data FDATA0. In this way, as shown in FIG. 3, at time t11, the value of the frequency division ratio set in the register 52 changes from “1/2” to “1/4”, and the value of the data FDATA0 is changed. Change.

  At time t11, since the D-FF 51 holds the previous value of the data FDATA0, the output of the comparator 40 transitions from the high level to the low level, similarly to the time t1. After that, when the clock DCLK rises at time t12, the D-FF 51 captures and outputs the changed data FDATA0, so that the change data VD set in the register 52 at time t11 is sent to the clock selection circuit 50 as data FDATA1. Is entered as Of the change data VD, data indicating the division ratio is input to the selector 50b as the division ratio selection signal SELB, and data indicating the multiplication ratio is input to the selector 50a as the multiplication ratio selection signal SELA. Since the frequency division ratio selection signal SELB at this time indicates the frequency division ratio “1/4”, the selector 50b selects and outputs the output of the frequency divider 50h. As a result, as shown in FIG. 3, at time t12, the frequency of the peripheral clock PCLK is changed from 1/2 to 1/4 of the frequency of the system clock SCLK.

  Further, when the data FDATA1 changes at time t12, the data FDATA0, 1 coincide with each other, and the output of the comparator 40 transitions from the Low level to the High level.

  Immediately before time t12, the output of the comparator 40 is at the low level. Therefore, at time t12, the output of the D-FF 44 does not change and the low level is maintained. Since the output of the D-FF 44 is at the low level immediately before time t12, the output of the D-FF 43 transitions from the high level to the low level at time t12. As a result, at the time t12, the outputs of the D-FFs 43 and 44 coincide with each other, and the output of the comparator 41 transits from the Low level to the High level.

  When the output level of the comparator 41 changes, the interrupt generation circuit 42 outputs an interrupt request signal IREQ to the CPU 1. As described above, the output of the comparator 41 changes at almost the same timing as the frequency of the peripheral clock PCLK is changed, and the interrupt generation circuit 42 detects a change in the output level of the comparator 41 and detects an interrupt request signal. In order to output IREQ, the CPU 1 receives an interrupt request after the change of the frequency of the peripheral clock PCLK is completed.

  Thereafter, the CPU 1 accesses the peripheral I / O 30 and the peripheral I / O 31 of the peripheral I / O unit 3 and operates them.

  As described above, in the microprocessor 100 according to the first embodiment, the clock generation unit 5 changes the frequency of the peripheral clock PCLK based on the change request CR and the change destination information VI notified from the CPU 1. Since the clock generation unit 5 changes the frequency of the peripheral clock PCLK at the rising timing of the clock DCLK, the frequency of the peripheral clock PCLK is actually changed from the notification of the change request CR of the CPU 1 to the clock generation unit 5. A time difference is caused. Therefore, if the CPU 1 accesses the peripheral I / O 30, 31 immediately after outputting the change request CR, the frequency of the peripheral clock PCLK is not changed, and the peripheral I / O 30, 31 may malfunction.

  For example, when the peripheral I / O 30 is a serial I / O port, predetermined data is set in the control register group 31a before the frequency of the peripheral clock PCLK is changed, and the serial I / O port performs a communication operation. If this is done, the desired communication speed cannot be realized. Further, when the peripheral I / O 30 is a timer, predetermined data is set in the control register group 31a before the frequency of the peripheral clock PCLK is changed, and when the timer performs a timer operation, a desired time is measured. become unable.

  However, in the first embodiment, since the interrupt generation unit 4 notifies the CPU 1 of an interrupt request after the frequency of the peripheral clock PCLK is actually changed, the CPU 1 transmits the peripheral clock PCLK in the clock generation unit 5. It can be recognized that the change of the frequency has been completed. Therefore, after the CPU 1 receives the interrupt request from the interrupt generation unit 4, the CPU 1 accesses the peripheral I / O 30, 31 before the frequency of the peripheral clock PCLK is changed by accessing the peripheral I / O 30, 31. This can be prevented. As a result, malfunctions of the peripheral I / Os 30 and 31 can be reduced, and malfunctions of the microprocessor 100 can be reduced.

Embodiment 2. FIG.
FIG. 4 is a block diagram showing a configuration of the microprocessor 200 according to the second embodiment of the present invention. The microprocessor 200 according to the second embodiment includes the clock change completion determination unit 6 instead of the interrupt generation unit 4 in the configuration of the microprocessor 100 according to the first embodiment.

  The clock change completion determination unit 6 includes the comparator 40 described above. The comparator 40 compares the data FDATA 0 and 1 with each other, and if they match, the comparator 40 outputs a completion signal FNS that is a high level signal, and if they do not match, the comparator 40 receives a busy signal BSY that is a low level signal. 3 is output.

  A completion signal FNS and a busy signal BSY are input to the peripheral I / Os 30 and 31, respectively. If the peripheral I / O 30 receives an access request from the CPU 1 while the busy signal BSY is input, that is, when the output of the clock change completion determination unit 6 is at the low level, the I / O selection signal PSEL0 is at the high level. Then, the writing of data to the control register group 30a and the output of the acknowledgment signal ACK0 are suspended. Then, when the output of the comparator 40 is switched from the busy signal BSY to the completion signal FNS and the completion signal FNS is input to the peripheral I / O 30, the peripheral I / O 30 receives data from the reserved control register group 30a. Perform writing. At the same time, the peripheral I / O 30 outputs an acknowledgment signal ACK0 to the CPU 1, and this signal is input to the CPU 1 as the acknowledgment signal ACK.

  Similarly, when the peripheral I / O 31 receives an access request from the CPU 1 while the busy signal BSY is input, that is, when the output of the clock change completion determination unit 6 is at the low level, the I / O selection signal PSEL1 is When it becomes High level, the writing of data to the control register group 31a and the output of the acknowledgment signal ACK1 are suspended. When the output of the comparator 40 is switched from the busy signal BSY to the completion signal FNS and the completion signal FNS is input to the peripheral I / O 31, the peripheral I / O 31 receives data from the reserved control register group 31a. Perform writing. At the same time, the peripheral I / O 31 outputs an acknowledgment signal ACK1 to the CPU 1, and this signal is input to the CPU 1 as the acknowledgment signal ACK.

  When the CPU 1 receives the confirmation response signal ACK, the CPU 1 recognizes that the access to the peripheral I / Os 30 and 31 has been accepted, and starts the next operation. Since other configurations and operations are the same as those of the microprocessor 100 according to the first embodiment, description thereof is omitted.

  As described with reference to FIG. 3 in the first embodiment, when the frequency of the peripheral clock PCLK is changed, the write enable signal WEN is input from the CPU 1 to the register 52 and the change data VD is set in the register 52. Is done. When the change data VD is set in the register 52, the output of the comparator 40 changes from the High level to the Low level, and the comparator 40 outputs the busy signal BSY. The comparator 40 switches from the busy signal BSY output to the completion signal FNS output at the subsequent rising timing of the clock DCLK. Further, the frequency of the peripheral clock PCLK is changed at the timing when the busy signal BSY output is switched to the completion signal FNS output.

  Thus, since the busy signal BSY is output from the comparator 40 until the frequency of the peripheral clock PCLK is actually changed after the CPU 1 notifies the clock generation unit 5 of the change request CR, the busy signal BSY It can be said that the signal indicates that the frequency is being changed.

  On the other hand, since the completion signal FNS is output from the comparator 40 at a timing when the frequency of the peripheral clock PCLK is actually changed in the clock generation unit 5, it can be said that the signal is indicative of completion of the change of the frequency of the peripheral clock PCLK. .

  As described above, in the microprocessor 200 according to the second embodiment, the peripheral I / Os 30 and 31 receive the confirmation response after the completion signal FNS is input when there is an access request from the CPU 1 while the busy signal BSY is input. Signals ACK 0 and 1 are output to CPU 1, respectively. That is, when the access request from the CPU 1 is notified during the change of the frequency of the peripheral clock PCLK in the clock generation unit 5, the peripheral I / O 30, 31 is changed after the change of the frequency of the peripheral clock PCLK is completed. Confirmation response signals ACK0 and ACK1 are output to the CPU1, respectively. Therefore, it is possible to prevent the CPU 1 from accessing the peripheral I / Os 30 and 31 again while changing the frequency of the peripheral clock PCLK.

  Unlike the microprocessor 200 according to the second embodiment, the peripheral I / O unit 3 notifies the CPU 1 of the acknowledgment signal ACK even when the frequency of the peripheral clock PCLK is changed. In the case of the O port, since the CPU 1 shifts to the next operation when receiving the acknowledgment signal ACK, the CPU 1 causes the peripheral I / O 30 to execute the communication operation without changing the frequency of the peripheral clock PCLK. Sometimes. Therefore, a desired communication speed may not be executed.

  In the second embodiment, it is possible to prevent the CPU 1 from accessing the peripheral I / O unit 3 again while changing the frequency of the peripheral clock PCLK. Therefore, in the state where the frequency of the peripheral clock PCLK is not changed, It is possible to reduce the peripheral I / O 30 from performing a communication operation. As a result, a desired communication speed can be realized, and malfunctions of the microprocessor 200 can be reduced.

  In the second embodiment, the peripheral I / Os 30 and 31 perform a predetermined operation in response to an access request from the CPU 1 after the clock frequency change in the clock generation unit 5 is completed. Data is written to the register groups 30a and 31a. Therefore, it is possible to prevent the peripheral I / Os 30 and 31 from operating before the frequency of the peripheral clock PCLK is changed. Therefore, malfunctions of the peripheral I / Os 30 and 31 can be reduced, and as a result, malfunctions of the microprocessor 200 can be further reduced.

Embodiment 3 FIG.
FIG. 5 is a block diagram showing a configuration of a microprocessor 300 according to Embodiment 3 of the present invention. The microprocessor 300 according to the third embodiment is configured to include the interrupt generation unit 14 instead of the interrupt generation unit 4 and further include clock supply control units 7a and 7b in the first embodiment. is there.

  The clock supply controllers 7a and 7b are provided corresponding to the peripheral I / Os 30 and 31, respectively, and control the supply of the peripheral clock PCLK to the peripheral I / Os 30 and 31, respectively. Each of the clock supply control units 7 a and 7 b includes a detection circuit 73 having a comparator 70 and a memory 71 and an OR circuit 72.

  FIG. 6 is a block diagram showing the configuration of the comparator 70 and the memory 71. As shown in FIG. 6, the memory 71 is composed of a plurality of registers R1 to Rn (n ≧ 2). Each register R1 to Rn can rewrite stored information, and is read and written by the CPU 1 through the data bus DBUS. When there is no need to particularly distinguish the registers R1 to Rn, they are collectively referred to as a register Rn.

  Information indicating a predetermined frequency is stored in the register Rn of the memory 71 in the clock supply control unit 7a. For example, information (hereinafter referred to as “prohibited clock information FI1A”) indicating the frequency outside the operation specifications of the peripheral I / O 30 among the frequencies of the peripheral clock PCLK that can be set in the clock generation unit 5 is stored in the register Rn. . The entire prohibited clock information FI1A stored in the memory 71 of the clock supply controller 7a constitutes an information table. Hereinafter, this information table is referred to as “prohibition table T1A”.

  Information indicating a predetermined frequency is also stored in the register Rn of the memory 71 in the clock supply control unit 7b. For example, information indicating a frequency outside the operation specification of the peripheral I / O 31 (hereinafter referred to as “prohibited clock information FI1B”) among the frequencies of the peripheral clock PCLK that can be set in the clock generation unit 5 is stored in the register Rn. . The entire prohibited clock information FI1B stored in the memory 71 of the clock supply control unit 7b constitutes an information table. Hereinafter, this information table is referred to as a “prohibition table T1B”.

  As described above, the memory 71 according to the third embodiment stores information indicating the frequency of the peripheral clock PCLK that should not be input to the peripheral I / O.

  In the third embodiment, among combinations of multiplication ratios and frequency division ratios that can be set in the clock selection circuit 50, combinations in which the frequency of the peripheral clock PCLK becomes a value outside the operation specifications of the peripheral I / Os 30 and 31. Are employed as the prohibited clock information FI1A and FI1B, respectively.

  For example, when the system clock SCLK can operate at 10 MHz and the peripheral I / O 30 can operate at a maximum of 10 MHz, the combination of the multiplication ratio “4” and the division ratio “1”, the multiplication ratio “4” and the division ratio. A combination of “1/2” and a combination of multiplication ratio “2” and frequency division ratio “1” are stored in registers R1 to R3, respectively, and these combinations are included in prohibition table T1A. Yes. For example, when the system clock SCLK is 10 MHz and the peripheral I / O 31 can operate at a maximum of 20 MHz, the combination of the multiplication ratio “4” and the division ratio “1” is stored in the register R1. This combination is included in the prohibition table T1B.

  As shown in FIG. 6, the comparator 70 includes n comparison circuits CM <b> 1 to CMn and an OR circuit OR. The comparison circuits CM1 to CMn are provided corresponding to the registers R1 to Rn, respectively. Each of the comparison circuits CM1 to CMn in the clock supply control unit 7a compares the prohibited clock information FI1A stored in the corresponding register Rn with the data FDATA1, and outputs a High level if they match, and if they do not match. In this case, the Low level is output. Similarly, each of the comparison circuits CM1 to CMn in the clock supply control unit 7b compares the prohibited clock information FI1B stored in the corresponding register Rn with the data FDATA1, and outputs a high level if they match. If they do not match, the Low level is output. The OR circuit OR calculates the logical sum of the outputs of the comparison circuits CM <b> 1 to CMn, and outputs the calculation result to the OR circuit 72 as the output of the detection circuit 73.

  As a result, when the value of the data FDATA1 exists in the prohibition table T1A stored in the memory 71 of the clock supply control unit 7a, the detection circuit 73 outputs the high level, and when it does not exist, the low level is output. . Further, when the value of the data FDATA1 exists in the prohibition table T1B stored in the memory 71 of the clock supply control unit 7b, the High level is output, and when it does not exist, the Low level is output.

  As described above, the comparator 70 of the detection circuit 73 compares the information indicating the predetermined frequency stored in the memory 71 with the data FDATA1. As described above, since the data FDATA1 includes the multiplication ratio selection signal SELA and the frequency division ratio selection signal SELB, when the CPU 1 changes the frequency of the peripheral clock PCLK, the data FDATA1 The frequency to which the peripheral clock PCLK is changed is shown. Accordingly, by comparing the information stored in the memory 71 with the data FDATA1, the frequency indicated by the information, the frequency outside the operation specifications of the peripheral I / O in the third embodiment, and the change of the peripheral clock PCLK are displayed. The previous frequency is compared. That is, the comparator 70 according to the third embodiment compares the frequency indicated by the information stored in the memory 71 with the frequency to which the peripheral clock PCLK is changed, and outputs the comparison result.

  As described above, the detection circuit 73 compares the change destination frequency of the peripheral clock PCLK with the frequency indicated by the information stored in the memory 71, so that the change destination frequency matches the frequency indicated by the information. Whether it is detected. In the detection circuit 73 according to the third embodiment, it is detected whether or not the frequency to which the peripheral clock PCLK is changed matches the frequency outside the operation specifications of the peripheral I / O. Then, the high level is output to the OR circuit 72 as a detection result when they match, and the low level is output as a detection result when they do not match.

  The OR circuit 72 of the clock supply control unit 7a calculates the logical sum of the output of the detection circuit 73 and the peripheral clock PCLK output from the clock selection circuit 50 and outputs the logical sum to the peripheral I / O 30. Thus, the peripheral clock PCLK is not supplied to the peripheral I / O 30 when the output of the detection circuit 73 is at the high level, and the peripheral clock PCLK is supplied when the output is at the low level. As described above, the clock supply control unit 7 a controls whether or not the peripheral clock PCLK is supplied to the peripheral I / O 30 based on the detection result output from the detection circuit 73.

  Similarly, the OR circuit 72 of the clock supply control unit 7 b calculates the logical sum of the output of the detection circuit 73 and the peripheral clock PCLK output from the clock selection circuit 50 and outputs it to the peripheral I / O 31. Thus, the peripheral clock PCLK is not supplied to the peripheral I / O 31 when the output of the detection circuit 73 is at the high level, and the peripheral clock PCLK is supplied when the output is at the low level. As described above, the clock supply control unit 7 b controls whether or not to supply the peripheral clock PCLK to the peripheral I / O 31 based on the detection result output from the detection circuit 73. The value is written into the register Rn of the memory 71 by the CPU 1 when the microprocessor 300 is initialized upon power-on or reset.

  The outputs of the detection circuits 73 of the clock supply controllers 7a and 7b are input to the interrupt generator 14 as comparison result signals CRA and CRB, respectively. The interrupt generator 14 also receives I / O selection signals PSEL0 and PSEL1. The interrupt generator 14 outputs an interrupt request signal IREQ to the CPU 1 when the I / O selection signal PSEL0 transits from the Low level to the High level when the comparison result signal CRA is at the High level. Furthermore, the interrupt generation unit 14 outputs an interrupt request signal IREQ to the CPU 1 when the I / O selection signal PSEL1 transits from the Low level to the High level when the comparison result signal CRB is at the High level. Since other configurations and operations are the same as those of the microprocessor 100 according to the first embodiment, description thereof is omitted.

  As described above, in the microprocessor 300 according to the third embodiment, when the frequency to which the peripheral clock PCLK is changed in the clock generation unit 5 matches the frequency indicated by the information stored in the memory 71, the peripheral I / O The peripheral clock PCLK is not supplied to O30 and 31. Accordingly, by storing in the memory 71 information indicating an unacceptable frequency of the peripheral clock PCLK that should not be input to the peripheral I / Os 30 and 31, the peripheral clock PCLK has an unacceptable frequency due to a defect in the execution program of the CPU 1 or the like. Is set, the supply of the peripheral clock PCLK to the peripheral I / Os 30 and 31 is stopped.

  For example, as shown in the third embodiment, by storing information indicating the frequency outside the operation specifications of the peripheral I / Os 30 and 31 in the memory 71, the frequency of the peripheral clock PCLK is the operation of the peripheral I / Os 30 and 31. When set outside the specification, the detection circuit 73 detects that the frequency to which the peripheral clock PCLK is changed is outside the operation specifications of the peripheral I / Os 30 and 31, and based on the detection result, the peripheral I The input of the peripheral clock PCLK to / O30, 31 is stopped.

  Further, when the frequency of the CPU clock CCLK input to the CPU 1 is increased in order to cause the CPU 1 to execute high-speed processing, the frequency of the peripheral clock PCLK is also changed and set outside the operation specifications of the peripheral I / Os 30 and 31. Even in such a case, such a peripheral clock PCLK is not input to the peripheral I / Os 30 and 31.

  As described above, in the microprocessor 300 according to the third embodiment, it is possible to prevent the peripheral clock PCLK having an inappropriate frequency from being input to the peripheral I / Os 30 and 31, so that the peripheral I / Os 30 and 31 Malfunctions can be reduced, and as a result, malfunctions of the microprocessor 300 can be reduced.

  Further, the interrupt generation unit 14 according to the third embodiment outputs an interrupt request signal IREQ to the CPU 1 when the I / O selection signal PSEL0 rises when the comparison result signal CRA is at a high level. The high level of the comparison result signal CRA indicates a state in which the peripheral clock PCLK is not supplied to the peripheral I / O 30, and when the I / O selection signal PSEL0 rises, there is an access request from the CPU 1 to the peripheral I / O 30. It is shown that. Therefore, when the CPU 1 accesses the peripheral I / O 30 when the clock supply control unit 7a does not supply the peripheral clock PCLK to the peripheral I / O 30, the interrupt generator 14 notifies the CPU 1 of an interrupt request. Similarly, when the CPU 1 accesses the peripheral I / O 31 when the clock supply control unit 7b does not supply the peripheral clock PCLK to the peripheral I / O 31, the interrupt generation unit 14 notifies the CPU 1 of the interrupt request. Yes.

  As described above, in the third embodiment, when the CPU 1 accesses the peripheral I / Os 30 and 31 to which the peripheral clock PCLK is not supplied due to a defect in the execution program of the CPU 1, an interrupt request is issued from the interrupt generation unit 14. Since the CPU 1 is notified, the CPU 1 can recognize that the peripheral clock PCLK is not supplied to the peripheral I / Os 30 and 31. Therefore, the CPU 1 can be prevented from accessing the peripheral I / Os 30 and 31 to which the peripheral clock PCLK is not supplied again.

  For example, the CPU 1 that has received an interrupt request from the interrupt generation unit 14 sets the predetermined data in the register 52 to change the frequency of the peripheral clock PCLK within the operation specifications of the peripheral I / Os 30 and 31, and then the peripheral I / O30, 31 can be accessed. As a result, malfunctions of the microprocessor 300 can be reduced.

  Further, since an interrupt request is notified to the CPU 1 from the interrupt generation unit 14, it is easy to debug the execution program at the development stage of the execution program of the CPU 1. As a result, it is possible to reduce the occurrence of malfunction such as the CPU 1 accessing the peripheral I / Os 30 and 31 in a state where the peripheral clock PCLK is not supplied.

  In addition, since the memory 71 according to the third embodiment can rewrite the stored information, the memory 71 can be changed by changing the contents of the memory 71 even after the microprocessor 300 is designed or manufactured. The predetermined frequency indicated by the information stored in can be changed. Therefore, after the design or manufacture of the microprocessor 300, the frequency outside the operation specification of the peripheral I / O 30, 31 set in the memory 71 can be changed.

  Usually, after designing or manufacturing, the operation of the peripheral I / Os 30 and 31 is confirmed, and the frequency that can guarantee the operation of the peripheral I / Os 30 and 31, that is, the frequency within the operation specification is finally determined. Therefore, by adopting a rewritable storage device in the memory 71, information indicating the frequency outside the operation specifications can be written in the memory 71 based on the operation specifications of the peripheral I / Os 30 and 31 after final determination. . As a result, malfunctions of the peripheral I / Os 30 and 31 can be reliably reduced.

Embodiment 4 FIG.
FIG. 7 is a block diagram showing a configuration of a microprocessor 400 according to Embodiment 4 of the present invention. The microprocessor 400 according to the fourth embodiment includes the interrupt generation unit 24 instead of the interrupt generation unit 4 and further includes the access control unit 8 in the microprocessor 100 according to the first embodiment described above. Is.

  The access control unit 8 includes detection circuits 80a and 80b and AND circuits 81 and 82, and controls access from the CPU 1 to the peripheral I / Os 30 and 31. Each of the detection circuits 80a and 80b includes the above-described comparator 70 and the memory 71 in the same manner as the detection circuit 73 according to the third embodiment. For example, the prohibition clock information FI1A is stored in the memory 71 of the detection circuit 80a, and the prohibition clock information FI1A stored in the memory 71 constitutes the prohibition table T1A. Further, for example, prohibited clock information FI1B is stored in the memory 71 of the detection circuit 80b, and the entire prohibited clock information FI1B stored in the memory 71 constitutes a prohibited table T1B.

  In the fourth embodiment, as in the third embodiment, the frequency of the peripheral clock PCLK is the operation specification of the peripheral I / Os 30 and 31 among the combinations of the multiplication ratio and the division ratio that can be set in the clock selection circuit 50. Combinations having external values are employed as the prohibited clock information FI1A and FI1B, respectively.

  The comparison result signal CRA output from the comparator 70 of the detection circuit 80a is input to the AND circuit 81 and the interrupt generator 24. The AND circuit 81 calculates a logical product of the inverted signal of the comparison result signal CRA and the I / O selection signal PSEL0 and outputs the logical product to the peripheral I / O 30. As a result, the I / O selection signal PSEL0 is not input to the peripheral I / O 30 when the output of the detection circuit 80a is at the high level, but is input when the output is at the low level. Here, as described above, when the I / O selection signal PSEL0 becomes the high level, the access request from the CPU 1 is notified to the peripheral I / O 30. Therefore, whether the access control unit 8 permits the CPU 1 to access the peripheral I / O 30 by controlling the input of the I / O selection signal PSEL0 to the peripheral I / O 30 based on the output of the comparator 70. No control is performed. That is, the access control unit 8 controls whether to permit access to the peripheral I / O 30 from the CPU 1 based on the detection result output from the detection circuit 80a.

  The comparison result signal CRB output from the comparator 70 of the detection circuit 80b is input to the AND circuit 82 and the interrupt generation unit 24. The AND circuit 82 calculates the logical product of the inverted signal of the comparison result signal CRB and the I / O selection signal PSEL1, and outputs the logical product to the peripheral I / O 31. As a result, the peripheral I / O 31 is not input with the I / O selection signal PSEL1 when the output of the detection circuit 80b is at the high level, but is input with the output at the low level. Here, as described above, the access request from the CPU 1 is notified to the peripheral I / O 31 by setting the I / O selection signal PSEL1 to the high level. Therefore, whether the access control unit 8 permits the CPU 1 to access the peripheral I / O 31 by controlling the input of the I / O selection signal PSEL1 to the peripheral I / O 31 based on the output of the comparator 70. No control is performed. That is, the access control unit 8 controls whether or not to permit access to the peripheral I / O 31 from the CPU 1 based on the detection result output from the detection circuit 80b.

  The interrupt generator 24 also receives I / O selection signals PSEL0 and PSEL1. The interrupt generator 24 outputs an interrupt request signal IREQ to the CPU 1 when the I / O selection signal PSEL0 transits from the Low level to the High level when the comparison result signal CRA is at the High level. Furthermore, when the I / O selection signal PSEL1 transitions from the Low level to the High level when the comparison result signal CRB is at the High level, the interrupt generation unit 24 outputs the interrupt request signal IREQ to the CPU1. Since other configurations and operations are the same as those of the microprocessor 100 according to the first embodiment, description thereof is omitted.

  As described above, in the microprocessor 400 according to the fourth embodiment, when the outputs of the detection circuits 80a and 80b are at the high level, access to the peripheral I / Os 30 and 31 from the CPU 1 is prohibited. As can be understood from the contents of the third embodiment, the detection circuits 80 a and 80 b have the frequency to which the peripheral clock PCLK is changed in the clock generation unit 5 set to the frequency indicated by any of the information stored in the memory 71. If they match, the High level is output. Therefore, when the frequency to which the peripheral clock PCLK is changed coincides with the frequency indicated by the information stored in the memory 71 by the operation of the access control unit 8, the CPU 1 is prohibited from accessing the peripheral I / Os 30 and 31. Is done.

  As a result, for example, by storing information indicating frequencies outside the operation specifications of the peripheral I / Os 30 and 31 in the memory 71, a state in which the peripheral clock PCLK outside the operation specifications is input due to a defect in the execution program of the CPU 1, etc. Thus, even if the CPU 1 tries to access the peripheral I / Os 30 and 31, it can be prevented from being actually accessed. As a result, the peripheral I / Os 30 and 31 to which the peripheral clock PCLK outside the operation specification is input are not operated, so that the malfunction of the microprocessor 400 can be reduced.

  The interrupt generator 24 according to the fourth embodiment outputs an interrupt request signal IREQ to the CPU 1 when the I / O selection signal PSEL0 rises when the comparison result signal CRA is at a high level. In the fourth embodiment, the high level of the comparison result signal CRA indicates that the peripheral clock PCLK having a frequency outside the operation specifications is input to the peripheral I / O 30, and the rising edge of the I / O selection signal PSEL0. Indicates that the CPU 1 tried to access the peripheral I / O 30. Therefore, when the access control unit 8 prohibits access from the CPU 1 to the peripheral I / O 30 and the CPU 1 tries to access the peripheral I / O 30, the interrupt generation unit 24 notifies the CPU 1 of an interrupt request. Yes. Similarly, when the access control unit 8 prohibits the CPU 1 from accessing the peripheral I / O 31 when the access control unit 8 prohibits the CPU 1 from accessing the peripheral I / O 31, the interrupt generating unit 24 issues an interrupt request to the CPU 1. Notify.

  As described above, when the access control unit 8 prohibits the CPU 1 from accessing the peripheral I / Os 30 and 31, when the CPU 1 tries to access the peripheral I / Os 30 and 31, the CPU 1 is notified of an interrupt request. Therefore, the CPU 1 can recognize that the peripheral clock PCLK having an inappropriate frequency is supplied to the peripheral I / Os 30 and 31. Therefore, for example, it is possible to prevent the CPU 1 from trying to access again the peripheral I / Os 30 and 31 to which the peripheral clock PCLK outside the operation specification is supplied. As a result, malfunctions of the microprocessor 400 can be reduced.

  Further, since the interrupt request is notified to the CPU 1 from the interrupt generation unit 24, it becomes easy to debug the execution program at the development stage of the execution program of the CPU 1. As a result, it is possible to reduce the occurrence of malfunction such as the CPU 1 accessing the peripheral I / O 30, 31 in a state where the peripheral clock PCLK having an inappropriate frequency is supplied.

  Further, since the memory 71 of the detection circuits 80a and 80b can rewrite the stored information, even after the design or manufacture of the microprocessor 400, the contents of the memory 71 can be changed to change to the memory 71. The predetermined frequency indicated by the stored information can be changed. Therefore, the frequency outside the operation specifications of the peripheral I / Os 30 and 31 set in the memory 71 can be changed after the design or manufacture of the microprocessor 400. As a result, based on the operation specifications of the peripheral I / Os 30 and 31 finally determined after design and manufacture, information indicating the frequency outside the operation specifications can be written in the memory 71, thereby ensuring the peripheral I / O 30. , 31 can be reduced.

Embodiment 5 FIG.
FIG. 8 is a block diagram showing a configuration of a microprocessor 500 according to the fifth embodiment of the present invention. The microprocessor 500 according to the fifth embodiment includes the interrupt generation unit 34 instead of the interrupt generation unit 4 in the configuration of the microprocessor 100 according to the first embodiment, and further includes the clock change control unit 9. It is to be prepared.

  The clock change control unit 9 includes a detection circuit 90, a register 92, an OR circuit 93, and AND circuits 94 and 95. As described above, the CPU 1 outputs a change request CR for the frequency of the peripheral clock PCLK to the clock generation unit 5. The clock change control unit 9 controls whether or not to permit notification of the change request CR to the clock generation unit 5. Hereinafter, this control is referred to as “notification permission control CNT”.

  Like the detection circuit 73 according to the third embodiment, the detection circuit 90 includes a comparator 70 and a memory 71, and the memory 71 according to the fourth embodiment stores information indicating a predetermined frequency. Has been. For example, in each of the registers R1 to Rn of the memory 71, information indicating the frequency outside the operation specifications of the peripheral I / Os 30 and 31 among the frequencies of the peripheral clock PCLK that can be set in the clock generator 5 (hereinafter referred to as “prohibited clock information”). FI2 ") is stored. The entire prohibited clock information FI2 stored in the memory 71 constitutes an information table. Hereinafter, this information table is referred to as “prohibition table T2”. In the fifth embodiment, the maximum values of the operation specifications of the peripheral I / Os 30 and 31 with respect to the peripheral clock PCLK are the same.

  In the fifth embodiment, among combinations of multiplication ratios and frequency division ratios that can be set in the clock selection circuit 50, combinations in which the peripheral clock PCLK is outside the operation specifications of the peripheral I / Os 30 and 31 are prohibited clocks. It is adopted as information FI2. For example, when the system clock SCLK is 10 MHz and both the peripheral I / Os 30 and 31 can operate at a maximum of 10 MHz, the combination of the multiplication ratio “4” and the division ratio “1” and the multiplication ratio “ The combination of 4 ”and the division ratio“ 1/2 ”and the combination of the multiplication ratio“ 2 ”and the division ratio“ 1 ”are stored in the registers R1 to R3, respectively, and these combinations are prohibited. It is included in table T2.

  As described above, the memory 71 according to the fifth embodiment stores information indicating the frequency of the peripheral clock PCLK that should not be input to both the peripheral I / Os 30 and 31.

  The data FDATA1 is input to the comparator 70 according to the above-described third embodiment, but is output from the CPU 1 to the comparator 70 according to the fifth embodiment when the frequency of the peripheral clock PCLK is changed. The change data VD is input instead. Specifically, in the block diagram of the comparator 70 shown in FIG. 6, the change data VD output from the CPU 1 is input to each of the comparison circuits CM1 to CMn instead of the data FDATA1. Therefore, in the comparator 70 according to the fifth embodiment, the information stored in the memory 71 and the change data VD are compared, and the change data matches the information stored in the memory 71. Then, the High level is output from the OR circuit OR, and the Low level is output when they do not match.

  In the fifth embodiment, information indicating a frequency outside the operation specifications of the peripheral I / Os 30 and 31 is adopted as the information stored in the memory 71. Therefore, in the comparator 70 according to the fifth embodiment, the memory 70 71 is compared with the change data VD output from the CPU 1 when the frequency of the peripheral clock PCLK is changed, and the division ratio and multiplication ratio included in the change data VD are compared. When the combination is present in the prohibition table T2, the High level is output, and when the combination is not present, the Low level is output.

  As described above, the comparator 70 of the detection circuit 90 compares the information indicating the predetermined frequency stored in the memory 71 with the change data VD. Here, as described above, the change data VD includes the change destination information VI indicating the change destination frequency of the peripheral clock PCLK. Therefore, by comparing the information stored in the memory 71 with the change data VD, the frequency indicated by the information in the memory 71, the frequency outside the operating specifications of the peripheral I / Os 30 and 31 in the fifth embodiment, and The frequency to which the peripheral clock PCLK is changed is compared. That is, the comparator 70 according to the fifth embodiment compares the frequency indicated by the information stored in the memory 71 with the frequency to which the peripheral clock PCLK is changed, and outputs the comparison result.

  As described above, the detection circuit 90 compares the frequency to which the peripheral clock PCLK is changed with the frequency indicated by the information stored in the memory 71, so that the frequency to be changed is the frequency indicated by the information in the memory 71. Is detected if it matches. The detection circuit 90 according to the fifth embodiment detects whether or not the frequency to which the peripheral clock PCLK is changed matches the frequency outside the operation specifications of the peripheral I / O. If they match, the high level is output to the OR circuit 93 as a detection result, and if not, the low level is output as a detection result.

  The OR circuit 93 calculates and outputs a logical sum of the output of the detection circuit 90 and the I / O execution signal EX output from the peripheral I / O unit 3. Here, the I / O execution signal EX indicates a high level when at least one of the peripheral I / Os 30 and 31 is operating, and indicates a low level when both are not operating. For example, when the peripheral I / O 30 and 31 are a timer and a serial I / O port, respectively, when the peripheral I / O 30 performs a timer operation and executes time measurement, or the peripheral I / O 31 is serially connected to an external device. During communication, the I / O execution signal EX indicates a high level.

  Information indicating execution / non-execution of the notification permission control CNT is written in the register 92. In the fifth embodiment, “1” is written in the register 52 as information indicating execution of the notification permission control CNT, and “0” is written in the register 52 as information indicating non-execution. Then, the register 92 outputs the stored value to the AND circuit 94. Note that the CPU 1 writes the value into the register 92, for example.

  The AND circuit 94 calculates and outputs a logical product of the output of the register 92 and the output of the AND circuit 93. The AND circuit 95 calculates the logical product of the inverted signal of the output of the AND circuit 93 and the write enable signal WEN output from the CPU 1 and outputs the logical product to the register 52. As a result, the write enable signal WEN is input to the register 52 when the output of the AND circuit 94 is at the low level, and is not input when the output is at the high level.

  The interrupt generator 34 receives the output of the AND circuit 94 and the write enable signal WEN. The interrupt generation unit 34 outputs an interrupt request signal IREQ to the CPU 1 when the write enable signal WEN is input when the output of the AND circuit 94 is at a high level.

  Note that the CPU 1 according to the fifth embodiment differs from the CPU 1 according to the first to fourth embodiments in that when the frequency of the peripheral clock PCLK is changed, the output of the AND circuit 94 is determined after the change data VD is output. The write enable signal WEN is output. Since other configurations and operations are the same as those of the microprocessor 100 according to the first embodiment, description thereof is omitted.

  Next, the operation of the clock change control unit 9 will be described in detail. First, the operation of the clock change control unit 9 when the output of the detection circuit 90 is at the low level will be described.

  When “1” is written in the register 92, that is, when the information written in the register 92 indicates execution of the notification permission control CNT, when at least one of the peripheral I / Os 30 and 31 is operating, the clock In the change control unit 9, the output of the AND circuit 94 becomes High level. For this reason, the output of the AND circuit 95 is fixed to the Low level, and the notification of the change request CR by the CPU 1 to the clock generation unit 5 is not permitted. When both the peripheral I / Os 30 and 31 are not operating, the output of the AND circuit 94 is at a low level, and notification of the change request CR output from the CPU 1 to the clock generation unit 5 is permitted.

  When “0” is written in the register 92, that is, when the information written in the register 92 indicates that the notification permission control CNT is not executed, the clock is output regardless of the operation of the peripheral I / Os 30 and 31. In the change control unit 9, the output of the AND circuit 94 is always low, and the notification of the change request CR to the clock generation unit 5 is always permitted.

  In this way, when “1” is set in the register 92, the clock change control unit 9 executes notification permission control CNT based on whether or not the peripheral I / Os 30 and 31 are operating. If the register 92 is set to “0”, the notification permission control CNT is not executed.

  Here, as described above, when the frequency of the peripheral clock PCLK is changed, the CPU 1 outputs the write enable signal WEN after the output of the AND circuit 94 is determined after the change data VD is output. Therefore, when the clock change control unit 9 executes the notification permission control CNT, the CPU 1 tries to change the frequency of the peripheral clock PCLK during the operation of the peripheral I / Os 30 and 31 due to a defect in the execution program of the CPU 1 or the like. However, the change request CR is not notified to the clock generator 5. Therefore, the frequency of the peripheral clock PCLK is not changed during the operation of the peripheral I / Os 30 and 31. Therefore, malfunctions of the peripheral I / Os 30 and 31 can be reduced, and malfunctions of the microprocessor 500 can be reduced.

  Next, the operation of the clock change control unit 9 when the I / O execution signal EX is at a low level will be described.

  When “1” is written in the register 92 and the change data VD matches any of the information stored in the memory 71 of the detection circuit 90, the output of the AND circuit 94 is high in the clock change control unit 9. Become a level. In the fifth embodiment, since the memory 71 stores information indicating the frequency outside the operation specifications of the peripheral I / Os 30 and 31, the change destination information VI included in the change data VD is the peripheral I / Os 30 and 31. When the frequency is outside the operation specifications, the output of the AND circuit 94 becomes High level. For this reason, the output of the AND circuit 95 is fixed to the Low level, and the notification of the change request CR by the CPU 1 to the clock generation unit 5 is not permitted.

  When the change data VD does not match any of the information stored in the memory 71 of the detection circuit 90, the output of the AND circuit 94 becomes low level. In the fifth embodiment, when the change destination information VI included in the change data VD indicates a frequency within the operation specifications of the peripheral I / Os 30 and 31, the output of the AND circuit 94 is at a low level. Therefore, notification of the change request CR output from the CPU 1 to the clock generation unit 5 is permitted.

  As described above, the clock change control unit 9 according to the fifth embodiment controls whether to allow the notification of the change request CR to the clock generation unit 5 based on the detection result of the detection circuit 90.

  When “0” is written in the register 92, the output of the AND circuit 94 is always at the Low level in the clock change control unit 9 regardless of the contents of the change destination information VI included in the change data VD. Therefore, notification of the change request CR to the clock generation unit 5 is always permitted.

  In this way, when “1” is set in the register 92, the clock change control unit 9 notifies based on whether or not the change destination information VI indicates outside the operation specifications of the peripheral I / Os 30 and 31. The permission control CNT is executed, and when the register 92 is set to “0”, the notification permission control CNT is not executed.

  As described above, in the microprocessor 500 according to the fifth embodiment, the frequency indicated by the change destination information VI is stored in the memory 71 when the clock change control unit 9 executes the notification permission control CNT. When the frequency matches the frequency indicated by the information, the clock generation unit 5 is not notified of the change request CR. Here, as described above, when the CPU 1 according to the fifth embodiment changes the frequency of the peripheral clock PCLK, after the change data VD is output, the output of the AND circuit 94 is determined and then the write enable signal WEN is determined. Is output. Therefore, for example, by storing information indicating the frequency outside the operation specifications of the peripheral I / Os 30 and 31 in the memory 71, the CPU 1 sets the frequency of the peripheral clock PCLK due to a defect in the execution program of the CPU 1 and the like. Even if an attempt is made to set a value outside the 31 operation specifications, the change request CR is not notified to the clock generator 5. Therefore, the frequency of the peripheral clock PCLK is not changed to an inappropriate frequency. As a result, malfunctions of the peripheral I / Os 30 and 31 can be reduced, and malfunctions of the microprocessor 500 can be reduced.

  Further, the interrupt generation unit 34 according to the fifth embodiment outputs the change request CR from the CPU 1 in a situation where the clock change control unit 9 does not permit the clock generation unit 5 to notify the change request CR. If it does, the CPU 1 is notified of an interrupt request. Therefore, it becomes easy to debug the execution program in the development stage of the execution program of the CPU 1. As a result, an unnecessary operation such as the CPU 1 trying to change the peripheral clock PCLK outside the operation specifications of the peripheral I / O 30, 31 or the CPU 1 sets the frequency of the peripheral clock PCLK during the operation of the peripheral I / O 30, 31. It is possible to reduce the occurrence of unnecessary operations such as changing.

  In addition, since the clock change control unit 9 according to the fifth embodiment includes the register 92 that can write information indicating execution / non-execution of the notification permission control CNT, whether the notification permission control CNT is executed. A choice of whether or not can be made.

  In the fifth embodiment, the CPU 1 outputs the write valid signal WEN after outputting the change data VD. However, as with the CPUs according to the first to fourth embodiments, the change data VD, the write valid signal WEN, May be output simultaneously. In this case, a clock generation unit is provided by delaying the input of the write enable signal WEN to the AND circuit 95 and the interrupt generation unit 34 until the output of the AND circuit 94 is determined from the output of the change data VD. The notification of the change request CR to 5 can be controlled.

  In addition, since the memory 71 of the detection circuit 90 can rewrite the stored information, the memory 71 is stored in the memory 71 by changing the contents of the memory 71 even after the microprocessor 500 is designed or manufactured. The predetermined frequency indicated by the stored information can be changed. Therefore, after designing or manufacturing the microprocessor 500, for example, the frequency outside the operation specifications of the peripheral I / O 30, 31 set in the memory 71 can be changed. As a result, based on the operation specifications of the peripheral I / Os 30 and 31 finally determined after design and manufacture, information indicating the frequency outside the operation specifications can be written in the memory 71, thereby ensuring the peripheral I / O 30. , 31 can be reduced.

  In the third to fifth embodiments of the present specification, the memory 71 is composed of a plurality of registers R1 to Rn, but may be composed of a single register R1. In this case, the comparison circuit in the comparator 70 may be one comparison circuit CM1, and the OR circuit OR becomes unnecessary. The output of the comparison circuit CM1 is output as the output of the detection circuit 73.

  In addition, some of the registers R1 to Rn constituting the memory 71 are used for holding frequencies outside the operation specifications of the peripheral I / Os 30 and 31, and when other registers are not used, the comparison circuit in the subsequent stage A device is devised so that the comparison circuit corresponding to the other registers among CM1 to CMn always outputs a low level.

  For example, a valid bit is provided in the most significant bit (MSB) of each register R1 to Rn, the valid bit of the register Rn to be used is set valid, and the valid bit of the unused register Rn is set invalid. Then, using the effective bit of the register Rn, the detection circuit is configured so that the subsequent comparison circuit corresponding to the unused register Rn always outputs the Low level. Thereby, even when some of the registers R1 to Rn are used, the basic configuration shown in FIG. 6 can be used.

  In the third to fifth embodiments, the memory 71 is constituted by a register. However, the memory 71 may be constituted by a RAM or a writable PROM (Programmable ROM). As the PROM, any ROM such as a non-rewritable PROM such as a fuse ROM or a rewritable PROM such as an EEPROM may be adopted.

  In addition, if it is possible to determine the frequency outside or within the operation specifications of the peripheral I / Os 30 and 31 at the stage of circuit design, the comparison circuits CM1 to CMn can be compared with the data FDATA1 or the change data VD. The value of may be a fixed value. For example, instead of inputting the output of the register Rn to the comparison circuits CM1 to CMn, a digital value composed of a combination of the high level and the low level obtained from the wiring of the power supply line and the ground line is input to the comparison circuits CM1 to CMn. Also good.

It is a block diagram which shows the structure of the microprocessor which concerns on Embodiment 1 of this invention. It is a block diagram which shows the structure of the microprocessor which concerns on Embodiment 1 of this invention. 3 is a timing chart illustrating an operation of the microprocessor according to the first embodiment of the present invention. It is a block diagram which shows the structure of the microprocessor which concerns on Embodiment 2 of this invention. It is a block diagram which shows the structure of the microprocessor which concerns on Embodiment 3 of this invention. It is a block diagram which shows the structure of the microprocessor which concerns on Embodiment 3 of this invention. It is a block diagram which shows the structure of the microprocessor which concerns on Embodiment 4 of this invention. It is a block diagram which shows the structure of the microprocessor which concerns on Embodiment 4 of this invention.

Explanation of symbols

1 CPU, 4, 14, 24, 34 Interrupt generation unit, 5 clock generation unit, 6 clock change completion determination unit, 7a, 7b clock supply control unit, 8 access control unit, 9 clock change control unit, 30, 31 peripheral I / O, 70 comparator, 71 memory, 73, 80a, 80b, 90 detection circuit, 92 registers.

Claims (13)

A CPU having an interrupt function;
A clock generator that outputs a clock with variable frequency;
Peripheral I / O that operates based on the clock and is accessed from the CPU;
An interrupt generation unit,
The clock generation unit changes the frequency of the clock based on a change request from the CPU,
The interrupt generation unit notifies the CPU of an interrupt request when the change of the clock frequency in the clock generation unit is completed. CPU,
A clock generator that outputs a clock with variable frequency;
Peripheral I / O that operates based on the clock and outputs an acknowledgment signal to the CPU in response to an access request from the CPU;
A clock change completion determination unit,
When the CPU notifies the access request to the peripheral I / O, the CPU performs the following operation after receiving the confirmation response signal from the peripheral I / O,
The clock generation unit changes the frequency of the clock based on a change request from the CPU,
The clock change completion determination unit receives a busy signal indicating that the clock frequency is being changed in the clock generation unit and a completion signal indicating completion of the clock frequency change in the clock generation unit. Output to / O,
The peripheral I / O is a microprocessor that outputs the confirmation response signal after inputting the completion signal when the CPU requests the access while the busy signal is input.   3. The peripheral I / O performs a predetermined operation on the access request after the completion signal is input when the CPU requests the access while the busy signal is input. The described microprocessor. CPU,
A clock generator that outputs a clock with variable frequency;
Peripheral I / O that operates based on the clock;
A clock supply control unit that controls supply of the clock to the peripheral I / O;
The clock generation unit changes the frequency of the clock based on a change request from the CPU,
The clock supply control unit has a detection circuit that detects whether or not a frequency to which the clock is changed in the clock generation unit matches a predetermined frequency, and based on a detection result of the detection circuit, the clock supply control unit A microprocessor that controls whether to supply to I / O. The CPU has an interrupt function;
When the clock supply control unit is not supplying the clock to the peripheral I / O, the CPU further includes an interrupt generation unit that notifies the CPU of an interrupt request when the CPU accesses the peripheral I / O. The microprocessor according to claim 4. CPU,
A clock generator that outputs a clock with variable frequency;
Peripheral I / O operating based on the clock;
An access control unit that controls access from the CPU to the peripheral I / O;
The clock generation unit changes the frequency of the clock based on a change request from the CPU,
The access control unit includes a detection circuit that detects whether or not a frequency to which the clock is changed in the clock generation unit matches a predetermined frequency, and based on a detection result of the detection circuit, the peripheral from the CPU A microprocessor that controls whether to permit access to I / O. The CPU has an interrupt function;
When the access control unit prohibits access from the CPU to the peripheral I / O, when the CPU tries to access the peripheral I / O, an interrupt is generated to notify the CPU of an interrupt request. The microprocessor according to claim 6, further comprising a unit. A clock generator that outputs a clock with variable frequency;
Peripheral I / O that operates based on the clock;
A CPU for outputting a change request for the frequency of the clock to the clock generation unit;
A clock change control unit for controlling whether to permit notification of the change request to the clock generation unit,
The clock change control unit, in the control,
When the peripheral I / O is not operating, permit notification of the change request to the clock generation unit,
When the peripheral I / O is operating, the notification of the change request to the clock generation unit is not permitted,
The clock generation unit is a microprocessor that changes a frequency of the clock based on the change request. A clock generator that outputs a clock with variable frequency;
Peripheral I / O that operates based on the clock;
A CPU that outputs a change request to the clock frequency and first information indicating a change destination of the clock frequency to the clock generation unit;
A clock change control unit for controlling whether to permit notification of the change request to the clock generation unit,
The clock change control unit includes a detection circuit that detects whether a frequency indicated by the first information matches a predetermined frequency, and the change request to the clock generation unit based on a detection result of the detection circuit Control whether or not to allow notifications,
The clock generation unit is a microprocessor that changes a frequency of the clock based on the first information and the change request. The CPU has an interrupt function;
The system further comprises an interrupt generation unit that notifies the CPU of an interrupt request when the CPU outputs the change request in a situation where the clock change control unit does not permit the clock generation unit to notify the change request. The microprocessor according to any one of claims 8 and 9. The clock change control unit
A register capable of writing second information indicating execution / non-execution of the control;
The clock change control unit executes the control when the second information written in the register indicates the execution of the control, and executes the control when the second information indicates the non-execution of the control. The microprocessor according to any one of claims 8 to 10, wherein notification of a change request is always permitted. The detection circuit includes a memory in which stored information can be rewritten, and a comparator.
The memory stores information indicating the predetermined frequency,
The microprocessor according to claim 4, wherein the comparator compares a frequency indicated by the information with a frequency to which the clock is changed. The detection circuit includes a memory in which stored information can be rewritten, and a comparator.
The memory stores second information indicating the predetermined frequency,
The microprocessor according to claim 9, wherein the comparator compares the first information with the second information.

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