JP2005063181A - Synchronous dram controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an SDRAM (synchronous dynamic random access memory) controller capable of responding to a change in operation frequency such as a further increase in speed of the operation frequency (the frequency of clock signal) in the same SDRAM and SDRAM controller. <P>SOLUTION: This controller comprises a first command generation circuit 12a and a second command generation circuit 12b for generating a read command or write command at different times after generating an active command. A selector 14 selects the first command generation circuit 12a or the second command generation circuit 12b according to the frequency of the clock signal. The SDRAM 3 is controlled with the command generated by the selected command generation circuit. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to access control of a synchronous DRAM.

  A synchronous DRAM (Dynamic Random Access Memory; hereinafter referred to as “SDRAM” as appropriate) is a synchronous type that takes in an operation command in synchronization with a clock signal input to a clock input terminal and inputs / outputs data. DRAM. Since it can cope with the operation of a CPU that has recently been increased in speed, it is widely used as a main memory of a system.

  In addition, when data is written to or read from the SDRAM, the SDRAM control device outputs a command synchronized with the clock signal to the SDRAM. For example, when data is written to the SDRAM, the SDRAM control device first outputs an active command comprising a combination of command signals (for example, RAS signal, CAS signal, CS signal, WE signal) to the command terminal of the SDRAM. Also, the SDRAM control device outputs a row address (row address) signal to the address terminal of the SDRAM.

  Then, the SDRAM control device outputs a write command to the command terminal of the SDRAM after a RAS-CAS delay time (RAS-to-CAS Delay, hereinafter referred to as “tRCD”) has elapsed, and a column address (column address). ) Signal is output to the address terminal of the SDRAM. Further, the SDRAM control device outputs data to be written to the data terminal of the SDRAM.

Here, tRCD is a delay time from the output of an active command to the output of a read command / read command with auto precharge or a write command / write command with auto precharge, and is predetermined as SDRAM specifications. It has been. Therefore, after outputting the active command, the SDRAM control device needs to ensure a delay time satisfying the tRCD specification before outputting a read command or a write command. Specifically, the SDRAM control apparatus secures tRCD by outputting an active command to the SDRAM and then outputting a read command or a write command after a predetermined number of clocks (for example, Patent Document 1).
JP 2000-339956 A

  In recent years, the operating frequency has been increased by improving the performance of CPUs and the like. In this case, if the operation clock of the entire system is operated at high speed, the time required for one clock is shortened. For example, when the operating frequency is “33 MHz”, the time required for one clock is “30 ns”, but when the operating frequency is “100 MHz”, the time required for one clock is “10 ns”.

  Here, the SDRAM and the SDRAM control device operate in synchronization with the clock signal as described above. For example, consider a case where an SDRAM having a tRCD of “20 ns” as an SDRAM specification operates at an operating frequency of “33 MHz”. When the operating frequency is “33 MHz”, the time required for one clock is “30 ns”. Therefore, in order to secure tRCD, the SDRAM control device secures tRCD which is the specification of the SDRAM by outputting an active command to the SDRAM and then outputting a read command or a write command after one clock.

  However, when the same SDRAM and SDRAM control device are operated at an operating frequency (clock signal frequency) of “100 MHz”, the time required for one clock is “10 ns”. In this case, when the SDRAM control device outputs an active command and then outputs a read command or a write command after one clock, the tRCD that can be secured by the SDRAM is “10 ns”. Accordingly, tRCD “20 ns”, which is the SDRAM specification, cannot be secured. For this reason, there has been a problem that the SDRAM cannot be operated.

  In addition, in order to operate the SDRAM at a high speed, there is a problem that the SDRAM control apparatus currently used needs to be replaced with a SDRAM control apparatus compatible with the high speed operation by a repair worker or the like.

  An object of the present invention is to provide an SDRAM control device that can cope with a change in operating frequency, such as a higher operating frequency (frequency of a clock signal) in the same SDRAM and SDRAM control device.

In order to solve the above problem, the invention according to claim 1
In the synchronous DRAM control device that operates with the same clock signal as the synchronous DRAM,
A plurality of command generation circuits for generating a read command or a write command at different timings after generating an active command;
A selection circuit that selectively selects a command generation circuit from the plurality of command generation circuits according to the frequency of the clock signal;
And the synchronous DRAM is controlled by a command generated by a command generation circuit selected by the selection circuit.

  According to the first aspect of the present invention, the synchronous DRAM can be controlled by alternatively selecting a plurality of command generation circuits. Therefore, even when the operating frequency is changed, it is possible to control the operation of the synchronous DRAM by the same synchronous DRAM control device, and it is possible to cope with the change of the operating frequency.

  According to the present invention, the synchronous DRAM can be controlled by selectively selecting a plurality of command generation circuits. Therefore, even when the operating frequency is changed, it is possible to control the operation of the synchronous DRAM by the same synchronous DRAM control device, and it is possible to cope with the change of the operating frequency.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a configuration diagram of a system including an SDRAM control apparatus 1 according to an embodiment of the present invention. The SDRAM control device 1 is connected between the host bus 5 and the SDRAM 3. In addition, the clock signal 7 is input to the SDRAM control device 1 and the SDRAM 3 and operates with the same clock signal.

  The SDRAM control device 1 includes a command generation unit 10, a bus interface 20, a mode setting register 30, an address generator 40, and a data buffer 50.

  The command generation unit 10 is a circuit that generates a command for controlling the SDRAM 3. The command generation unit 10 includes a first command generation circuit 12a, a second command generation circuit 12b, and a selector 14.

  The first command generation circuit 12 a is a circuit that generates various commands for controlling the SDRAM 3. The selector 14, the address generator 40, and the data buffer 50 are connected to the output terminal of the first command generation circuit 12a. In addition, a control signal and a data signal are input to the first command generation circuit 12 a from the host bus 5 through the bus interface 20. As will be described in detail later, the first command generation circuit 12a is a circuit characterized in that it generates a read command or a write command after one clock has elapsed after generating an active command.

  Similarly to the first command generation circuit 12a, the second command generation circuit 12b is a circuit that generates various commands for controlling the SDRAM 3. The selector 14, the address generator 40, and the data buffer 50 are connected to the output terminal of the second command generation circuit 12a. In addition, a control signal and a data signal are input from the host bus 5 through the bus interface 20 to the second command generation circuit 12a. As will be described in detail later, the second command generation circuit 12b is characterized in that it generates a read command or a write command after two clocks have elapsed after generating an active command.

  The selector 14 has an input terminal connected to the first command generation circuit 12 a and the second command generation circuit 12 b, and an output terminal connected to the command terminal C of the SDRAM 3. The selector 14 constitutes a selection circuit that selects the first command generation circuit 12a and the second generation command circuit 12b. The selector 14 selects the first command generation circuit 12 a or the second command generation circuit 12 b based on the register value stored in the mode setting register 30 and outputs a command to the SDRAM 3.

  The bus interface 20 is an interface for connecting the host bus 5 and the SDRAM control device 1.

  The mode setting register 30 is a storage area in which the bus interface 20 is connected to the input terminal and the command generation unit 10 is connected to the output terminal. The mode setting register includes a register that stores a value in association with the operating frequency of the system and a command generation circuit to be selected. For example, when the operation frequency is “33 MHz”, the register value “1” associated with the first command generation circuit 12 a is stored. When the operation frequency is “100 MHz”, the register value “2” associated with the second command generation circuit 12 b is stored. The register value is a register that is set before the SDRAM control apparatus 1 operates. For example, the register value is stored at the time of factory shipment, or is stored / updated by a repair worker or a user. Needless to say, this register value storing / updating operation can be executed in software via the host bus 5.

  The address generator 40 outputs an address signal related to a row address or a column address to the SDRAM 3 based on signals input from the bus interface 20 and the command generator 10.

  The data buffer 50 is a temporary storage area that stores data when data is read from the SDRAM 3 and stores data when data is written to the SDRAM 3.

  In the SDRAM 3, the output terminal of the address generator 40 is connected to the address terminal A, the output terminal of the command generator 10 is connected to the command terminal C, and the input / output terminal of the data buffer 50 is connected to the data terminal D. A clock signal 7 is input from the clock terminal CK, and the SDRAM 3 is synchronized. In the present embodiment, the tRCD of the SDRAM 3 is described as “20 ns”, but the tRCD is not limited to this value.

  The basic operation principle of the SDRAM control device 1 will be described with reference to FIG. The first command generation circuit 12a is a circuit that outputs an active command and outputs a read command or a write command after one clock. The second command generation circuit 12b is a circuit that outputs an active command, then outputs a NOP command, and outputs a read command, a write command, or the like after two clocks. The selector 14 selects the first command generation circuit 12a when the value of the mode setting register is “1”, and selects the second command generation circuit 12b when the value of the mode setting register is “2”. To do.

  Here, when the operating frequency is “33 MHz” (the time required for one clock is “30 ns”), the register value is set to “1” in the mode setting register. Therefore, the selector 14 selects the first command generation circuit 12a. The first command generation circuit 12a outputs a read command or a write command after one clock after outputting the active command. Therefore, there is an interval of “30 ns” between the active command and the read command or the write command, and the tRCD “20 ns” of the SDRAM 3 can be ensured (FIG. 2A).

  When the operating frequency is “100 MHz” (the time required for one clock is “10 ns”), “2” is set in the mode setting register. Therefore, the selector 14 selects the second command generation circuit 12b. The second command generation circuit 12b outputs a read command, a write command, or the like after two clocks after outputting the active command. Therefore, there is an interval of “20 ns” between the active command and the read command or write command, and the tRCD “20 ns” of the SDRAM 3 can be ensured (FIG. 2B).

  Next, a specific example of the SDRAM control device 1 in the present embodiment will be described in detail using a timing chart.

(1) When the operating frequency (frequency of the clock signal) is 33 MHz First, the operation of the SDRAM control device 1 when the operating frequency is “33 MHz” (the time required for one clock is “30 ns”) is shown in FIGS. The description will be given with reference. The mode setting register 30 stores “1” indicating that the current operating frequency is “33 MHz” as a register value.

(A) Write Operation First, the case where the SDRAM control device 1 executes the write operation will be described with reference to the timing chart of FIG.

  First, the selector 14 reads the register value of the mode setting register 30. Since the current register value is “1”, the selector 14 selects the first command generation circuit 12a. As a result, the command generated by the first command generation circuit 12a is output to the command terminal C of the SDRAM 3.

  Therefore, at time A10, the active command (/ RAS signal = “Low”, / CAS signal = “Hi”, / CS signal = “Low”, / WE signal = generated by the first command generation circuit 12a. “Hi”) is output to the command terminal C of the SDRAM 3. The address generator 40 outputs a row address signal to the address terminal A of the SDRAM 3.

  Next, at time A12 after one clock, the write command (/ RAS signal = “Hi”, / CAS signal = “Low”, / CS signal = “Low”, / WE generated by the first command generation circuit 12a. Signal = “Low”) is output to the command terminal C of the SDRAM 3. Further, the column address signal generated by the address generator 40 is output to the address terminal A of the SDRAM 3. Then, the data D0 is taken into the SDRAM 3.

(B) Reading Operation Next, the case where the SDRAM control device 1 executes the reading operation will be described with reference to the timing chart of FIG.

  First, at time B10, the active command generated by the first command generation circuit 12a is output to the command terminal C of the SDRAM 3. Further, the address generator 40 outputs a row address signal to the SDRAM 3.

  Next, at time B12 after one clock, the write command (/ RAS signal = “Hi”, / CAS signal = “Low”, / CS signal = “Low”, / WE generated by the first command generation circuit 12a. Signal = “Hi”) is output to the command terminal C of the SDRAM 3. Further, the column address signal generated by the address generator 40 is output to the SDRAM 3.

  Next, the data D0 output from the SDRAM 3 is read at time B14 after two clocks, which is the CAS latency (tCL). Here, CAS latency refers to the number of clocks required from the read command to the time when data can be read, and is predetermined as the specification of the SDRAM 3. In the present embodiment, the CAS latency is “2”, but the present invention is not limited to this.

  As described above, according to FIGS. 3 and 4, when the operating frequency is “33 MHz”, the SDRAM control device 1 outputs a read command or a write command after one clock (30 ns) after outputting an active command. Therefore, “20 ns” can be secured as the tRCD of the SDRAM 3 and a command can be output to the SDRAM 3.

(2) When the operating frequency (frequency of the clock signal) is 100 MHz Next, the operation of the SDRAM control device 1 when the operating frequency is “100 MHz (the time required for one clock is“ 10 ns ”) will be described with reference to FIGS. The description will be given with reference. The mode setting register 30 stores “2” indicating that the current operating frequency is “100 MHz” as a register value.

(A) Write Operation First, the case where the SDRAM control device 1 executes the write operation will be described with reference to the timing chart of FIG.

  First, the selector 14 reads the register value of the mode setting register 30. Since the register value is currently “2”, the selector 14 selects the second command generation circuit 12b. As a result, the command generated by the second command generation circuit 12b is output to the command terminal C of the SDRAM 3.

  Therefore, the active command generated by the second command generation circuit 12b is output to the command terminal C of the SDRAM 3 at time C10. The row address generated by the address generator 40 is output to the address terminal A of the SDRAM 3.

  Next, the NOP signal (/ RAS signal = "Hi", / CAS signal = "Hi", / CS signal = "Low", / WE signal = "Hi") generated by the second command generation circuit 12b is It is output to the command terminal C of the SDRAM 3.

  Next, at time C12 after two clocks have elapsed, the write command generated by the second command generation circuit 12b is output to the command terminal C of the SDRAM 3. Further, the address generator 40 outputs a column address signal to the address terminal A of the SDRAM 3. Further, the data D0 is taken into the SDRAM 3.

(B) Reading Operation Next, the case where the SDRAM control device 1 outputs a read command will be described with reference to the timing chart of FIG.

  First, at time D10, the active command generated by the second command generation circuit 12b is output to the command terminal C of the SDRAM 3. Further, the row address signal generated by the address generator 40 is output to the address terminal A of the SDRAM 3.

  Next, the NOP signal generated by the second command generation circuit 12 b is output to the command terminal C of the SDRAM 3.

  Next, at time D12 after two clocks, the write command generated by the second command generation circuit 12b is output to the command terminal C of the SDRAM 3. Further, the address generator 40 outputs a column address signal to the address terminal A of the SDRAM 3.

  Next, the data D0 output from the SDRAM 3 is read at a time D14 after two clocks, which is CAS latency (tCL).

  As described above, according to FIGS. 5 and 6, when the operating frequency is “100 MHz”, the SDRAM control device 1 outputs a read command or a write command after two clocks (20 ns) after outputting an active command. Therefore, “20 ns” is secured as tRCD in the SDRAM 3 and a signal is output to the SDRAM 3.

  As described above, the SDRAM control device 1 can secure the tRCD of the SDRAM 3 regardless of whether the operating frequency is low or high. Therefore, it is possible to provide an SDRAM control device that can cope with a change in operating frequency, such as increasing the operating frequency (frequency of the clock signal) in the same SDRAM and SDRAM control device.

  Note that the values used for the operating frequency, tRCD, tCL, and the like in this embodiment are examples, and of course are not limited to these values. Also, the command generation circuit has been described as having two circuits in the present embodiment, but is not limited to two, and may have two or more generation circuits. Of course.

  For example, the operating frequency is “33 MHz” (time required for one clock is “30 ns”), “100 MHz” (time required for one clock is “10 ns”), “133 MHz” (time required for one clock is “7.5 ns”) ) Corresponding to the first command generation circuit, the second command generation circuit, and the third command generation circuit.

  The first command generation circuit is a circuit that outputs an active command and outputs a read command or a write command after one clock (30 ns). The second command generation circuit is a circuit that outputs an active command and outputs a read command or a write command after two clocks (20 ns). The third command generation circuit is a circuit that outputs an active command and outputs a read command or a write command after 3 clocks (22.5 ns). The selector selects the first command generating circuit when the operating frequency is “33 MHz”, selects the second command generating circuit when the operating frequency is “100 MHz”, and selects the first command generating circuit when the operating frequency is “133 MHz”. 3 command generation circuits are selected. Therefore, even when the operating frequency is changed, tRCD (20 ns) of the SDRAM can be ensured, and it is possible to provide an SDRAM control device that can handle a plurality of operating frequencies.

It is the figure which showed the structure of the system containing an SDRAM control apparatus. It is a figure which shows the basic operation | movement of a 1st command generation circuit and a 2nd command generation circuit. 6 is a time chart showing an operation when a write command is output to the SDRAM during low-speed operation. 6 is a time chart showing an operation when a read command is output to the SDRAM during low-speed operation. 6 is a time chart showing an operation when a write command is output to the SDRAM during high-speed operation. 6 is a time chart showing an operation when a read command is output to the SDRAM during high-speed operation.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 SDRAM control apparatus 10 Command generation part 12a 1st command generation circuit 12b 2nd command generation circuit 14 Selector 20 Bus interface 30 Mode setting register 40 Address generator 50 Data buffer

Claims (1)

In the synchronous DRAM control device that operates with the same clock signal as the synchronous DRAM,
A plurality of command generation circuits for generating a read command or a write command at different timings after generating an active command;
A selection circuit that selectively selects a command generation circuit from the plurality of command generation circuits according to the frequency of the clock signal;
And a synchronous DRAM control device that controls the synchronous DRAM with a command generated by a command generation circuit selected by the selection circuit.

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