JP2004192202A - Clock signal distributing circuit and semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock signal distributing circuit for suppressing through-currents generated synchronously with a clock signal, and for effectively reducing the deterioration of a power supply voltage or EMI even in a semiconductor integrated circuit having a largely scaled circuit block whose integration level is high. <P>SOLUTION: This clock signal distributing circuit is configured to distribute and supply a clock signal supplied from a clock signal supply source to a plurality of circuit blocks A, B and C operating synchronously with a clock signal. This clock signal distributing circuit is provided with a delay clock signal generating part 3 for delaying a clock signal C<SB>0</SB>supplied from the clock signal supply source, and for generating and outputting a plurality of delay clock signals C<SB>1</SB>, C<SB>2</SB>and C<SB>3</SB>whose delay values are different from each other and a distributing part 4 for selectively switching the plurality of delay clock signals C<SB>1</SB>, C<SB>2</SB>, and C<SB>3</SB>whose delay values are different based on the clock signal C<SB>0</SB>, and for respectively distributing them to the circuit blocks A, B and C. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a clock signal distribution circuit that distributes a clock signal to a plurality of circuit blocks and a semiconductor integrated circuit including the clock signal distribution circuit.
[0002]
[Prior art]
An ASIC (Application Specific Integrated Circuit) is an integrated circuit designed for use in a specific application of a specific user. The ASIC internal circuit includes a logical sum (OR), a logical product (AND), a logical NOT (NOT), a flip-flop that operates in synchronization with a clock signal, and the like in which a plurality of CMOS transistors (hereinafter, referred to as “transistors”) are combined. Is composed of theoretical cells.
[0003]
In recent years, there are some ASICs in which all the functions of the system desired by the user are incorporated, and such ASICs are configured by including circuit blocks such as a microprocessor, a memory, and an interface on one chip. The transistors constituting each circuit block are switched in synchronization with a clock signal supplied from a clock supply source, so that a current flows between a drain and a source and a capacitor in the circuit block is charged and discharged.
[0004]
Due to the configuration of the transistor, a current flows from the power supply to GND at the time of state transition. This current is called a through current. Among the theoretical cells that constitute the circuit, flip-flops, in particular, perform state transitions in synchronization with the rising edge of a clock signal. An appropriate number of transistors will transition, and a large through current will flow through the ASIC as shown in FIG.
[0005]
The generation of the through current causes a decrease in the power supply voltage in the ASIC, which causes an increase in power consumption and a malfunction of another circuit provided on the same circuit board as the ASIC. In addition, the harmonic component of the through current also becomes a noise source, and may cause radiated electromagnetic noise (Electromagnetic Inference, hereinafter referred to as “EMI”) to other circuits and devices. For this reason, the EMI must be reduced to a value less than or equal to a standard value defined by a domestic standard such as VCCI or an international standard such as IEC.
[0006]
Some ASICs include a clock signal distribution circuit that provides a clock signal supplied from a clock supply source at a different timing for each circuit block in order to reduce the influence caused by the through current. As an example, as shown in FIG. 5, when the ASIC has three circuit blocks X, Y, and Z, a delay formed by connecting three delay elements for delaying a clock signal C supplied from a clock supply source in series. A clock signal generator is provided, and the delayed clock signal C _X output from the first-stage delay element is applied to the circuit block X, and the delayed block signal C _Y output from the second-stage delay element is applied to the circuit block Y. that the delayed clock signal C _Z output from the delay elements of the stage to be supplied to the circuit block Z are known (e.g., see Patent Document 1.).
[0007]
Since the delay values of the delayed clock signals C _X , C _Y , and C _Z are different from each other, the timings at which the operations of the circuit blocks X, Y, and Z start are also shifted. As a result, as shown in FIG. 6, the timing at which a through current occurs in each of the circuit blocks X, Y, and Z differs according to the timing of each of the delayed clock signals C _X , C _Y , and C _Z. Compared to the case shown, the peak value of the amount of through current generated can be greatly reduced. The delay value of each of the delayed clock signals C _X , C _Y , and C _Z is set within a range that guarantees the setup time and the hold time of the flip-flop provided in each circuit block. The synchronization of the ASIC with the signal is maintained.
[0008]
[Patent Document 1]
JP-A-11-111854
[Problems to be solved by the invention]
However, the in the conventional clock signal distribution circuit (Patent Document 1), to supply delay to the circuit block X clock signal C _x, the circuit block Y to the delay clock signal C _Y, the circuit block Z the delayed clock signal C _Z respectively The clock signals supplied to the circuit blocks X, Y, and Z are fixed. Therefore, as shown in FIG. 6, every time a clock signal is supplied from the clock supply source to the ASIC, a through current always occurs in the same phase. For example, if there is a difference in the degree of integration of the circuit blocks and the amount of through current generated is large compared to other circuit blocks like the circuit block Z, the power supply voltage drop and EMI still occur due to the through current generated from the circuit block Z. This could have been very difficult to mitigate.
An object of the present invention is to provide a clock signal distribution circuit capable of effectively reducing a power supply voltage drop and EMI even in a semiconductor integrated circuit having a large-scale circuit block with a high degree of integration, and a semiconductor having the same. It is to provide an integrated circuit.
[0010]
[Means for Solving the Problems]
In order to solve the above problem, an invention according to claim 1 is a clock signal distribution circuit that distributes a clock signal supplied from a clock signal supply source to a plurality of circuit blocks operating in synchronization with a clock signal. A delay clock signal generation unit that delays a clock signal supplied from the clock signal supply source, generates and outputs a plurality of delay clock signals having different delay values, and generates a different delay value based on the clock signal. And a distributing unit for selectively switching the plurality of delayed clock signals to distribute to each of the circuit blocks.
[0011]
According to the first aspect of the present invention, the clock signal distribution circuit supplies a delayed clock signal having a different delay value to each circuit block, and based on the clock signal supplied from the clock signal supply source, Since the delay clock signal supplied to the circuit block is selectively switched to a delay clock signal having a different delay value, the timing at which each circuit block operates can be set to a different timing every time a clock signal is input from a clock supply source. it can. Since the clock signal is input in units of n seconds, macroscopically, the through current generated at the start of operation in each circuit block appears as an average, and a large-scale circuit block having a high degree of integration is required. Even if it has one, the effect of the through current generated by it can be reduced. Therefore, it is possible to reduce the peak value of the through current in the entire circuit, thereby preventing the power supply voltage from lowering and reducing the EMI.
[0012]
According to a second aspect of the present invention, in the clock signal distribution circuit according to the first aspect, the distribution unit supplies each of the circuit blocks in synchronization with an inverted signal of a delayed clock signal having a maximum delay value. The delay clock signal is selectively switched.
[0013]
According to the second aspect of the present invention, the distributing unit selectively switches the delay clock signals to be supplied to the respective circuit blocks in synchronization with the inverted signal of the delay clock signal having the maximum delay value, and performs another switching. When using a delayed clock signal having a delay value, the timing of this switching operation can be shifted from the timing at which each circuit block starts operating with the delayed clock signal. Thereby, malfunction of each circuit block can be prevented.
[0014]
According to a third aspect of the present invention, there is provided a semiconductor integrated circuit including a plurality of circuit blocks operating in synchronization with a clock signal, wherein the semiconductor integrated circuit includes the clock signal distribution circuit according to the first or second aspect. Features.
[0015]
According to the third aspect of the present invention, even with a semiconductor integrated circuit having a plurality of circuit blocks having independent functions on one chip, the clock signal distribution circuit according to the first or second aspect provides The operation timing of each circuit block can be shifted, and the operation timing of each circuit block can be changed every time a clock signal is input. Therefore, the peak value of the amount of through current generated can be reduced, the power supply voltage can be prevented from lowering, and EMI can be reduced.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, the configuration will be described.
FIG. 1 shows an ASIC 1 as a semiconductor integrated circuit according to the present embodiment. The ASIC 1 is an integrated circuit designed to be used for a specific application of a specific user, as described above, and includes a plurality of circuit blocks A, B, and C.
Each of the circuit blocks A, B, and C includes AND, OR, NOT, a theoretical cell of a flip-flop that operates in synchronization with a clock signal, and the like.
[0017]
In the present embodiment, as schematically shown in FIG. 1, it is assumed that there is a difference in the degree of integration (scale) of each of the circuit blocks A, B, and C. Description will be made on the assumption that the circuit block A> the circuit block B.
[0018]
ASIC1, said circuit blocks A, B, other C, includes a clock source supplied from (not shown) clock signal C ₀ each circuit block A, B, the distribution and supplies the clock signal distribution circuit 2 to C I have.
[0019]
The clock signal distribution circuit 2 delays the clock signal C ₀ to generate and output a plurality of delayed clock signals C ₁ , C ₂ , and C ₃ having different delay values, and a delayed clock signal generator 3 And a distribution unit 4 for distributing the delayed clock signals C ₁ , C ₂ , and C ₃ generated as described above to the respective circuit blocks A, B, and C as internal clock signals (D ₁ , D ₂ , and D ₃ ). I have.
[0020]
The delay clock signal generator 3 is configured by three delay elements 31, 32, and 33 connected in series. Clock signal _{C 0} is supplied to the delay element 31 of the first stage of the three delay elements 31, 32 and 33. The delay element 31 delays the clock signal C ₀ to generate a _first delayed clock signal C _1, and outputs the first delayed clock signal C ₁ to the second-stage delay element 32 and the distribution unit 4.
[0021]
The second-stage delay element 32 further delays the first delayed clock signal C ₁ to generate a _second delayed clock signal C _2, and outputs the second delayed clock signal C ₂ to the third-stage delay element 33 and the distribution unit 4. The third-stage delay element 33 further delays the second delayed clock signal C ₂ to generate a _third delayed clock signal C _3, and outputs the third delayed clock signal C ₃ to the distribution unit 4.
[0022]
Note that the delay values of the respective delayed clock signals C ₁ , C ₂ , and C _{3 from} the clock signal are as follows: first delayed clock signal C ₁ <second delayed clock signal C ₂ <third delayed clock signal C ₃ . Each is set within a range that satisfies the setup time and the hold time of the flip-flop provided in each of the circuit blocks A, B, and C.
[0023]
The distribution unit 4 includes an inverter 41 that generates and outputs an inverted signal U of the third delayed clock signal C3, a selection signal generation counter 42 that generates and outputs a selection signal S in response to the input of the inverted signal U, A selector 43 for selectively switching the delayed clock signals C ₁ , C ₂ , and C ₃ distributed to the circuit blocks A, B, and C to distribute a predetermined delayed clock signal to the predetermined circuit blocks. ing.
[0024]
The inverter 41 is connected between the output terminal of the third-stage delay element 33 and the input terminal of the selection signal generation counter 42. Inverter 41 inverts the third delayed clock signal C ₃ supplied from the delay element 33, and supplies the generated inverted signal U to the selection signal generating counter 42.
[0025]
The selection signal generation counter 42 generates and outputs a selection signal S in synchronization with the rising edge of the supplied inverted signal U.
[0026]
The selection signal generation counter 42 increases the count value in the order of 0 to 1 and 2 each time the inverted signal U is input, and when counting up to 2, the count value returns to 0 by the next input inverted signal U. The selection signal S indicates the count value of the selection signal generation counter 42, and indicates one of 0, 1, and 2. The selection signal S instructs the selector 43 to distribute the input delayed clock signals C ₁ , C ₂ , and C ₃ to the circuit blocks A, B, and C. The details of the selection signal S will be described later.
[0027]
The selector 43 has an input terminal to which the delayed clock signals C ₁ , C ₂ , C ₃ and the selection signal S are input, and an output terminal connected to the input terminals of the circuit blocks A, B, C. The selector 43 switches the connection between the input terminal to which each of the delayed clock signals C ₁ , C ₂ , and C ₃ is input and the output terminal in the selector 43 in accordance with the content specified by the selection signal S.
[0028]
Output signal to be supplied to the circuit block A from the selector 43 is selected delayed clock signal D ₁ of the circuit block A, the output signal supplied to the circuit block B from the selector 43 is selected delayed clock signal D ₂ of the circuit block B There, the output signal supplied to the circuit block C from the selector 43 is the select delayed clock signal D ₃ of the circuit blocks C.
[0029]
Here, the selection signal S and the selection delay clock signals D ₁ , D ₂ , and D ₃ will be described. When the count value of the selection signal generating counter 42 indicated by the selection signal is 0, for example, to the first delay clock signal C ₁ of the circuit block A, the second delayed clock signal C ₂ to the circuit block B, the third It becomes that instructs to switch the connection of the selector 43 to supply the delayed clock signal C ₃ to the circuit block C. This is indicated as a data string “A, B, C” in FIG.
[0030]
Therefore, when the selection signal S is represented by “A, B, C”, the selected delay clock signal D ₁ of the circuit block A becomes the first delay clock signal C ₁ and the selection delay of the circuit block B clock signal D ₂ becomes the second delayed clock signal C _2, selected delayed clock signal D ₃ of the circuit block C is third delayed clock signal C _3.
[0031]
When the count value indicated by the selection signal S is 1, in FIG. 2, it is displayed as, for example, "C, A, B". The selector 43 supplies the first delayed clock signal C ₁ to the circuit block C, the second delayed clock signal C ₂ to the circuit block A, and the third delayed clock signal C ₃ to the circuit block B. Is to be switched.
[0032]
Thus, selection delayed clock signal D ₁ of the circuit block A becomes the second delayed clock signal C _2, selected delayed clock signal D ₂ of the circuit block B becomes the third delayed clock signal C _3, the circuit block C selection delayed clock signal D ₃ of the made to the first delay clock signal C _1.
[0033]
When the count value indicated by the selection signal S is 2, for example, it is displayed as “B, C, A” in FIG. This means that, similarly to the above, the first delayed clock signal C ₁ is supplied to the circuit block B, the second delayed clock signal C ₂ is supplied to the circuit block C, and the third delayed clock signal C ₃ is supplied to the circuit block A. Instruct the connection of the selector 43 to be switched.
[0034]
As a result, the selected delayed clock signal D ₁ of the circuit block A becomes the third delayed clock signal C ₃ , the selected delayed clock signal D ₂ of the circuit block B becomes the first delayed clock signal C ₁ , and the circuit block C selection delayed clock signal D ₃ of becomes the second delayed clock signal C _2.
[0035]
Next, the operation of the ASIC 1 described above will be described.
When the clock signal C ₀ is supplied from the clock signal supply source to the clock signal distribution circuit 2, the delay elements 31, 32, and 33 of the delay unit 3 cause the first delay elements having different delay values from each other as shown in FIG. A clock signal C ₁ , a second delayed clock signal C ₂ , and a third delayed clock signal C ₃ are generated. These delayed clock signals C ₁ , C ₂ , and C ₃ are input to the selector 43.
[0036]
The third delayed clock signal _{C 3} is input to the inverter 41 with the selector 43. Inverter 41 inverts _third delayed clock signal C3 to generate inverted signal U as shown in FIG. The generated inverted signal U is output to the selection signal generation counter 42.
[0037]
The selection signal generation counter 42 counts in synchronization with the rising edge of the inverted signal U, generates a selection signal S having a value corresponding to the count value, and outputs the selection signal S to the selector 43.
[0038]
When the count value indicated by the selection signal S is 0, the selection signal S is displayed as “A, B, C” as described above. Thus the selector 43 supplies the first delayed clock signal C ₁ as the selected delayed clock signal D ₁ to the circuit block A, circuit block A operates in synchronization with the rising edge of the selection delayed clock signal D1.
[0039]
Similarly, the circuit block B is supplied the second delayed clock signal C _2, circuit block B operates in synchronization with the second rising edge of the delayed clock signal C _2. Furthermore the circuit block C is supplied a third delayed clock signal C _3, the circuit block C operates in synchronization with the third rising edge of the delayed clock signal C _3. With the operation of each of the circuit blocks A, B, and C, a through current is generated in the order of the circuit block A, the circuit block B, and the circuit block C as shown in FIG.
[0040]
When the next clock signal is input to the clock signal distribution circuit 2 from the clock supply source, the count value of the selection signal generation counter 42 becomes 1, and the selection signal S is changed to one indicated by “C, A, B”. Become.
[0041]
The selector 43 switches the internal connection according to the selection signal S, and supplies the first delayed clock signal C ₁ to the circuit block C, the second delayed clock signal C ₂ to the circuit block A, and the third delayed clock signal each distributing C ₃ to the circuit block B. Each of the circuit blocks A, B, and C sequentially operates according to the input delayed clock signals C ₂ , C ₃ , and C ₁ . Accordingly, a through current is generated in the order of the circuit block C, the circuit block A, and the circuit block B.
[0042]
When the clock signal _C0 is further supplied from the clock supply source, the count value of the selection signal generation counter 42 becomes 2, and the selection signal S is displayed as "B, C, A". The selector 43 sequentially supplies the first delayed clock signal C ₁ to the circuit block B, the second delayed clock signal C ₂ to the circuit block C, and the third delayed clock signal C ₃ in response to the selection signal S. The internal connection is switched so as to supply the circuit block A.
Each of the circuit blocks A, B, and C operates according to the supplied delayed clock signals C ₃ , C ₁ , and C _2, and accordingly, a through current flows through the circuit block B, the circuit block C, and the circuit block A in this order. Occurs.
[0043]
According to the ASIC 1 described above, since the clock signal distribution circuit 2 is provided, the delay clock signals having different delay values are supplied to the circuit blocks A, B, and C as the selected delay clock signals D ₁ , D ₂ , and D _3. This prevents each of the circuit blocks A, B, and C from starting to operate simultaneously, thereby dispersing the amount of through current generated.
[0044]
Further, it is possible to change the generation timing of the selected delay clock signals D ₁ , D ₂ , D ₃ based on the clock signal C ₀ supplied from the clock supply source. That is, the selected delay clock signal D ₁ of the circuit block A changes in the order of the first delay clock signal C ₁ , the second delay clock signal C ₂ , and the third delay clock signal C ₃ , and the selection delay of the circuit block B The clock signal D ₂ changes in the order of the second delayed clock signal C ₂ , the third delayed clock signal C ₃ , and the first delayed clock signal C ₁ , and the selected delayed clock signal D ₃ of the circuit block C is the third delayed clock signal D ₃ . The delay clock signal C ₃ , the first delay clock signal C ₁ , and the second delay clock signal C ₃ change in this order.
[0045]
The circuit block synchronized with each of the delayed clock signals C ₁ , C ₂ , and C ₃ is switched every clock, and as shown in FIG. 3, macroscopically, each of the delayed clock signals C ₁ , C ₂ , and C ₃ is switched. The through current generated in each circuit block at the rising edge (change point) is averaged and appears. Therefore, even when the ASIC 1 includes a large-scale block with a high degree of integration such as the circuit block C, the influence of the through current generated by the circuit block C can be reduced by the other circuit blocks A and B. For this reason, the reduction in the peak value of the through current as a whole of the ASIC 1 can prevent the power supply voltage from lowering and reduce EMI.
[0046]
Further, by generating the selection signal S delay value selection signal generating counter 42 in synchronization with the inverted signal U of the third delayed clock signal C ₃ having the maximum respective delayed clock signals C _1, C _2, C _When the signal level of the signal No. ₃ is “low”, the internal connection of the selector 43 is switched to switch the delay clock signal supplied to each circuit block A, B, C. Therefore, it is possible to prevent the selector 43 from erroneously operating when switching the connection, and to ensure that each of the delayed clock signals C ₁ , C ₂ , and C ₃ input to the input terminals has a predetermined value in accordance with the content of the selection signal S. It can be distributed to circuit blocks.
[0047]
Further, the timing of switching the connection inside the selector 43 and the timing of starting operation of each of the circuit blocks A, B, and C by the delayed clock signal can be shifted, so that generation of noise due to simultaneous switching can be prevented. In addition, malfunction of each of the circuit blocks A, B, and C can be prevented.
[0048]
The delay value of each of the delayed clock signals C ₁ , C ₂ , and C ₃ is within a range that satisfies the setup time and the hold time of the flip-flop provided in each of the circuit blocks A, B, and C. , B, and C, the synchronization of the entire ASIC 1 can be maintained.
[0049]
It should be noted that the present invention is not limited to the above-described embodiment, and can be modified as appropriate without departing from the spirit of the present invention.
For example, the number of circuit blocks included in the ASIC 1 and the number of delay elements included in the delay unit 3 are not limited. The configuration of the delay unit 3, as long as the clock signal C ₀ supplied from the clock signal supply source can generate a plurality of delayed clock signals having different delay values, being limited to the above structure Absent.
[0050]
Further, the count value indicated by the selection signal S and the delay clock signals C ₁ , C ₂ , and C ₃ that the selector 43 supplies to the circuit blocks A, B, and C, respectively, are predetermined, but are not limited thereto. Not something. The distribution unit 4 distributes the plurality of delayed clock signals C ₁ , C ₂ , and C ₃ having different delay values generated by the delayed clock generation unit 3 to the circuit blocks A, B, and C based on the selection signal S. Any configuration can be used as long as it can selectively switch the delayed clock signal to a delayed clock signal having a different delay value.
[0051]
【The invention's effect】
According to the first aspect of the present invention, a delay clock signal having a different delay value is supplied to each circuit block, and a delay clock supplied to each circuit block based on a clock signal supplied from a clock signal supply source. Since the signal is selectively switched to the delayed clock signal having another delay value, the timing at which each circuit block operates can be different every time a clock signal is input from the clock supply source. When the clock signal is viewed macroscopically, the through current generated at the start of operation in each circuit block will appear on average, and even if a large-scale circuit block with a high degree of integration is provided, the through current will occur. The effect of the current can be reduced. Therefore, it is possible to reduce the peak value of the through current in the entire circuit, thereby preventing the power supply voltage from lowering and reducing the EMI.
[0052]
According to the second aspect of the present invention, the same effects as those of the first aspect can be obtained, and the distributing section can synchronize each circuit block with the inverted signal of the delayed clock signal having the maximum delay value. Since the supplied delayed clock signal is switched to the delayed clock signal having another delay value, the timing of the switching operation of the distribution unit and the timing of starting the operation of each circuit block by the delayed clock signal can be shifted. Thereby, malfunction of each circuit block can be prevented.
[0053]
According to the third aspect of the present invention, even if the semiconductor integrated circuit includes a plurality of circuit blocks having independent functions, each circuit block operates by the clock signal distribution circuit according to the first or second aspect. And the timing at which each circuit block operates can be changed each time a clock signal is input. Therefore, the peak value of the amount of through current generated can be reduced, the power supply voltage can be prevented from lowering, and EMI can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a circuit configuration of an example of a clock signal distribution circuit and a semiconductor integrated circuit according to the present invention.
FIG. 2 is a diagram showing waveforms of various signals generated by the clock signal distribution circuit of FIG.
FIG. 3 is a diagram macroscopically showing a waveform of a through current generated with each of the delayed clock signals C ₁ , C ₂ , and C ₃ .
FIG. 4 is a waveform diagram showing a state of occurrence of a conventional through current.
FIG. 5 is a block diagram showing a conventional clock signal distribution circuit.
FIG. 6 is a diagram showing waveforms of various signals generated by a conventional clock signal distribution circuit.
[Explanation of symbols]
1 ASIC (semiconductor integrated circuit)
2 clock signal distribution circuit 3 delay clock signal generation unit 31 delay element 32 delay element 33 delay element 4 distribution unit 41 inverter 42 selection signal generation counter 43 selector C ₀ clock signal C ₁ delay clock signal C ₂ delay clock signal C ₃ delay clock Signal D ₁ Selected delayed clock signal D ₂ Selected delayed clock signal D ₃ Selected delayed clock signal S Selected signal

Claims (3)

A clock signal distribution circuit that distributes a clock signal supplied from a clock signal supply source to a plurality of circuit blocks operating in synchronization with the clock signal,
A delayed clock signal generating unit that delays a clock signal supplied from the clock signal supply source and generates and outputs a plurality of delayed clock signals having different delay values from each other;
A distributing unit that selectively switches a plurality of delayed clock signals having different delay values and distributes the delayed clock signals to the respective circuit blocks based on the clock signal;
A clock signal distribution circuit, comprising: The clock signal distribution circuit according to claim 1,
A clock signal distribution circuit, wherein the distribution unit selectively switches a delay clock signal to be supplied to each circuit block in synchronization with an inverted signal of a delay clock signal having a maximum delay value. In a semiconductor integrated circuit having a plurality of circuit blocks operating in synchronization with a clock signal,
A semiconductor integrated circuit comprising the clock signal distribution circuit according to claim 1.

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