JP2004112310A - Transistor circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a transistor circuit capable of shifting a level of an input signal at a high speed and providing an output with low power consumption. <P>SOLUTION: A voltage drop circuit P2 provided between a power terminal and a power line of a signal input circuit 12 and producing a voltage drop between both terminals and a switch circuit P3 turned ON / OFF in response to an output of the signal input circuit 12 are connected in parallel. The voltage drop circuit P2 drops a voltage at the power terminal of the signal input circuit 12 when a high level is given to the signal input circuit 12 to prevent a through current flowing to the signal input circuit 12 and when a low level is given to the signal input circuit 12, the switch circuit P3 boosts a voltage at the power terminal of the signal input circuit 12 to ensure a high level of the output. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a transistor circuit. In particular, the present invention relates to a level shift circuit which is configured by a CMOS including a P-channel type MOS transistor and an N-channel type MOS transistor and shifts the level of an input signal voltage to output.
[0002]
[Prior art]
In recent years, in order to reduce power consumption and because the withstand voltage of elements decreases as semiconductor integrated circuits become more highly integrated and miniaturized, the voltage of internal circuits has been reduced, and the power supply voltage of internal circuits has been reduced to 1.5V. Some semiconductor integrated circuits using the same have appeared. However, a signal having a voltage of 3.3 V or 5.0 V is conventionally used for an interface between the semiconductor integrated circuit and the outside. Therefore, a power supply voltage of 3.3 V or 5.0 V is applied to an external interface circuit that performs input / output with the outside, and the level of a 1.5 V signal from the internal circuit is converted to 3.3 V or 5.0 V. It is common to incorporate a level shift circuit for outputting to the outside.
[0003]
This conventional level shift circuit will be described with reference to the drawings. FIG. 9 is a block diagram of a level shift circuit of Conventional Example 1 (for example, see Patent Document 1). The level shift circuit shown in FIG. 9 is a crossover circuit composed of CMOS inverters I101 and I102 operating with a 1.5V power supply, N-channel MOS transistors N101 and N102, and P-channel MOS transistors P101 and P102. It comprises a CMOS inverter I103 that operates on a power supply. 0V is applied to the grounds of these circuits, and 1.5V power is supplied to the inverters I101 and I102, and 3.3V power is supplied to the crossing circuit and the inverter I103. Here, the N-channel MOS transistors N101 and N102 and the P-channel MOS transistors P101 and P102 have the same driving capability, and the N-channel MOS transistors N101 and N102 have the same driving capability. The size of the transistor is set so as to have a considerably larger driving capability than P102.
[0004]
Next, the operation of the level shift circuit of the conventional example 1 will be described. FIG. 10 is a waveform diagram of the level shift circuit of FIG. In the initial state t20, a low level of 0 V is applied to the input IN of the inverter I101. At this time, the output point D of the inverter I101 becomes high and the gate electrode of the N-channel MOS transistor N101 becomes 1.5V. The channel MOS transistor N101 is on. Since the output of the inverter I102 is at a low level, the N-channel MOS transistor N102 is off, the P-channel MOS transistor P101 is off, and the P-channel MOS transistor P102 is conducting. At this time, the point E is 0 V, the point F is 3.3 V, the voltage of the output OUT is 0 V, and a low level is output.
[0005]
Next, when the input IN rises, the output point D of the inverter I102 starts falling at the timing t21 in response thereto, and the output voltage of the inverter I102 increases in response thereto. When the output voltage of the inverter I102 rises to about 0.8 V corresponding to the threshold voltage of the N-channel MOS transistor N102, the N-channel transistor N102 starts conducting, and the point F is determined by the balance of the on-resistance with the conducting P-channel transistor P102. Starts dropping from 3.3 V (timing t22). However, the voltage at point E remains at 0 V at the timing of t22. Subsequently, when the potential at the point F drops to about 2.5V, the P-channel MOS transistor P101 starts conducting, and the potential at the point E starts rising from 0V. When the potential at the point E rises to about 2.5 V, the P-channel MOS transistor P102 turns off, the potential at the point F falls to 0 V, and a stable high level of 3.3 V is output from the output OUT (timing t23).
[0006]
Next, when the input IN falls from the high level 1.5V to the low level 0V, the output point D of the inverter I101 starts increasing from 0V to 1.5V (timing t24). When the potential at the point D exceeds about 0.8 V, the N-channel MOS transistor N101 starts to conduct, and the potential at the point E gradually increases from 3.3 V due to the balance of the on-resistance with the P-channel transistor P101 in the conducting state. The descent is started (timing t25). When the point D goes high, the output of the inverter I102 goes low, turning off the N-channel MOS transistor N102. Subsequently, when the potential at the point E drops to about 2.5 V, the P-channel MOS transistor P102 starts to conduct, the potential at the point F rises from 0 V, and when the potential at the point F reaches about 2.5 V, P The channel MOS transistor P101 turns off, the potential at the point E drops to 0V, the point F outputs a stable low level of 3.3V, and the OUT outputs a stable low level of 0V (timing t26).
[0007]
In the level shift circuit of the conventional example 1, no current flows when switching is not performed, but at the time of switching, the P-channel MOS transistor and the N-channel MOS transistor (P101 and N101, and P102 and N102) connected in series conduct simultaneously. Then, a pull-through timing occurs, so that a through current flows and the switching operation is delayed.
[0008]
Next, a level shift circuit different from the first conventional example will be described as a second conventional example. The prior art 2 is a known circuit whose document name cannot be specified.
[0009]
FIG. 11 is a block diagram of the second conventional example, which comprises four stages of CMOS inverters I111 to I114 connected in series. Here, the CMOS inverters I111, I113, and I114 are ordinary CMOS inverters each having one P-channel MOS transistor and one N-channel MOS transistor whose gate electrode and drain electrode are commonly connected, respectively. As shown in the figure, it is composed of two P-channel MOS transistors P111 and P112 and one NMOS transistor connected in series. Here, the size of the N-channel MOS transistor N111 is set so as to have a considerably larger driving capability than the P-channel MOS transistors P111 and P112. 1.5 V is supplied to the inverter I111 and 3.3 V is supplied to the inverters I112 to I114. The ground is common at 0V.
[0010]
Next, the operation of the level shift circuit of FIG. 11 will be described with reference to a timing chart of FIG. In the initial state t30, the input IN to the inverter I111 is 0V, and the potential at the output G of the inverter I111 is 1.5V. At this time, the P-channel MOS transistors P111 and P112 and the N-channel MOS transistor N111 are all turned on, and a through current flows steadily. However, as described above, the N-channel MOS transistor N111 is larger than the P-channel MOS transistors P111 and P112. Since it has the driving capability, the potential at the output H point of the inverter I112 is close to 0V. Therefore, the output of the inverter I113 is at a high level of 3.3V, and the output OUT of the inverter I114 is at a low level of 0V.
[0011]
Next, when the voltage of the input IN to the inverter I111 changes from 0V to 1.5V at t31, the point G becomes 0V, the N-channel MOS transistor N111 turns off, and the inverter I112 enters a state where no through current flows. The voltage at point H rises to 3.3V. When the voltage at the point H rises to 3.3 V, the output of the inverter I113 becomes 0 V as the voltage rises, and the output OUT of the inverter I114 outputs a high level of 3.3 V.
[0012]
Thereafter, when the voltage of the input IN to the inverter I111 changes from 1.5V to 0V at t32, the state returns to the initial state, a through current flows to the inverter I112, and 0V is output to the output OUT. .
[0013]
Next, as a third conventional example, a transistor circuit that converts a TTL level signal into a CMOS level signal will be described (for example, see Patent Document 2). FIG. 13 is a block diagram of this conventional transistor circuit. This transistor circuit includes a CMOS inverter I121 including a P-channel MOS transistor P121 and an N-channel MOS transistor N121, a CMOS inverter I122 including a P-channel MOS transistor P122 and an N-channel MOS transistor N122, and a source electrode connected to the source of the P-channel MOS transistor P121. An N-channel MOS transistor N123 in which the drain electrode is connected to the positive power supply VCC and the gate electrode is connected to the reference bias power supply VR, the source electrode is the positive power supply VCC, the drain electrode is the output of the inverter I121, and the gate electrode is the output of the inverter I122. And a P-channel MOS transistor P123 connected to the Here, 5V is applied to the positive power supply VCC, and the grounds of the inverters I121 and I122 are common to 0V.
[0014]
Next, the operation of the transistor circuit of Conventional Example 3 will be described. Since this transistor circuit is a circuit that converts a TTL level signal to a CMOS level signal, the input voltage of I121 when receiving a low level signal is 0.8V. At this time, since the N-channel MOS transistor N121 is turned off and the P-channel MOS transistor P121 is turned on, the inverter I121 outputs a voltage higher than the input threshold level of the inverter I122. Therefore, the output of the inverter I122 becomes almost 0V, the P-channel MOS transistor P123 is turned on, the output of the inverter I121 is raised to the high level 5V, and the output of the inverter I122 is stabilized at the low level 0V.
[0015]
Next, when the input voltage of the inverter I121 changes from low level 0.8V to TTL level 2.2V, the positive power of the inverter I121 is supplied via the N-channel MOS transistor N123 whose gate electrode is connected to the reference bias power supply VR. Therefore, the gate-source voltage of the P-channel MOS transistor P121 becomes lower than the threshold level of the P-channel MOS transistor P121, the P-channel MOS transistor P121 is turned off, and the N-channel MOS transistor N121 is turned on. Here, since the P-channel MOS transistor P123 is on, the P-channel MOS transistor P123 and the N-channel MOS transistor N121 are simultaneously turned on, and the power supply VCC passes through the P-channel MOS transistor P123 and the N-channel MOS transistor N121 to ground. Through current flows through At this time, the input voltage of the P inverter I122 is a voltage obtained by dividing the voltage VCC by the source-drain voltage of the P-channel MOS transistor P123 and the source-drain voltage of the N-channel MOS transistor N121. Since the driving capability of MOS transistor N121 is set higher than that of P-channel MOS transistor P123, the input voltage of inverter I122 gradually decreases. When the input voltage of the inverter I122 becomes lower than the threshold voltage, the output of the inverter I122 is inverted and rises to a high level. Further, when the output of the inverter I122 rises to a voltage close to 5 V, the P-channel MOS transistor P123 is turned off, and there is no through current flowing from the power supply VCC to the ground through the P-channel MOS transistor P123 and the N-channel MOS transistor N121. The output voltages of I121 and inverter I122 are fixed at approximately 0V and 5V, respectively.
[0016]
[Patent Document 1]
JP-A-2000-174610 (page 3-4, FIG. 13)
[Patent Document 2]
JP-A-60-70822 (page 4, FIG. 6)
[0017]
[Problems to be solved by the invention]
The transistor circuits functioning as the level shift circuits of the conventional examples 1 to 3 described above have the following problems in order to obtain high-speed switching with low power consumption.
[0018]
First, in the transistor circuit of Conventional Example 1 shown in FIG. 9, the gates of the N-channel MOS transistors of the P-channel MOS transistor and the N-channel MOS transistors (P101 and N101, P102 and N102) of the crossing circuit connected in series are connected. The input signal is connected, but the output of the opposite side of the crossing circuit is connected to the gate of the P-channel MOS transistor. Therefore, when the input signal changes, the N-channel MOS transistor immediately turns on and off. However, a through current flows between the turned-on N-channel MOS transistor and the P-channel MOS transistor that is to maintain the current on-state, and the switching speed is reduced. Is not suitable for applications requiring high-speed switching.
[0019]
Further, in the transistor circuit of Conventional Example 2 shown in FIG. 11, when the input voltage IN is at a low level, both the P-channel MOS transistors P111 and P112 of I112 and the N-channel MOS transistor are turned on, so that the input voltage IN is low. Since a through current constantly flows as long as the level is at a level, a transistor circuit with low power consumption cannot be realized.
[0020]
In addition, when the input voltage rises from a low level to a high level, the transistor circuit of Conventional Example 3 shown in FIG. 13 receives the output of the inverter I122, which is the output of the transistor circuit, and tries to maintain the current state and continue the ON state. The P-channel MOS transistor P123 and the N-channel MOS transistor N121 which receives an input signal and changes to the ON state are simultaneously turned on, and a through current flows from the P-channel MOS transistor P123 to the N-channel MOS transistor N121. The state in which the through current flows does not disappear until the voltage at the contact point of the two transistors gradually increases due to the ratio of the P-channel MOS transistor P123 and the N-channel MOS transistor N121 and exceeds the input threshold level of the inverter I122. Therefore, the switching when the input voltage rises from the low level to the high level becomes slow similarly to the transistor circuit of the conventional example 1, and high-speed switching operation cannot be expected.
[0021]
As a result of studying the above conventional transistor circuit, an object of the present invention is to provide a high-speed transistor circuit or a level shift circuit with low power consumption.
[0022]
[Means for Solving the Problems]
A transistor circuit according to the present invention includes a signal input circuit including a transistor that performs an on / off operation in response to an input signal, and a voltage drop provided between a power supply terminal of the signal input circuit and a power supply line. A voltage drop circuit that is generated, and a switch circuit that is connected between a power supply end of the signal input circuit and the power supply line and that is controlled in response to an output signal of the signal input circuit, the signal input circuit being turned on. And a switch circuit for forming an electric path between the power supply end of the power supply line and the power supply line.
[0023]
Thus, in the present invention, the voltage drop circuit provided between the power supply terminal of the signal input circuit and the power supply line and generating a voltage drop between both ends, and the power supply terminal of the signal input circuit and the power supply line A switch circuit connected between the power supply terminal and the power supply line, the switch circuit being configured to be controlled in response to an output signal of the signal input circuit and forming an electric path between a power supply terminal of the signal input circuit and the power supply line when turned on. Since the power supply voltage provided to the power supply terminal of the signal input circuit can be changed depending on the level of the input signal, a through current does not almost flow at the time of switching, and a transistor circuit or a level shift circuit that performs high-speed switching operation Can be realized.
[0024]
In the transistor circuit of the present invention, the transistor circuits are connected in cascade in a plurality of stages, and the voltage drop of the voltage drop circuit included in each stage can be made smaller as the voltage drop circuit included in the subsequent stage. According to such a configuration, the level of the input signal can be shifted to a signal of a large voltage by increasing the number of cascade-connected stages. Further, by reducing the voltage level to be shifted per stage, a steady through current of the signal input circuit can be more completely prevented.
[0025]
Further, the transistor circuit according to the present invention may include a first conductivity type first MOS transistor, and a second conductivity type first MOS transistor having a gate electrode and a drain electrode connected to the gate electrode and the drain electrode of the first MOS transistor, respectively. A CMOS gate circuit including a second MOS transistor; a voltage drop circuit provided between a source electrode of the first MOS transistor and a power supply line to generate a voltage drop therebetween; A switch circuit connected in parallel with the voltage drop circuit between the power supply line and a power supply line, the switch circuit being turned on / off based on an output voltage of the CMOS gate circuit, and being turned on when a source electrode of the first MOS transistor is turned on. And a first switch circuit forming an electric path between the power supply line and the power supply line.
[0026]
As described above, in the present invention, the voltage drop circuit and the switch circuit are connected in parallel between the source electrode of the CMOS gate circuit and the power supply line, and ON / OFF of the switch circuit is controlled based on the output voltage of the CMOS gate circuit. As a result, the power supply voltage applied to the CMOS gate circuit can be changed according to the level of the input signal, and a transistor circuit or a level shift circuit that performs a high-speed switching operation with little through current flowing during switching is realized. it can.
[0027]
Further, the transistor circuit of the present invention includes a second switch circuit connected in series with the voltage drop circuit between the power supply line and a power supply terminal of a CMOS gate circuit, and a source electrode of the second MOS transistor. A third switch circuit connected to the second MOS transistor and connected in parallel with the second MOS transistor. When the second switch circuit is turned on by a control signal, the third switch circuit is turned on. When turning off and turning off the second switch circuit, the third switch circuit may be turned on. With such a configuration, when a high-speed switching operation is not required, a leakage current of the CMOS gate circuit can be prevented by a control signal, and the output voltage of the transistor circuit or the level shift circuit can be fixed.
[0028]
Further, in the transistor circuit of the present invention, the transistor circuits are connected in cascade in a plurality of stages, and the voltage drop of the voltage drop circuit included in each stage can be reduced as the potential difference generation circuit included in the subsequent transistor circuit. According to such a configuration, the level of the input signal can be shifted to a signal of a large voltage by increasing the number of cascade-connected stages. In addition, by reducing the voltage level of the level shift per stage, a steady through current of the first CMOS inverter can be more completely prevented.
[0029]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a transistor circuit according to the first embodiment of the present invention. FIG. 1 shows a CMOS inverter I1 supplied with 1.5V power, a CMOS inverter I2 composed of a P-channel MOS transistor P1 and an N-channel MOS transistor N1, and CMOS inverters I3 and I4 supplied with 3.3V power. And a voltage drop circuit P2 composed of a P-channel MOS transistor inserted between the CMOS inverter I2 and the 3.3V power supply, and a switch composed of the same P-channel MOS transistor connected in parallel with the voltage drop circuit P2 And a circuit P3. The CMOS inverter I2 receives an input signal as a signal input circuit or a CMOS gate circuit and outputs an output signal. The inverter I1 is an inverter for generating a waveform, and may be omitted. If omitted, the inverted signal of the 1.5V input signal IN may be directly input to the CMOS inverter I2. The gate electrodes of the P-channel MOS transistor P1 and the N-channel MOS transistor N1 of the CMOS inverter I2 are connected to the output of the inverter I1. The source electrode of the N-channel MOS transistor N1 is ground, the source electrode of the P-channel MOS transistor P1 is a drain electrode and a gate electrode of a P-channel MOS transistor P2 forming a voltage drop circuit, and a P-channel MOS transistor P3 forming a switch circuit. Connected to the drain electrode of Further, the drain electrodes of the P-channel MOS transistor P1 and the N-channel MOS transistor N1 are commonly connected and connected to the input of the inverter I3. An output of the inverter I3 is connected to an input of the inverter I4 and a gate electrode of a P-channel MOS transistor P3 serving as a switch circuit. The source electrodes of the P-channel MOS transistors P2 and P3 are connected to a 3.3V power supply line. Although the inverter I4 is provided to drive the 3.3V system circuit, the inverter I4 may be omitted and the output may be taken directly from the inverter I3.
[0030]
Next, the operation of the level shift circuit of the present invention shown in FIG. 1 will be described with reference to timing charts FIGS. In the initial state t0, it is assumed that a low level 0V is input to the input IN. At this time, the voltage at the output point A of the inverter I1 becomes the high level 1.5V. Here, assuming that the threshold value (VT) of the P-channel MOS transistors P1 and P2 is 0.8 V, the gate and drain of the commonly connected P-channel MOS transistor P2 and the source electrode of the P-channel MOS transistor P1 are about 3.3V-0. 8V = 2.5V. Since the voltage at the point A is 1.5V, the P-channel MOS transistor P1 is weakly turned on, but the N-channel MOS transistor N1 is strongly turned on, so that the potential at the output point B of the inverter I2 becomes almost low level 0V. . Then, the output point C of the inverter I3 becomes high level 3.3V, and the inverter I3 outputs low level 0V. At this time, the switch circuit P3 constituted by the P-channel MOS transistor is turned off.
[0031]
Next, when the input IN rises from 0V to a high level of 1.5V at t1, the voltage at the output point A of the inverter I1 drops to 0V. When the point A falls, the N-channel MOS transistor N1 turns off, the P-channel MOS transistor P1 turns on, and the output point B of the inverter I2 rises to about 2.5 V (timing t2). When the voltage at point B rises to 2.5V, the P-channel MOS transistor of inverter I3 turns off and the N-channel transistor turns on, so that the voltage at point C falls to 0V. When the voltage at the point C falls to 0V, OUT outputs a high level of 3.3V, and the switch circuit P3 consisting of a P-channel MOS transistor turns on, and the source electrode of the P-channel MOS transistor P1 rises to 3.3V. As a result, the voltage at point B is further increased from 2.5 V to 3.3 V.
[0032]
Subsequently, a case where the input IN falls from 1.5 V to the low level 0 V will be described with reference to a timing chart of FIG. When the input IN falls at t3, the voltage at the point A rises from 0V to 1.5V. When the voltage at the point A rises to 1.5 V, the N-channel transistor N1 turns on. At this time, since the switch circuit P3 is turned on, the source electrode of the P-channel MOS transistor P1 has 3.3 V, and passes through the switch circuit P3, the P-channel MOS transistor P1, and the N-channel transistor N1. Electric current flows. Here, since the driving capability of the N-channel MOS transistor N1 is larger than the driving capability of the P-channel MOS transistors P1 and P3, the potential at the point B becomes equal to or lower than the input threshold voltage of the inverter I3 (timing t4). Therefore, the voltage at the point C is about 3.3 V, and the output OUT outputs a low level 0 V. When the voltage at the point C becomes about 3.3 V, the switch circuit P3 including the P-channel MOS transistor is turned off, and the source voltage of the P-channel MOS transistor P1 decreases by the voltage drop of the diode-connected P-channel MOS transistor P2. It becomes about 2.5V. When the source voltage of the P-channel MOS transistor P1 drops to about 2.5V, the voltage at the point A is 1.5V, so that the P-channel MOS transistor P1 is almost off, the voltage at the point B becomes almost 0V, and the inverter The through current of I2 only slightly flows.
[0033]
Next, a description will be given of a result of a simulation performed on the first embodiment described above in comparison with Conventional Example 1 and Conventional Example 2. The simulation was performed under the conditions of a power supply voltage of 1.35 V on the input side, a power supply voltage of 3.0 V on the output side, and a temperature of 125 ° C. Here, the size of each transistor is such that the W / L of P1 shown in FIG. 1 is 2.5 μm / 0.39 μm, the W / L of P2 is 10 μm / 0.39 μm, and the W / L of P3 is 0.5 μm / 0. .39 μm, W / L of N1 is 5 μm / 0.55 μm, W / L of P101 and P102 shown in FIG. 10 are 2 μm / 0.39 μm, respectively, and W / L of N101 and N102 are 5 μm / 0.55 μm, respectively. The W / L of P111 and P112 described in No. 12 was 1.5 μm / 0.39 μm, respectively, and the W / L of N111 was 5 μm / 0.55 μm.
[0034]
FIG. 4 is an input / output waveform diagram by the above simulation. In the present invention shown in FIG. 1, the rise time and the fall time are 0.50 ns and 0.39 ns, respectively, whereas in the conventional example 1, the rise time and the fall time are 0.95 ns and 1.06 ns, respectively. In Example 2, the rise time and the fall time were 0.41 ns and 0.36 ns, respectively.
[0035]
Next, FIG. 5 is a waveform diagram of an intermediate node by the above simulation, that is, a point B of FIG. 1, a point E of FIG. 10, and a point H of FIG. Since the rise and fall of the point E in the conventional example 1 are both determined by the balance between the P-channel MOS transistor and the N-channel MOS transistor connected in series, the switching speed is slow. Further, the point H in the conventional example 2 does not become 0 V even when the low level is output because the P-channel MOS transistors P111 and P112 are not turned off. Further, in the present invention, when the point B rises, it rises at a high speed up to about 2 V, inverts the output, and then waits for the switch circuit P3 to conduct to rise to 3.0 V.
[0036]
Next, FIG. 6 is a waveform diagram of a current by the above simulation. The right axis indicates the amount of current flowing from the 3.0 V power supply. In Conventional Example 1, a large through current flows for a long time during switching between rising and falling. In addition, in Conventional Example 2, when IN and OUT are at the low level, it can be seen that the current constantly flows. On the other hand, in the present invention, the through current at the time of switching can be significantly reduced as compared with the conventional example 1. In addition, according to the present invention, it can be understood that the steady-state current at the time of 0V output is significantly reduced as compared with the conventional example 2. Summarizing the simulation results for the current consumption, the average current consumption per cycle during high-speed switching is 27 μA in the present invention, 101 μA in Conventional Example 1, and 35 μA in Conventional Example 2. is there. Further, the steady-state current at the time of 0V output is 8 μA in the present invention, whereas it is almost 0 in Conventional Example 1 and 35 μA in Conventional Example 2.
[0037]
Next, as a second embodiment, by cascading a plurality of the transistor circuits or the level shift circuits of the above-described first embodiment, even when there is a large difference in power supply voltage between input and output, high speed and high speed can be achieved. A transistor circuit which can perform level shift with low power consumption can be obtained. Hereinafter, an example in which a plurality of the above-described transistor circuits or level shift circuits are connected in cascade will be described as a second embodiment. FIG. 7 is a block diagram of a transistor circuit suitable for level-shifting a 1.5V-system signal to 5.0V, for example. The same circuits as those in FIG. In FIG. 7, the power of 5.0 V is applied to the portion where the power of 3.3 V was supplied in FIG. In FIG. 7, the voltage dropping circuit uses a diode-connected P-channel MOS transistor in four stages to generate a large potential difference. Further, in FIG. 7, the power sources of the P-channel MOS transistor P31 and the N-channel MOS transistor N31 corresponding to the inverter I3 of FIG. 1 are not directly connected to the 5.0V system power source, but are connected to the diode-connected PMOS transistor P32. A second potential difference generating circuit and a second switch circuit including a P-channel MOS transistor P33 connected in parallel with the second potential difference generating circuit to a 5.0 V power supply and a source electrode of the P-channel MOS transistor P31. Connected to a 5.0 V system power supply. The circuit shown in FIG. 7 has a two-stage cascade connection of a signal input circuit (CMOS gate circuit) and a transistor circuit including a voltage drop circuit and a switch circuit inserted in parallel between the signal input circuit and the power supply. You may think. In FIG. 4, I2 and I3, P21 to P24 and P32, and P3 and P33 correspond to the previous and next signal input circuits (CMOS gate circuits), voltage drop circuits, and switch circuits, respectively. The output signal of the preceding signal input circuit is inverted by the next signal input circuit and supplied to the preceding switch circuit.
[0038]
In the first embodiment, when there is a large potential difference between the power supply voltage of the input system and the power supply voltage of the output system, the voltage level input to the signal input circuit (I2 in FIG. 1) and the generation of the voltage drop circuit P2 Depending on the potential difference to be applied, a through current flows through the signal input circuit or the gate (the inverter I3 in FIG. 1) that receives the output of the signal input circuit, or the potential difference between the input system power supply voltage and the output system power supply voltage is too large. In that case it might not work. However, in the second embodiment, by cascading a plurality of transistor circuits as described above, even when a large potential difference is required between the input system power supply voltage and the output system power supply voltage, the level shift operation can be performed. it can. Further, the current flowing through the input signal circuit at the time of steady state can be reduced to zero by reducing the level shift voltage per stage. FIG. 7 shows an example in which transistor circuits are connected in two stages. However, the number of stages is not limited to two, and the more the number of stages is increased, the more the level can be shifted to a signal having a level higher than the power supply voltage of the input system. it can. In the case of cascade connection in multiple stages, the voltage drop generated by the voltage drop circuit included in the preceding transistor circuit or the level shift circuit should be larger, and the voltage drop circuit included in the subsequent transistor circuit should have smaller voltage drop. do it.
[0039]
Further, a description will be given of a third embodiment in which the above-described transistor circuit is provided with a circuit for preventing a shoot-through current constantly flowing to a signal input circuit when a high-speed switching operation is unnecessary and for fixing an output voltage. I do. FIG. 8 is a block diagram of the third embodiment. FIG. 8 shows a second switch circuit P41 composed of a P-channel MOS transistor connected in series with a voltage drop circuit between the power supply of the transistor circuit of FIG. 1 and a signal input circuit (CMOS gate circuit) and a CMOS inverter I2. A third switch circuit N41 composed of an N-channel MOS transistor connected between the output and the ground is further provided. When a high-speed switching operation is not required, on / off control is performed by an external control signal so that the switch circuit P41 is turned off and N41 is turned on. When the switch circuit P41 is turned off and N41 is turned on, the CMOS inverter I2 is turned on. Does not flow, and the potential at point B is fixed at 0V. On the other hand, when the switch circuit P41 turns on and the N41 turns off, the circuit operation is exactly the same as in FIG.
[0040]
Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments. For example, in the above-described first to third embodiments, the potential difference generating circuit and the first switch circuit are inserted between the positive power supply and the CMOS inverter. It is needless to say that the switch circuit may be inserted between the negative power supply and the N-channel transistor source electrode of the CMOS inverter.
[0041]
The signal input circuit (CMOS gate circuit) is not limited to a one-input one-output inverter, but is a gate circuit that receives a plurality of input signals, performs a logical operation on the input signals such as NAND and NOR, and outputs an output signal. You may. For example, if the CMOS inverter I2 shown in FIGS. 1, 7, and 8 is replaced with a CMOS NAND gate and a NOR gate, respectively, a transistor circuit that receives a plurality of input signals, performs a logical operation on the result, and level-shifts and outputs the result. A level shift circuit is obtained. Needless to say, an input-side inverter corresponding to I1 in FIGS. 1, 7, and 8 may be provided for each of a plurality of input signals as needed.
[0042]
【The invention's effect】
As described above, the transistor circuit of the present invention can shift the level of an input signal of a low voltage level to a signal of a high voltage level with low current consumption and at a high speed and output the signal.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a transistor circuit according to a first embodiment of the present invention.
FIG. 2 is a waveform diagram when an input / output signal of the transistor circuit of FIG. 1 rises.
FIG. 3 is a waveform diagram when an input / output signal of the transistor circuit of FIG. 1 falls.
FIG. 4 is an input / output signal simulation waveform diagram comparing the present invention with a conventional example.
FIG. 5 is an intermediate node signal simulation waveform diagram comparing the present invention with a conventional example.
FIG. 6 is a current consumption simulation waveform diagram comparing the present invention with a conventional example.
FIG. 7 is a block diagram illustrating a transistor circuit according to a second embodiment of the present invention.
FIG. 8 is a block diagram showing a transistor circuit according to a third embodiment of the present invention.
FIG. 9 is a block diagram showing a level shift circuit of Conventional Example 1.
FIG. 10 is a waveform diagram of the level shift circuit of FIG. 9;
FIG. 11 is a block diagram showing a level shift circuit of Conventional Example 2.
FIG. 12 is a waveform diagram of the level shift circuit of FIG. 11;
FIG. 13 is a block diagram showing a level shift circuit of Conventional Example 3.
[Explanation of symbols]
I1-212 CMOS inverter
P1 to P123 P-channel MOS transistor
N1 to N123 N-channel MOS transistor
P2, P21 to P24, P32 Voltage drop circuit
P3, P33, P41, N41 switch circuit

Claims (7)

A signal input circuit including a transistor that performs an on / off operation in response to an input signal; a voltage drop circuit provided between a power supply terminal of the signal input circuit and a power supply line to generate a voltage drop between both ends; A switch circuit connected between a power supply terminal of the signal input circuit and the power supply line and controlled in response to an output signal of the signal input circuit, and when turned on, a power supply terminal of the signal input circuit and the power supply line And a switch circuit that forms an electric path between the transistor circuit. A transistor circuit comprising a plurality of cascade-connected transistor circuits according to claim 1, wherein a voltage drop circuit included in a subsequent stage has a smaller voltage drop. A CMOS including a first MOS transistor of a first conductivity type and a second MOS transistor of a second conductivity type having a gate electrode and a drain electrode connected to a gate electrode and a drain electrode of the first MOS transistor, respectively. A gate circuit,
A voltage drop circuit provided between a source electrode of the first MOS transistor and a power supply line to generate a voltage drop therebetween;
A switch circuit connected in parallel with the voltage drop circuit between the source electrode and the power supply line, wherein the switch circuit is on / off controlled based on an output voltage of the CMOS gate circuit, and is turned on and off when turned on. A transistor circuit, comprising: a first switch circuit that forms an electric path between a source electrode of a MOS transistor and the power supply line. The first switch circuit includes a first conductivity type third MOS transistor having a source electrode connected to the power supply line and a drain electrode connected to a source electrode of the first MOS transistor, and an output of the CMOS gate circuit. 4. The transistor circuit according to claim 3, wherein an inverted signal of the third MOS transistor is applied to a gate electrode of said third MOS transistor to perform on / off control. 5. The transistor according to claim 3, wherein the voltage drop circuit includes a fourth MOS transistor that connects a gate electrode and a source electrode in common and generates a constant potential difference between the drain electrode and the gate electrode. circuit. A second switch circuit connected in series with the potential drop circuit between the power supply line and a source electrode of the first MOS transistor;
A third switch circuit connected to a source electrode and a drain electrode of the second MOS transistor and connected in parallel to the second MOS transistor;
According to a control signal, when the second switch circuit is turned on, the third switch circuit is turned off, and when the second switch circuit is turned off, the third switch circuit is turned on. The transistor circuit according to any one of claims 3 to 5, wherein: 7. The transistor circuit according to claim 3, wherein a plurality of stages are cascaded, and a voltage drop of the voltage drop circuit included in each stage is smaller as a voltage drop circuit included in a transistor circuit of a subsequent stage. Characteristic transistor circuit.

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