JP2004064247A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce power consumption by suppressing transition of data while suppressing increase of the chip area due to addition of a circuit. <P>SOLUTION: Input section 110 of a second logic circuit 140 is constituted of an inverter while separating the power supply thereof from a processing section 120 and connected with an output fixing signal s150 being generated from an output fixing signal generating means 150. When the outputs s111o-s116o at the input section 110 is fixed to logic "0", the output fixing signal s150 is set at logic "0" . Power consumption can be reduced by providing a means for fixing the data input while suppressing increase in the chip area due to addition of a circuit by dropping the output forcibly to logic "0" utilizing a pMOS in the inverter thereby suppressing transition of a nonoperating circuit. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit which fixes data input to an unused logic circuit and reduces power consumption by reducing the operation of a circuit inside the logic circuit.
[0002]
[Prior art]
2. Description of the Related Art In recent years, a large number of portable terminals have come to the world, and there is a strong demand for lowering the power consumption of a semiconductor integrated circuit mounted on the portable terminal. The following equation is generally known as an equation for calculating the power consumption.
[0003]
(Power consumption) = (transition probability) × (frequency) × (load capacity) × (square of voltage)
As a technique for reducing the transition probability in the above equation in order to suppress the power consumption of the semiconductor integrated circuit, a circuit that fixes data input to an unused logic circuit and reduces the operation of the circuit inside the logic circuit There is a technique for configuring.
[0004]
Hereinafter, a conventional semiconductor integrated circuit with low power consumption will be described with reference to FIG.
FIG. 13 is a configuration diagram of a conventional semiconductor integrated circuit with low power consumption.
[0005]
In FIG. 13, a conventional semiconductor integrated circuit with low power consumption has a configuration in which an output of a first logic circuit 1300 is input to a processing unit 1320 via an input unit 1310 for fixing input data. An input unit 1310 for fixing input data is composed of AND circuits 1311, 1312, 1313, 1314, 1315, and 1316. One of the inputs of these AND circuits is an output fixing for fixing the output of the AND circuit. The signal s1350 is connected.
[0006]
In this configuration, if it is known that the processing unit 1320 is not used in advance, the output fixing signal s1350 is set to logic "0", thereby fixing the outputs of all the AND circuits to logic "0". Thus, a change in the circuit inside the second logic circuit 1340 can be prevented, and low power consumption can be achieved.
[0007]
[Problems to be solved by the invention]
However, the configuration of FIG. 13 has a problem that the number of AND circuits required is equal to the number of data inputs of the second logic circuit, and the chip area of the semiconductor integrated circuit is increased. Further, since the added AND circuit itself consumes power, there is also a problem that when the power consumption is measured as a whole, the power consumption increases as a result.
[0008]
The semiconductor integrated circuit of the present invention has been made in view of the above points, and has a low power consumption by providing a means for fixing data input and suppressing data transition while suppressing an increase in chip area due to addition of a circuit. The purpose is to achieve the conversion.
[0009]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a semiconductor integrated circuit having a processing unit whose circuit operation may be stopped depending on an operation state, and an input inserted immediately before the processing unit on a signal line input to the processing unit. Unit, and an output fixed signal generating means for selecting and supplying a voltage to be supplied to a power supply of the input unit, and supplying a ground voltage from the output fixed signal generating means, thereby changing an output value of the input unit. It is characterized by being fixed to low.
[0010]
The semiconductor integrated circuit according to claim 2, wherein a processing unit whose circuit operation may be stopped according to an operation state, an input unit inserted immediately before the processing unit of a signal line input to the processing unit, Output fixed signal generating means for selecting and supplying a voltage to be supplied to the ground of the input section, and supplying a power supply voltage from the output fixed signal generating means to fix the output value of the input section to high. It is characterized by the following.
[0011]
According to a third aspect of the present invention, in the semiconductor integrated circuit according to the first aspect, a circuit forming the input unit is disposed near a power supply wiring, and a power supply wiring length from the power supply wiring to the circuit is minimized. , The effect of the IR drop is suppressed.
[0012]
According to a fourth aspect of the present invention, in the semiconductor integrated circuit according to the second aspect, a circuit constituting the input unit is arranged near a ground line, and a ground line length from the ground line to the circuit is minimized. By doing so, the effect of the IR drop is suppressed.
[0013]
6. The semiconductor integrated circuit according to claim 5, wherein the n-well region of the input unit is separated from the n-well region of the processing unit, and the n-well region of the input unit is separated. By connecting a region to a power supply of the input portion, charge on the drain side of the transistor is extracted.
[0014]
7. The semiconductor integrated circuit according to claim 2, wherein the p-well region of the input unit is separated from the p-well region of the processing unit, and the p-well of the input unit is separated. By connecting a region to the ground of the input portion, charge on the drain side of the transistor is extracted.
[0015]
The semiconductor integrated circuit according to claim 7, wherein a processing unit whose circuit operation may be stopped according to an operation state, an input unit inserted immediately before the processing unit on a signal line input to the processing unit, Output fixed signal generation means for selecting and supplying a voltage to be supplied to a power supply and a ground of the input unit, and separating an n-well region of a pMOS transistor of the input unit from an n-well region of the processing unit; A voltage supplied from the output fixed signal generating means to the n-well region of the pMOS transistor is supplied to the source of the pMOS transistor, and supplied from the output fixed signal generating means to the p-well region of the nMOS transistor in the input section. Another voltage is supplied to the source of the nMOS transistor, and the output fixed signal generating means outputs the pMOS transistor of the input section. The output value of the input section is fixed to low by supplying a ground voltage to the source of the input section, or the power supply voltage is supplied to the source of the nMOS transistor of the input section from the output fixed signal generating means. The value is fixed at high.
[0016]
9. The semiconductor integrated circuit according to claim 8, wherein a processing unit whose circuit operation may be stopped according to an operation state, an input unit inserted immediately before the processing unit on a signal line input to the processing unit, Output fixed signal generating means for selecting and supplying a voltage to be supplied to a power supply and a ground of the input unit, respectively, separating a p-well region of the nMOS transistor of the input unit from a p-well region of the processing unit, A voltage supplied from the output fixed signal generating means to a p-well region of the nMOS transistor is supplied to a source of the nMOS transistor, and supplied from the output fixed signal generating means to an n-well region of the pMOS transistor in the input section. Another voltage is supplied to the source of the pMOS transistor, and the pMOS transistor of the input section is supplied from the output fixed signal generating means. The output value of the input section is fixed at low by supplying a ground voltage to the source of the input section, or the power supply voltage is supplied to the source of the nMOS transistor of the input section from the output fixed signal generating means. The output value is fixed at high.
[0017]
According to a ninth aspect of the present invention, there is provided the semiconductor integrated circuit according to the seventh or the eighth aspect, further comprising a majority decision means for separating a signal value input to the input section and selecting a signal value having the largest number of inputs. Controlling the voltage of the power supply and the ground output from the output fixed signal generation means based on the result of the majority decision means, thereby taking into account the input signal value of the input part when the circuit operation is stopped, Characterized in that the fixed output value is controlled.
[0018]
With the above configuration, it is possible to reduce power consumption by suppressing data transition by providing a means for fixing data input while suppressing an increase in chip area due to the addition of a circuit.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the semiconductor integrated circuit of the present invention will be described.
(Embodiment 1)
Hereinafter, the semiconductor integrated circuit according to the first embodiment of the present invention will be described with reference to FIGS. 1, 2, 3, 4, and 5.
[0020]
FIG. 1 is a configuration diagram of a semiconductor integrated circuit which achieves low power consumption according to the present invention. 2 is a configuration diagram of a “0” fixed inverter according to the first embodiment of the present invention, FIG. 3 is a layout diagram of the “0” fixed inverter according to the first embodiment of the present invention, and FIG. 4 is a first embodiment of the present invention. And FIG. 5 is a layout diagram of the "1" fixed inverter according to the first embodiment of the present invention.
[0021]
As shown in FIG. 1, an input unit 110 including an inverter is added to the second logic circuit 140. Alternatively, if an inverter is used as an input of the second logic circuit 140, the circuit is used as an input unit. Circuits other than the input unit 110 in the second logic circuit 140 are referred to as a processing unit 120.
[0022]
When the outputs s111o, s112o, s113o, s114o, s115o, and s116o of the respective inverters are fixed to the logic “0” by the output fixing signal s150, each inverter has the configuration shown in FIG.
[0023]
In FIG. 2, each inverter separates the power supply from the power supply of the processing unit 120, and connects the output fixed signal s220 to the separated power supply. If it is desired to fix the output of the inverter to logic "0", the power supply to the inverter is stopped by setting the output fixing signal s220 to logic "0". Of the output signals s111o to s116o, the one having the logic "1" is fixed to the logic "0" through the pMOS 260. If the second logic circuit 140 does not operate for several cycles, the inside of the processing unit 120 does not operate, so that low power consumption is achieved. Further, since the operation can be shifted to the normal operation only by setting the output fixed signal s220 to the logic “1”, the time required for shifting to the normal operation can be reduced.
[0024]
However, if the separated power supply becomes a long wiring, an IR drop occurs, the power supply becomes insufficient, and the time required to shift to the normal operation increases.
FIG. 3 shows a layout configuration for preventing this problem.
[0025]
As shown in FIG. 3, the inverters 330, 340, 350, 360, 370, and 380 are arranged on both sides of the power supply 320 separated from the processing unit 120, so that the separated power supply 320 can be shortened. It is possible to reduce the influence of the IR drop. Note that the output fixed signal generating means 301 can be easily realized by an inverter.
[0026]
When the outputs s111o to s116o of the inverters 111 to 116 are fixed to the logic "1" by the output fixing signal s150, the inverters 111 to 116 have the configuration shown in FIG.
[0027]
In FIG. 4, each inverter separates the ground from the processing unit, and connects the output fixed signal s420 to the separated ground. When it is desired to fix the output of each inverter to logic "1", the power is forcibly supplied to each inverter by setting the output fixing signal s420 to logic "1". Of the output signals s111o to s116o, the one having the logic "0" is fixed to the logic "1" via the nMOS 470. Also in this case, if the second logic circuit 140 does not operate for several cycles, the inside of the processing unit does not operate, so that low power consumption is achieved.
[0028]
Also, as shown in FIG. 5, the layout in which the inverters 530, 540, 550, 560, 570, and 580 are arranged on both sides of the separated ground 525 can shorten the separated ground 525. It is possible to reduce the influence of the IR drop.
[0029]
With the above configuration, it is possible to reduce power consumption by suppressing data transition by providing a means for fixing data input while suppressing an increase in chip area due to the addition of a circuit.
[0030]
In the configuration of FIG. 1, if it is known in advance that the signals s111o to s116o input to the processing unit 120 are biased to either the logic “0” or the logic “1”, the logic is fixed to the biased logic. , The configuration shown in FIG. 2 or the configuration shown in FIG. In this case, since the number of inputs for fixing the logic is stochastically reduced, it is possible to reduce the movement of the internal state of the processing unit, and to further reduce the power consumption.
(Embodiment 2)
Hereinafter, a semiconductor integrated circuit according to the second embodiment of the present invention will be described with reference to FIGS. 6, 7, 8, and 9.
[0031]
FIG. 6A is a configuration diagram of a “0” fixed inverter according to the second embodiment of the present invention, FIG. 6B is a structural sectional view of the “0” fixed inverter according to the second embodiment of the present invention, and FIG. FIG. 8A is a layout diagram of a “0” fixed inverter according to the second embodiment, FIG. 8A is a configuration diagram of a “1” fixed inverter according to the second embodiment of the present invention, and FIG. 8B is an embodiment of the present invention; 2 is a cross-sectional view of the structure of the “1” fixed inverter, and FIG. 9 is a layout diagram of the “1” fixed inverter according to the second embodiment of the present invention.
[0032]
In the first embodiment, for example, when the output of the input unit is fixed to logic “0”, the output potential is lowered by using the pMOS, so that the potential remains as much as the threshold value of the transistor. When the power supply voltage is low, the potential corresponding to the threshold value becomes an intermediate potential, so that a problem that a through current is generated in the logic of the next stage occurs. Even when the logic is fixed to "1", the same problem occurs because the potential is reduced only by the threshold value. In the case where a transistor is a circuit in which two or more transistors are connected in series, the remaining potential is (the number of serial transistors × the threshold voltage), and thus cannot be applied when the number of serial transistors is increased.
[0033]
The configuration in FIG. 6 improves this point.
FIG. 6 shows a case where the logic is fixed to “0”. The difference from FIG. 2 is a node n600. That is, the nWELL 670 that is the substrate of the pMOS 630 is also connected to the output fixed signal s620. At this time, nWELL 670 of the input unit is separated from nWELL of the processing unit. When the logic is fixed to "0", the charge stored in the output 660 is also extracted from the pMOS 630, but the charge is also extracted by the PN junction between the separated nWELL 670 and the output (arrow in the figure). When the potential of the output drops to the threshold value, the charge is extracted only at the PN junction between the nWELL 670 and the output. With this effect, the potential does not remain for the threshold value of the transistor; therefore, the present invention can be applied to a circuit with a low power supply voltage.
[0034]
Further, the layout is as shown in FIG. 7, and it is only necessary to separate the nWELL 710 from the layout of FIG. 3 and add the contact 790 to the separated nWELL 710 to the separated power supply.
[0035]
Similarly, when the logic is fixed to "1", as shown in FIGS. 8 and 9, the separated pWELL 870 that is the substrate of the nMOS 840 is also connected to the output fixing signal s820, and the separated pWELL 870 is connected to the nWELL of the processing unit. And separate.
[0036]
Regarding the layout, as shown in FIG. 9, it is only necessary to separate pWELL 915 from the layout of FIG. 5 and add a contact 990 with the separated pWELL 915 to the separated ground.
[0037]
With the above configuration, it is possible to reduce power consumption by suppressing data transition by providing a means for fixing data input while suppressing an increase in chip area due to the addition of a circuit.
[0038]
In addition, since it is not affected by the potential corresponding to the threshold value, the present invention can be applied to circuits other than the inverter. In other words, the first logic receiving the input of the second logic circuit is regarded as the input portion, and the same effect can be obtained, and it can be realized only by adding only the output fixed signal generating means, so that the increase in the area is further suppressed. be able to.
(Embodiment 3)
Hereinafter, a semiconductor integrated circuit according to the third embodiment of the present invention will be described with reference to FIGS. 10, 11, and 12. FIG.
[0039]
FIG. 10A is a configuration diagram of an inverter according to the third embodiment of the present invention, FIG. 10B is a diagram illustrating a truth table of a control signal generation unit according to the third embodiment of the present invention, and FIG. FIG. 12 is a structural cross-sectional view of an inverter according to Embodiment 3 of the present invention, and FIG. 12 is a configuration diagram of a semiconductor integrated circuit for reducing power consumption according to Embodiment 3 of the present invention.
[0040]
In both the first and second embodiments, the output of the input unit can be fixed to only one of the logics. However, here, a configuration in which the output of the input unit can be fixed to any logic will be described.
[0041]
In FIG. 10, a control signal s1050 generated by the control signal generation means 1020 is input as a power supply of the inverter 1070, and a control signal s1060 generated by the control signal generation means 1020 is input as ground.
[0042]
With the configuration of FIG. 10, the output of the input unit can be fixed with any of the logics “0” and “1”. However, in addition to the output fixing control signal s1010 indicating whether or not the output of the input section is to be fixed, a selection signal s1000 indicating whether to fix the logic to “0” or “1”, and these two signals , A control signal generating means 1020 for generating a control signal is required.
[0043]
When WELLs are separated, a triple WELL configuration is required.
FIG. 11 shows a configuration example in the case of a p substrate.
Depending on the value of the selection signal s1100, a path for fixing the output 1171 via WELL is formed in the direction of the arrow in the figure. In the case of an n-substrate, it can be realized by inverting the attribute of the configuration of FIG.
[0044]
In FIG. 10B, if the output fixing signal is "0", the output is not fixed, so "1" is given to the separated power supply and "0" is given to the separated ground. When the output fixing control signal is “1”, if the selection signal is “0”, “0” is given to the separated power supply, and if the selection signal is “1”, “1” is given to the separated ground, and the logic of the output of the input section is given. Is fixed.
[0045]
With the above configuration, it is possible to reduce power consumption by suppressing data transition by providing a means for fixing data input while suppressing an increase in chip area due to the addition of a circuit.
[0046]
Further, by selecting which of the logic "0" or "1" is more at each input of the input section, and appropriately selecting the selection signal, the number of transitions when the output of the input section is fixed is minimized to reduce the power consumption. Can be reduced.
[0047]
12, the inverters 1251 to 1256 have the same configuration as the inverter 1070 in FIG. All inputs 1201 to 1206 are input to majority decision means 1230, and it is determined which logic is more. By giving the result as the selection signal s1240, the transition of the outputs 1211 to 1216 when the logic is fixed is minimized. As a result, the number of data transitions is reduced, so that current for charging / discharging does not flow, and power consumption can be further reduced.
[0048]
【The invention's effect】
When the input signal of the logic circuit is input via an inverter that can selectively fix the power supply or the ground to “0” or “1”, and when the logic circuit does not operate, the input signal value of the logic circuit is fixed. By doing so, it is possible to reduce power consumption by suppressing data transition by providing a means for fixing data input while suppressing an increase in chip area due to the addition of a circuit.
[0049]
In the second embodiment, the WELL of the transistor to which the output fixing signal is input to the power supply or the ground is separated, and the input of the output fixing signal is also input to this WELL to extract the electric charge from the output side of the inverter and to set the threshold of the pass transistor. Power consumption can be reduced by providing a means for fixing data input and suppressing data transition while suppressing a through current due to a value voltage and suppressing an increase in chip area due to the addition of a circuit.
[0050]
In the third embodiment, a majority decision unit is provided to check an input signal value, and a value to be fixed is determined by an output fixed signal generation unit, thereby suppressing an increase in chip area due to addition of a circuit. Low power consumption can be achieved.
[0051]
In the above description, an inverter is used as a circuit constituting the input unit. However, the circuit constituting the input unit can be realized by using other logic circuits.
Although the case where the signal input to the input unit is output from the first logic circuit has been described, the same configuration can be used even when a signal input from outside the semiconductor integrated circuit is directly input.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a semiconductor integrated circuit that achieves low power consumption according to the present invention; FIG. 2 is a configuration diagram of a “0” fixed inverter according to the first embodiment of the present invention; FIG. FIG. 4 is a layout diagram of a “1” fixed inverter according to the first embodiment of the present invention. FIG. 5 is a layout diagram of a “1” fixed inverter according to the first embodiment of the present invention. FIG. 6A is a configuration diagram of a “0” fixed inverter according to a second embodiment of the present invention; FIG. 6B is a structural cross-sectional view of a “0” fixed inverter according to a second embodiment of the present invention; Layout diagram of “0” fixed inverter according to the second embodiment. FIG. 8 (a) Configuration diagram of “1” fixed inverter according to the second embodiment of the present invention (b) “1” according to the second embodiment of the present invention Structure of fixed inverter FIG. 9 is a layout diagram of a “1” fixed inverter according to a second embodiment of the present invention. FIG. 10 (a) is a configuration diagram of an inverter according to a third embodiment of the present invention. FIG. 11 is a diagram showing a truth table of a control signal generating unit. FIG. 11 is a sectional view of the structure of an inverter according to a third embodiment of the present invention. FIG. 12 is a semiconductor integrated circuit with low power consumption according to a third embodiment of the present invention. FIG. 13 is a configuration diagram of a conventional semiconductor integrated circuit with low power consumption.
110 input section 111 input section inverter 112 input section inverter 113 input section inverter 114 input section inverter 115 input section inverter 116 input section inverter 120 processing section 140 second logic circuit s111o input section output s112o input section Output s113o input section output s114o input section output s115o input section output s116o input section output s150 output fixed signal 260 pMOS
s220 Fixed output signal 301 Fixed output signal generating means 320 Separated power supply 330 Inverter 340 at input section Inverter 350 at input section 360 Inverter 370 at input section Inverter 380 at input section 380 Inverter at input section s420 Output fixed signal 470 nMOS
525 Separate ground 530 Input inverter 540 Input inverter 550 Input inverter 560 Input inverter 570 Input inverter 580 Input inverter s620 Output fixed signal 630 pMOS
640 nMOS
660 output 670 nWELL
n600 node 710 nWELL
790 Contact with separated nWELL s820 Output fixed signal 840 nMOS
870 pWELL isolated
915 Isolated pWELL
990 Contact between the processing unit and the separated pWELL s1000 Selection signal s1010 Fixed output control signal 1020 Control signal generation means 1050 Control signal 1060 Control signal 1070 Inverter circuit s1100 Selection signal 1171 Output 1201 Input 1202 Input 1203 Input 1204 Input 1205 Input 1206 Input 1211 Output 1212 output 1213 output 1214 output 1215 output 1216 output 1230 majority decision means s1240 selection signal 1251 inverter 1252 inverter 1253 inverter 1254 inverter 1255 inverter 1256 inverter 1300 first logic circuit 1310 input section 1311 AND circuit 1312 AND circuit 1313 AND circuit 1314 AND circuit 1315 AND circuit 131 AND circuit 1320 processor 1340 second logic circuit s1350 output fixing signal

Claims (9)

A processing unit whose circuit operation may be stopped according to an operation situation, and an input unit inserted immediately before the processing unit of a signal line input to the processing unit,
Output fixed signal generating means for selecting and supplying a voltage to be supplied to the power supply of the input unit, and supplying a ground voltage from the output fixed signal generating means to fix the output value of the input unit to low. A semiconductor integrated circuit characterized by the above-mentioned. A processing unit whose circuit operation may be stopped depending on the operation status;
An input unit inserted immediately before the processing unit of a signal line input to the processing unit;
Output fixed signal generating means for selecting and supplying a voltage to be supplied to the ground of the input section, and supplying a power supply voltage from the output fixed signal generating means to fix the output value of the input section to high. A semiconductor integrated circuit characterized by the above-mentioned. 2. The effect of IR drop is suppressed by arranging a circuit constituting the input unit near a power supply wiring and minimizing a power supply wiring length from the power supply wiring to the circuit. A semiconductor integrated circuit as described in the above. 3. The effect of IR drop is suppressed by arranging a circuit constituting the input unit near a ground line and minimizing a ground line length from the ground line to the circuit. Semiconductor integrated circuit. Separating the n-well region of the input unit from the n-well region of the processing unit, and connecting the power supply of the input unit to the separated n-well region of the input unit, thereby extracting charges on the drain side of the transistor. The semiconductor integrated circuit according to claim 1 or 3, wherein: Separating the p-well region of the input unit from the p-well region of the processing unit and connecting the p-well region of the separated input unit to the ground of the input unit, thereby extracting charges on the drain side of the transistor; The semiconductor integrated circuit according to claim 2 or 4, wherein: A processing unit whose circuit operation may be stopped depending on the operation status;
An input unit inserted immediately before the processing unit of a signal line input to the processing unit;
Output fixed signal generation means for selecting and supplying a voltage to be supplied to a power supply and a ground of the input unit, and separating an n-well region of a pMOS transistor of the input unit from an n-well region of the processing unit; A voltage supplied from the output fixed signal generating means to the n-well region of the pMOS transistor is supplied to the source of the pMOS transistor, and supplied from the output fixed signal generating means to the p-well region of the nMOS transistor in the input section. Another voltage is supplied to the source of the nMOS transistor, and a ground voltage is supplied from the output fixed signal generating means to the source of the pMOS transistor of the input section, thereby fixing the output value of the input section to low, or From the fixed signal generating means, the source of the nMOS transistor The semiconductor integrated circuit characterized by high fixing the output value of the input unit by supplying a power supply voltage to. A processing unit whose circuit operation may be stopped depending on the operation status;
An input unit inserted immediately before the processing unit of a signal line input to the processing unit;
Output fixed signal generating means for selecting and supplying a voltage to be supplied to a power supply and a ground of the input unit, respectively, separating a p-well region of the nMOS transistor of the input unit from a p-well region of the processing unit, A voltage supplied from the output fixed signal generating means to a p-well region of the nMOS transistor is supplied to a source of the nMOS transistor, and supplied from the output fixed signal generating means to an n-well region of the pMOS transistor in the input section. Another voltage is supplied to the source of the pMOS transistor, and a ground voltage is supplied from the output fixing signal generating means to the source of the pMOS transistor of the input unit, thereby fixing the output value of the input unit to low, or From the output fixed signal generating means, the source of the nMOS transistor in the input section is The semiconductor integrated circuit characterized by high fixing the output value of the input unit by supplying a power supply voltage to the scan. A majority decision means for selecting a signal value having the largest number of inputs by classifying a signal value input to the input unit, and a power supply and a ground voltage output from the output fixed signal generation means based on a result of the majority decision means. 9. The semiconductor integrated circuit according to claim 7, wherein by controlling, a fixed output value of the input unit is controlled in consideration of an input signal value of the input unit when the circuit operation is stopped. .

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