JP2004039893A - Semiconductor device using different material - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain such a semiconductor device that is superior in breakdown strength, low in voltage drop at pn joint and in contact resistance with an electrode, and small in leak current. <P>SOLUTION: The semiconductor device is formed by laminating a surface electrode 28, an SiGe layer 26, and Si layers 24 and 22 in sequence. The SiGe layer 26 is of a first conductive type, the Si layer 24 on the side of the SiGe layer is of a first conductive type, the Si layer 22 on the opposite side thereof is of a second conductive type, and a pn joint is formed between the Si layer 24 and the Si layer 22. The SiGe layer is made of Si<SB>1-x</SB>Ge<SB>x</SB>, where x is substantially 0.0 in a part contact with the Si layer and 1.0 in a pact contact with the surface electrode and x continuously changes therebetween. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
The present invention relates to a semiconductor device using a heterojunction. In particular, the present invention relates to a technique for reducing a leakage current caused by various defects that cannot be avoided at a heterojunction.
[0002]
2. Description of the Related Art A technique using a heterojunction has been proposed in order to reduce the ON voltage of a semiconductor device, reduce switching loss, and the like.
[0003]
For example, Japanese Patent Application Laid-Open No. 8-37294 discloses an IGBT (Insulated Gate Bipolar Transistor). In order to realize a pn junction, a second conductivity type (p ⁺ ) is formed on a first semiconductor layer of a first conductivity type (p ⁺ ). This shows a technique in which a second (n ⁻ ) second semiconductor layer is stacked using a semiconductor material having a larger (wider) band gap than the first semiconductor layer. Specifically, silicon with a wide band gap is stacked on germanium with a narrow band gap, and germanium is set as a first conductivity type (p ⁺ ) and silicon is set as a second conductivity type (n ⁻ ). A technique for reducing the ON voltage of an IGBT by using a heterojunction is disclosed.
When the pn junction is formed of a heterojunction, the characteristics of the semiconductor device are degraded due to various kinds of defects that cannot be avoided at the heterojunction. JP-A-8-37294 discloses a layer of a first semiconductor material having a narrow band gap of a first conductivity type (p ⁺ ) and a layer of a first semiconductor material having a narrow band gap of a second conductivity type (n ⁻ ). Also disclosed is a semiconductor device in which a layer of a second semiconductor material of a second conductivity type (n ⁻ ) having a wide band gap is stacked. By using this structure, the pn junction and the heterojunction can be separated, and the characteristics of the semiconductor device can be prevented from deteriorating due to various defects that cannot be avoided at the heterojunction. A similar structure is also described in JP-A-2000-58819.
[0004]
In the technique described in Japanese Patent Application Laid-Open No. 8-37294, a pn junction is formed using a semiconductor material having a narrow band gap. In this case, the leak current tends to increase. Therefore, Japanese Patent Application Laid-Open No. 2000-357801 discloses a technique in which a pn junction is separated from a heterojunction and a pn junction is formed using a semiconductor material having a wide band gap. Specifically, a layer of first semiconductor material a narrow band gap of the first conductivity type (p ^+), a layer of a wide band gap of the first conductivity type (p ⁺⁾ second semiconductor material, the second conductive A semiconductor device in which a type (n ⁻ ) wide band gap second semiconductor material layer is stacked is disclosed. In this case, since the pn junction is formed using the second semiconductor material having a wide band gap, the leakage current is suppressed.
In the technique described in Japanese Patent Application Laid-Open No. 2000-357801, the ON voltage can be reduced by using a heterojunction, and the leakage current is suppressed by forming a pn junction using a semiconductor material having a wide band gap. This can prevent the characteristics of the semiconductor device from deteriorating due to various defects that are unavoidable to occur at the heterojunction to separate the pn junction and the heterojunction. If a defect exists in the pn junction, the leakage current increases. Therefore, the leakage current can be suppressed by separating the pn junction from the hetero junction.
[0005]
According to the technique described in Japanese Patent Application Laid-Open No. 2000-357801, the ON voltage can be reduced, and the leak current can be suppressed. However, it is required to further suppress the leak current.
[0006]
According to the technique described in Japanese Patent Application Laid-Open No. 2000-357801, a pn junction is formed by using a semiconductor material having a wide band gap, and a leakage is achieved by separating a pn junction from a hetero junction. Suppress current. The inventors' research has revealed that the latter technical element has room for further improvement. The present inventors have found that even if the pn junction and the heterojunction are separated, various defects that cannot be avoided at the heterojunction are distributed to the pn junction. If various defects generated in the hetero junction can be prevented from being distributed to the pn junction, the leak current can be more effectively suppressed.
[0007]
A semiconductor device created by the present invention is a semiconductor device in which a planar electrode, a first semiconductor material layer, and a second semiconductor material layer are laminated in that order, and a heterojunction is formed by the first semiconductor material layer and the second semiconductor material layer. Is configured. The first semiconductor material layer is of the first conductivity type, and the first semiconductor material layer side of the second semiconductor material layer is of the first conductivity type. Both sides of the heterojunction are of the first conductivity type and are separated from the pn junction. The opposite side of the second semiconductor material layer is of the second conductivity type, and a pn junction is formed between the second semiconductor material layer of the first conductivity type and the second semiconductor material layer of the second conductivity type. The pn junction is composed of a homojunction. The first semiconductor material is a composite material of a material having a band gap smaller than the band gap of the second semiconductor material and a second semiconductor material, and the ratio of the material having the small band gap is small on the second semiconductor material layer side. Large on the electrode side.
[0008]
The pn junction of the above semiconductor device is formed in the second semiconductor material layer having a larger band gap than the first semiconductor material, so that a leak current is suppressed.
The pn junction is formed in the second semiconductor material layer and is separated from a hetero junction formed at an interface between the first semiconductor material layer and the second semiconductor material layer. Moreover, the first semiconductor material is a composite material, and the second semiconductor material layer is mainly made of a semiconductor material having a small band gap on the side of the planar electrode, which is equal to or close to the second semiconductor material.
Since the first semiconductor material layer having a small band gap is used, the on-state voltage is reduced. Since the composition ratio of the first semiconductor material composed of the composite material is changed, the lattice strain is suppressed to a small value, and the generation of defects is suppressed. Since the density of occurrence of defects is kept low, and the pn junction is separated from the hetero junction, the defect density at the pn junction is kept low. For this reason, the leakage current generated when a defect exists in the pn junction is suppressed to a small value.
The semiconductor device of the present invention reduces the on-state voltage by using a heterojunction, suppresses a leak current by forming a pn junction in a semiconductor material having a wide band gap, and reduces the composition ratio of the material forming the heterojunction. The occurrence of defects is suppressed by elimination, and the occurrence of defects at the pn junction is further suppressed by separating the pn junction from the heterojunction. Leakage current caused by defects at the pn junction is reduced. Effectively suppress.
[0009]
In the case of a semiconductor device using silicon as a substrate, it is preferable to use SiGe as a semiconductor material having a smaller band gap than silicon.
The semiconductor device in this case is a semiconductor device in which a planar electrode, a SiGe layer, and a Si layer are stacked in this order. The SiGe layer is of the first conductivity type. The SiGe layer side of the Si layer is of the first conductivity type and the opposite side is of the second conductivity type, and a pn junction is formed between the two. SiGe layer is composed of _{Si 1-x} Ge x, x in the portion in contact with the Si layer is substantially 0.0, the portion in contact with the planar electrode is substantially 1.0, x is In the meantime, it changes continuously. The continuously changing mode includes changing stepwise.
[0010]
In the case of the above semiconductor device, since the pn junction is formed in the silicon layer having a large band gap, the leakage current is smaller than that in the case where the pn junction is formed in the SiGe layer having a small band gap. The pn junction is separated from the heterojunction, further SiGe layer is composed of _{Si 1-x} Ge x, x in the portion in contact with the Si layer is substantially 0.0 (i.e., Si is mainly ), The lattice mismatch rate of the heterojunction is kept small, and defects at the pn junction are extremely small. Leakage current due to defects present at the pn junction is kept small. Also, x in the portion in contact with the electrodes of the Si _1-x Ge _x layer is substantially 1.0 from (i.e., Ge is a is mainly) that the band gap is connected to the electrode through a small layer As a result, the contact resistance is suppressed, and the on-voltage is suppressed low. At the time of turn-off, electrons can easily escape from the pn junction, and the turn-off loss is small.
[0011]
Si _1-x Ge _x layer _{Si 1-x} Ge x C layer may also be used in place of. Also in this case, the advantages described in paragraph 0010 can be enjoyed.
[0012]
It is preferable that the impurity concentration of the SiGe layer is higher than that of the Si layer forming the pn junction. In particular, it is preferable that the impurity concentration of the SiGe layer be 1 × 10 ¹⁸ cm ⁻¹⁸ or more.
In this case, the resistance can be sufficiently reduced by sufficiently increasing the impurity concentration of the SiGe layer. Further, the contact resistance with the planar electrode can be sufficiently reduced.
[0013]
The impurity concentration of the first conductivity type Si layer is higher than the impurity concentration of the second conductivity type Si layer, and the impurity concentration of the first conductivity type SiGe layer is higher than the impurity concentration of the first conductivity type Si layer. Is preferred.
In this case, a sufficient withstand voltage can be ensured by the Si layer having the low impurity concentration of the second conductivity type. It is possible to prevent a band offset from occurring between the Si layer having the middle impurity concentration of the first conductivity type and the SiGe layer having the higher impurity concentration. Since band offset cannot be performed, the ON voltage required to make the semiconductor layer conductive can be kept low.
[0014]
A SiGe layer or a SiGeC layer in contact with the Si layer can be formed by CVD. Alternatively, molecular beam epitaxy (MBE: Molecular Beam Epi ^- taxy) or atomic layer epitaxy (ALE: Atomic layer Epi ^- taxy) can also be used. Further, a Ge layer or a GeC layer is deposited on the surface of the Si layer, and the deposited Ge layer or the GeC layer is melted and then cooled, so that the Ge layer or the GeC layer is dissolved in the Si layer to form a SiGe layer or a SiGeC layer. Layers can be formed.
[0015]
A step of deeply implanting the first conductivity type ions from the surface of the second conductivity type Si substrate and then diffusing the first conductivity type ions; a step of shallowly implanting the first conductivity type ions from the ion-implanted surface; depositing a Ge, the deposited Ge can produce a semiconductor device of the heat treatment and run to the present invention a process for forming a Si _1-x Ge _x of the first conductivity type.
In this case, a pn junction is formed in the Si substrate, and a semiconductor device in which _x of Si _1-x Gex is small on the Si substrate side and large on the surface side can be relatively easily produced.
[0016]
When a GeC layer is deposited instead of a Ge layer and the above method is performed, a semiconductor device having a SiGeC layer is produced.
[0017]
After ion implantation, heat treatment is preferably performed at a temperature of 600 ° C. or less. Alternatively, it is preferable to heat the surface of the deposited Ge layer or GeC layer above the melting point and maintain the temperature of the Si layer at 600 ° C. or less during the heating.
In this case, a semiconductor device can be produced without deteriorating the characteristics of the Si layer.
[0018]
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The main features of the embodiments described below are listed first. (Feature 1) A state where _x of the p ⁺ collector region or the p ⁺ anode region composed of Si _1-x Ge _x is substantially 0.0 to substantially 1.0 is applied by 5.5 nm or more. A semiconductor device characterized by being changed.
In this case, when changing the value of x in a stepwise manner for each atomic layer, the width of change can be suppressed to 0.1 or less, and the effect of distortion can be substantially reduced.
(Embodiment _{2) Si 1-x} Ge x of x has changed stepwise, if the layer of x = of 0.99 adjacent to x = 1.0 is located, x = 1.0 in A semiconductor device having a layer thickness of 1 μm or less.
When the thickness of the layer where x = 1.0 is 1 μm or less, it is possible to prevent the occurrence of dislocation in the Ge layer adjacent to the layer where x = 0.99.
(Embodiment _{3) Si 1-x} Ge x of x has changed stepwise, if the layer of x = 0.9 adjacent to x = 1.0 is located, x = 1.0 in A semiconductor device having a layer thickness of 0.1 μm or less.
When the thickness of the layer where x = 1.0 is 0.1 μm or less, it is possible to prevent the occurrence of dislocation in the Ge layer adjacent to the layer where x = 0.9.
[0019]
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 shows a configuration when the present invention is applied to an IGBT. p ⁺ lower on the collector region 26 impurity concentration than the ^{p +} collector region 26 p ^- collector region 24 is formed, p ^- n on the collector region 24 ^- drift region 22 is formed. A p base region 16 is formed on n ⁻ drift region 22, and an n ⁺ emitter region 12 and a p ⁺ body region 14 are formed in p base region 16. A trench type gate electrode 18 is formed through a gate oxide film 20 so as to penetrate the n ⁺ emitter region 12 and the p base region 16. The emitter electrode 10 is connected to the n ⁺ emitter region 12 and the p ⁺ body region 14. The silicon oxide film 8 insulates between the emitter electrode 10 and the gate electrode 18. The gate electrode 18 is connected to a gate pad formed on the surface of the semiconductor device in a cross section (not shown). Collector electrode 28 is in planar contact with p ⁺ collector region 26.
[0020]
The p ⁺ collector region 26 is formed of SiGe, and the p ⁻ collector region 24, the n ⁻ drift region 22, the p base region 16, the n ⁺ emitter region 12, and the p ⁺ body region 14 are formed of Si. The p ⁺ collector region 26 uses a semiconductor material having a smaller band gap than the p ⁻ collector region 24 and the n ⁻ drift region 22, and reduces the barrier of electrons flowing into the collector electrode at the time of turn-off to reduce switching loss. Can be.
p ⁺ collector region 26 is formed by _{Si 1-x} Ge _x. X is substantially 0.0 in a portion in contact with the p ^- collector region 24 made of Si, x is substantially 1.0 in a portion in contact with the collector electrode 28, and x is continuous between them. Has changed. Si is on the surface in contact with the p ^- collector region 24, Ge becomes richer as it approaches the collector electrode 28, and becomes Ge on the surface in contact with the collector electrode 28.
[0021]
The p ⁺ collector region 26 is a first semiconductor material layer, the p ⁻ collector region 24 and the n ⁻ drift region 22 are second semiconductor material layers, and the first semiconductor material layer is of a first conductivity type (p type in this case). The region of the second semiconductor material layer on the first semiconductor material layer side, that is, the p ⁻ collector region 24 is of the first conductivity type (p), and the region on the opposite side (p base region 16 side), that is, n ⁻ Drift region 22 is of the second conductivity type (n-type), and a pn junction is formed between p ⁻ collector region 24 and n ⁻ drift region 22. The first semiconductor material (SiGe in this case) is a composite material of a material (Ge) having a band gap smaller than the band gap of the second semiconductor material (Si in this case) and the second semiconductor material (Si), and has a small band gap. The proportion of the material having a gap (Ge) is small on the side of the second semiconductor material layer (p ^- collector region 24) and large on the side of the planar electrode (collector electrode 28).
[0022]
p ^- By forming the collector region 24, p ⁺ collector region 26 and p ^- to form a heterojunction at the interface between the collector region 24, a location other than the heterojunction, i.e. p ^- collector region 24 and n ^- Since the pn junction is formed at the interface with the drift region 22, the influence of the level density at the heterojunction interface and its variation on the characteristics of the semiconductor device can be reduced. By forming the thick p ⁺ collector region 26 and the thin p ⁻ collector region 24, both low collector resistance and low pn junction voltage can be achieved. Also in this IGBT, a high breakdown voltage can be obtained because the pn junction is formed of Si having a larger band gap than SiGe of the p ⁺ collector region 26. Since the p ^- collector region 24 exists, the amount of injected holes can be suppressed. Further, the presence of the heterojunction makes it easy for electrons to escape to the collector electrode at the time of turn-off, and the turn-off loss is small. The impurity concentration of the p ⁺ collector region 26 can be set to 1 × 10 ¹⁸ cm ⁻¹⁸ or more, the collector resistance can be sufficiently reduced, and the contact resistance with the collector electrode can be sufficiently reduced.
[0023]
As described above, in the IGBT of the present embodiment, by providing the low-concentration p ⁻ collector region 24 between the p ⁺ collector region 26 and the n ⁻ drift region 22, the hetero junction and the pn junction are separated from each other. The resistance of the collector region can be reduced.
[0024]
FIG. 2 shows a method of manufacturing the IGBT shown in FIG. Ions are implanted from the upper surface of the n ^- silicon substrate 22 and thermally diffused to form a p base region 26 (A). Thereafter, a resist mask is formed using a photolithography technique, and ions are implanted and thermally diffused using the resist mask to form an n ⁺ emitter region 12 and a p ⁺ body region 14 in the p base region 16 ( B). After the n ⁺ emitter region 12 is formed, a resist mask is formed again by using the photolithography technique, and Si is dry-etched (for example, about 3 μm) using the resist mask to form the trench 6 (C). Then, a side wall of the trench is thermally oxidized to form an oxide film 20, and the trench 6 is filled with polycrystalline Si by a CVD method to form a gate electrode 18 (D). After that, the emitter electrode 10 is formed by using the photolithography technique and the dry etching, and the oxide film 8 is further formed (E).
[0025]
Next, the lower surface of n ^- silicon substrate 22 is polished to adjust the thickness to a predetermined thickness, and ions are implanted deeply from the lower surface and thermally diffused to form p ^- collector region 24 (F). Next, ions are implanted shallowly from the lower surface of p ⁻ collector region 24 to form p ⁺ silicon region 26a. Next, a Ge layer 26b is deposited on the lower surface of the p ⁺ silicon region 26a (H). Next, the lower surface of the Ge layer 26b is irradiated with a laser to rapidly heat the Ge layer 26. At this time, the Ge layer 26 is melted and cooled. Molten Ge to form a _{Si 1-x} Ge _x layer 26 of ^{p +} diffused by entering the ^{p +} silicon region 26a. While the Ge layer 26 is rapidly heated and cooled, the Si layer 24 is maintained at a temperature of 600 ° C. or less, and the characteristics of Si do not deteriorate. Finally, form the collector electrode 28 on the lower surface of the _{Si 1-x} Ge _x layer 26.
In the above, Ge was melted and penetrated into Si to form a SiGe layer. Alternatively, Ge ions can be implanted to form a SiGe layer. By adjusting the implantation energy of Ge ions, a Si _1-x Ge _x layer in which _x varies between 0 and 1 can be formed.
Si _1-x Ge _x layer 26 p in the upper ^- in a portion in contact with the collector region 24 (Si layer) x is substantially 0.0, x is substantially at the portion in contact with the collector electrode 28 on the lower side 1.0, and x changes continuously between them.
Note that, on the lower surface of the p ^- collector region 24 (Si layer), x is set to 0.0 using molecular beam epitaxy (MBE) or atomic layer epitaxy (ALE). it is also possible to deposit a _{Si 1-x} Ge _x layer 26 varies gradually between 1.0 and. Alternatively, it can be deposited by a CVD method.
[0026]
In the present embodiment, it is realized heterojunction Si and Si _1-x Ge _x, can be formed of other semiconductor materials. The condition is that the band gap of the p ⁺ collector region 26 is smaller than that of the p ⁻ collector region 24, and for example, Si / SiGeC can be used. The band gap of SiGeC is smaller than that of Si.
Depending on the method of depositing a GeC layer on the Si layer and rapidly heating it to inject GeC into the Si layer, or the method of implanting Ge and C ions into the Si layer, x varies between 0 and 1. _{A 1-x} Ge _x C layer can be formed.
In this embodiment, the first conductivity type is p-type and the second conductivity type is n-type. However, p and n may be interchanged.
[0027]
FIG. 3 shows a configuration in which the present invention is applied to a heterojunction diode. An n ⁻ cathode region 32 is provided below the n ⁺ cathode region 30, and a p ⁻ anode region 34 is provided below the n ⁻ cathode region 32. A p ⁺ anode region 36 is provided below the p ⁻ anode region 34. The cathode electrode 29 is connected to the n ⁺ cathode region 30, and the anode electrode 38 is connected to the p ⁺ anode region 36. p ⁺ anode region 36 is formed by _{Si 1-x} Ge _x layer, the upper with p ^- in the portion in contact with the anode region 34 (Si layer) is substantially 0.0, the portion in contact with the anode electrode 38 on the lower side Where x is substantially 1.0, and x varies continuously between them. The p ^- anode region 34 and the n ^- cathode region 32 are formed of Si.
The p ⁺ anode region 36 is formed of a semiconductor material having a smaller band gap than the p ⁻ anode region 34 and the n ⁻ cathode region 32, and a hetero junction is formed at the interface between the p ⁺ anode region 36 and the p ⁻ anode region 34. You. On the other hand, ap ⁻ anode region 34 is formed adjacent to the p ⁺ anode region 36, and the n ⁻ cathode region 32 is in contact with the p ⁻ anode region 34. That is, it is formed at the interface between the p ^- anode region 34 and the n ^- cathode region 32 having a large band gap.
The p ⁺ anode region 36 corresponds to a first conductive type (here, p-type) first semiconductor material layer, the p ⁻ anode region 34 corresponds to a first conductive type second semiconductor material layer, and the n ⁻ cathode region. Reference numeral 12 corresponds to a second semiconductor material layer of a second conductivity type (here, n-type).
[0028]
pn junction ^{p +} anode region 36 and n ^- instead of being formed at the interface between the cathode region 32, a lower impurity concentration than ^{p +} anode region 36 p ^- the provided anode region 34, the p ^- anode region The potential difference (Vbi) at the pn junction can be reduced by forming it at the interface between the n ^-type cathode region 34 and the n ⁻ cathode region 32. In addition, since the pn junction is not formed in a semiconductor having a small band gap, but is formed in an interface between Sis having a large band gap, the maximum breakdown electric field is increased and a high breakdown voltage can be achieved. Furthermore, since the pn junction is formed at the interface between the p ^- anode region (Si) 34 and the n ^- cathode region (Si) 32, which are homojunctions, the lattice matching is improved as compared with the case where the pn junction is formed at the hetero junction. In addition, the junction leakage current at the time of reverse bias is reduced, and the withstand voltage can be increased.
In this embodiment, the p ⁺ anode region 36 can be single crystal, polycrystal, or amorphous.
[0029]
According to the present invention, the heterojunction and the pn junction are separated from each other, and the pn junction is formed of a semiconductor material having a large band gap. In addition, the leak current can be suppressed, and the maximum breakdown electric field can be increased to obtain a high breakdown voltage. Furthermore, since one material constituting the heterojunction is a composite material of the other material and a semiconductor material having a smaller band gap than that of the other material, since the composition ratio of the semiconductor material having a smaller band gap is varied, The lattice mismatch rate at the heterojunction interface can be reduced to reduce the defect generation density, and the leakage current can be further suppressed.
[Brief description of the drawings]
FIG. 1 is a sectional view of an IGBT according to a first embodiment of the present invention.
FIG. 2 is a diagram illustrating a manufacturing process of the IGBT according to the first embodiment of the present invention.
FIG. 3 is a sectional view of a diode according to a second embodiment of the present invention.
[Explanation of symbols]
16 and 20: the first semiconductor material layer of a first conductivity _{^{type, p + Si 1-x Ge}} x layer 14 and 22: the second semiconductor material layer of a first conductivity ^{type, p} - Si layer 12, 24: second conductive -Type second semiconductor material layer, n ^- Si layer

Claims (11)

A semiconductor device in which a planar electrode, a first semiconductor material layer, and a second semiconductor material layer are stacked in this order, wherein the first semiconductor material layer is of a first conductivity type, and a first semiconductor material layer of the second semiconductor material layer The side is of the first conductivity type and the opposite side is of the second conductivity type, and a pn junction is formed between the two. The first semiconductor material is a material having a band gap smaller than the band gap of the second semiconductor material. And a second semiconductor material, wherein the proportion of the material having a small band gap is small on the second semiconductor material layer side and large on the planar electrode side. This is a semiconductor device in which a planar electrode, a SiGe layer, and a Si layer are stacked in this order, the SiGe layer is of a first conductivity type, the SiGe layer side of the Si layer is of a first conductivity type, and the opposite side is a second conductivity type. type a was pn junction therebetween are formed, SiGe layer is composed of _{Si 1-x} Ge x, x in the portion in contact with the Si layer is substantially 0.0, the planar electrode Wherein x substantially equals 1.0 at a portion in contact with x, and x continuously changes between them. Si _1-x Ge _x layer semiconductor device according to claim 2 using a _{Si 1-x} Ge x C layer instead. 4. The semiconductor device according to claim 2, wherein the impurity concentration of the SiGe layer or the SiGeC layer is higher than the impurity concentration of the Si layer forming the pn junction. The impurity concentration of the first conductivity type Si layer is higher than the impurity concentration of the second conductivity type Si layer, and the impurity concentration of the SiGe layer or the SiGeC layer is higher than the impurity concentration of the first conductivity type Si layer. 4. The semiconductor device according to claim 2, wherein: 6. The semiconductor device according to claim 2, wherein the SiGe layer or the SiGeC layer in contact with the Si layer is a layer formed by CVD. 6. The semiconductor device according to claim 2, wherein the SiGe layer or the SiGeC layer in contact with the Si layer is a layer in which the Ge layer or the GeC layer deposited on the surface of the Si layer is dissolved in the Si layer. A step of deeply implanting the first conductivity type ions from the surface of the second conductivity type Si substrate and then diffusing the first conductivity type ions; a step of shallowly implanting the first conductivity type ions from the ion-implanted surface; depositing a Ge layer, with the deposited Ge layer to a heat treatment to the first conductivity type of the Si _1-x Ge _x layer to form a, pn junctions are formed in the Si substrate, Si _{1 how -x} Ge _x layer of x to produce a large semiconductor device on the surface side is small in the Si substrate side. 9. The production method according to claim 8, wherein a GeC layer is deposited instead of the Ge layer. The method according to claim 8, further comprising a step of performing a heat treatment at a temperature of 600 ° C. or less after the ion implantation. The method according to any one of claims 8 to 10, wherein the surface of the deposited Ge layer or GeC layer is heated to a temperature equal to or higher than the melting point and the temperature of the Si layer is maintained at 600 ° C or lower.

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