JP2003243980A - Pll circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a PLL circuit in which stable output can be obtained even in the case of switching without causing phase deviation between a reference clock and a compare clock when switching the reference clock and further the stable output can be realized with simple configuration by controlling the phase of the compare clock. <P>SOLUTION: The PLL circuit is provided with a switching clock selector for a plurality of clock signals and a timing generator for inputting a clock switching signal and the plurality of clock signals and outputting a clock select signal to a switching clock selector and when switching from an active clock signal to another clock signal, a timing generating circuit switches the clock signal and resets a frequency divider or loads a prescribed value in the fall timing of the relevant instructed clock signal. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL (Phase Loc) constructed so as to operate as a reference clock by selecting and switching a plurality of clock signals for active system and standby system.
ked loop) circuit, and more particularly to a control method when switching a reference clock.

[0002]

2. Description of the Related Art A PLL circuit configured to select and switch a plurality of clock signals to operate as a reference clock is used for various devices. A reference clock switching system in such a PLL circuit will be described with reference to the drawings. FIG. 11 shows a schematic block diagram of a conventional PLL circuit. Further, FIG. 12 is a timing chart showing the waveform of each part in the PLL circuit of FIG. This circuit has a well-known configuration, and an equivalent circuit is disclosed in, for example, Japanese Patent Application Laid-Open No. 3-22706.

In FIG. 12, it is assumed that the clock switching signal is asserted at time (T51) to switch the reference clock from clock A to clock B. Before the assertion, the reference clock (clock A) and the comparison clock are synchronized with each other by a known function of the PLL circuit, and for example, the time (T5
In 0), when the reference clock rises, the comparison clock also rises.

In this conventional circuit, only the reference clock is directly switched from the clock switching signal. Therefore, as shown in FIG. 12, when the clock switching signal is asserted (T51), immediately after (T5).
In 2), a phase difference between the comparison clock and the reference clock (clock B) occurs, and this is absorbed, so that the frequency of the output clock from the voltage controlled oscillator (VCXO) fluctuates for a certain period of time. Therefore, the PLL
An error may occur for a moment in the communication data processed by using the circuit, or the clock supplied to the subsequent PLL becomes unstable, which may cause inconvenience such as being temporarily unable to follow.

In order to solve this point, for example, as in Japanese Patent Laid-Open No. 3-22706, a frequency divider is provided at the input portion of the reference clock, the high speed clock is converted into the low speed clock, and the low speed clock is converted into the low speed clock. A method has been proposed in which the reference clock is input to the PLL circuit through a selection circuit, and the frequency shifter in the reference clock input section is reset to absorb the phase shift.

However, in the case of the above technique, the reference clock input section also requires a frequency divider. Further, in order to select a plurality of reference clocks, it is necessary to provide frequency dividers corresponding to the number of reference clocks to be selected and have means for resetting them, which causes a problem that the circuit configuration becomes complicated. .

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned actual situation in a PLL circuit, and by controlling the phase of the comparison clock, the phase difference between the reference clock and the comparison clock when the reference clock is switched. It is an object of the present invention to propose a PLL circuit that can obtain a stable output even at the time of switching and can be realized with a simple configuration.

[0008]

In order to solve the problems, according to the invention of claim 1, a clock selector for switching a working clock signal and a spare clock signal to supply as a reference clock, and a frequency divider for generating a comparison clock. In a PLL circuit configured to include an active clock and a standby clock, switching to the standby clock by the clock selector and resetting of the frequency divider are performed at the fall timing of the standby clock. A timing generator is provided.

The invention of claim 2 is the PL according to claim 1.
In the L circuit, the timing generator switches to the spare clock by the clock selector at the first falling edge of the spare clock when the clock selection signal from the switching instruction means is input, and The feature is that the frequency is reset.

According to a third aspect of the present invention, in the PLL circuit including a clock selector for switching between the working clock signal and the spare clock signal to supply it as a reference clock, and a frequency divider for generating a comparison clock, If the spare clock is at the H level when switching from the spare clock to the spare clock, the clock selection is switched and the frequency divider is reset at the next fall timing of the spare clock. When the spare clock is at the L level, the clock selector switches to the spare clock at the next rising timing of the spare clock, and the internal clock of the frequency divider for generating the comparison clock receives the comparison clock. It has a timing generator that loads the values so that it is the beginning of a rising edge.

According to a fourth aspect of the present invention, the PLL circuit selects and switches a plurality of clock signals and supplies them as a reference clock, a switching instruction means, a frequency divider for generating a comparison clock, and the switching. And a timing generator which receives the clock switching signal from the instruction means and each of the plurality of clock signals and outputs a clock selection signal to the switching clock selector, wherein the timing generation circuit switches from the working clock signal. When switching to another clock signal instructed by the instructing means, switching to the instructed clock signal by the clock selector and resetting of the frequency divider are performed at the falling timing of the instructed clock signal. Try to do it.

According to a fifth aspect of the present invention, the PLL circuit selects and switches a plurality of clock signals to supply as a reference clock, a switching clock selector, a switching instruction means, a frequency divider for generating a comparison clock, and the switching. And a timing generator which receives the clock switching signal from the instruction means and each of the plurality of clock signals and outputs a clock selection signal to the switching clock selector, wherein the timing generation circuit switches from the working clock signal. When switching to another clock signal instructed by the instructing means, if the instructed clock signal is at the H level, switching of clock selection and the frequency divider are performed at the next falling timing of this clock signal. However, if the specified clock signal is at L level, At the rising timing of the clock signal, switching to the clock signal instructed by the clock selector, and loading a value such that the comparison clock is at the beginning of the rising edge into the internal counter of the divider that generates the comparison clock To

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention comprises a switching clock selector for selecting and switching a plurality of clock signals and supplying it as a reference clock, a switching instruction means, and a frequency divider for generating a comparison clock. In the PLL circuit, when switching from one reference clock to another reference clock, the phase fluctuation (frequency fluctuation) of the output clock of the PLL can be minimized by adjusting the phase of the comparison clock to the reference clock. Characterize.

To this end, the PLL circuit of the present invention comprises a timing generator which receives the clock switching signal from the switching instructing means and a plurality of clock signals and outputs a clock selection signal to the switching clock selector. When the timing generation circuit switches from the current clock signal to another clock signal instructed by the switching instructing means, the clock selector switches the clock signal to the instructed clock signal at the falling timing of the instructed clock signal. Switch and reset the frequency divider.

Alternatively, when the timing generation circuit switches from the current clock signal to another clock signal instructed by the switching instructing means, if the instructed clock signal is at the H level, the next clock signal of this clock signal is output. The clock selection is switched and the frequency divider is reset at the falling timing. However, if the instructed clock signal is at the L level, the clock selector is switched at the rising timing of the clock signal. It is configured to switch to the clock signal instructed by, and to load the value such that the comparison clock is at the beginning of the rising edge into the internal counter of the frequency divider that generates the comparison clock.

Further, in an application in which only the working clock signal is switched to the spare clock signal, a clock selector and a frequency divider for generating a comparison clock are included, and when the working clock is switched to the spare clock, A timing generator for switching to the spare clock by the clock selector and resetting the frequency divider at the fall timing of the spare clock is provided.

Alternatively, as a timing generator, when the working clock is switched to the spare clock and the spare clock is at the H level, the clock selection is switched at the next fall timing of the spare clock, and The frequency divider is reset, but if the spare clock is at the L level, the clock selector switches to the spare clock and the comparison clock at the next rising timing of the spare clock. The internal counter of the frequency divider to be generated may be provided with a timing generator for loading a value such that the comparison clock is at the beginning of rising.

[First Embodiment] The present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 shows the P of the present invention.
A first embodiment of the LL circuit is shown in a schematic block diagram. The PLL circuit of the embodiment selects the PLL circuit main section 7, the clock A14 and the clock B15 input from the outside, and selects the PL.
It is composed of a switching clock selector 1 (hereinafter referred to as a selector 1) which is inputted to the L circuit main portion 7 as a reference clock, and a timing generator 6.

In this embodiment, the clock A is used as a current reference clock and the clock B is used as a spare reference clock.
It is assumed that some kind of failure occurs and the reference clock is switched to clock B. It is assumed that the clock A14 is used as a current reference clock and the clock B15 is used as a backup reference clock.
When a clock abnormality detection unit (not shown) detects an abnormality in the clock A, a clock switching signal is transmitted to this circuit.

The PLL circuit main part 7 is composed of a phase comparator 2, a low pass filter 3, a voltage controlled oscillator (VCXO) 4 and a frequency divider 5 in a known part.
The comparison clock 10 input to the PLL circuit main unit 7 is selected by the selector 1. The clock A14 and the clock B15 are input to the selector 1 and also to the timing generator 6.

The clock switching signal 13 is the clock A.
When the abnormality of 14 occurs, the timing generation circuit 6 is asserted. Further, a clock switching signal 13 is inputted to the timing generator 6, and the clock switching signal 1
3 is asserted, the clock selection signal 8 is sent to the selector 1 at the next falling timing of the clock B15.
And the reset signal 9 is output to the frequency divider 5. When the reset signal 9 is asserted, the frequency divider 5 clears the internal counter value and starts output from the falling edge. That is, the comparison clock 11 is at the beginning of the fall.

Next, the operation of this embodiment will be described with reference to FIGS.
This will be described in detail with reference to FIG. 2 to 5 are timing charts showing operation waveforms of respective parts in the PLL circuit of FIG. Clock signal selected by the selector 1 (usually the clock A14 is selected)
Is input to the PLL circuit main section 7 as the reference clock 10, the phase difference from the comparison clock 11 is compared by the phase comparator 2. The phase comparator 2 outputs a phase information signal 16 as a result of the phase comparison. The phase information signal 16 is smoothed by the low pass filter 3 and converted into a frequency control voltage signal 17. The VCXO 4 outputs an output clock 12 having a frequency corresponding to the voltage of the frequency control voltage signal 17 that has been input. The clock signal 12 is a frequency divider 5
Is divided into low-frequency clock signals at
It is output as 1 to the phase comparator 2.

The PLL circuit main section 7 operates to increase the frequency of the output clock 12 when the phase of the comparison clock 11 is ahead of the reference clock 10 and to decrease the frequency when the phase of the comparison clock 11 is behind. As the frequency of the output clock 12 increases, the cycle becomes shorter, so the phase of the comparison clock operates in a direction lagging behind the reference clock. On the contrary, since the cycle becomes longer as the frequency of the output clock 12 becomes lower, the phase of the comparison clock operates in the direction of advancing with respect to the reference clock.

The timing chart of FIG. 2 shows an example of timing waveforms before and after the reference clock is switched from the working clock to the backup clock. At time T1, the clock switching signal (asserted when H level) is negated at L level, and the clock selection signal is also clock A selected (clock L selection at L level, clock B selection at H level).
In addition, it is a steady state in which the phases of the reference clock and the comparison clock match. Next, at T2, the clock switching signal becomes asserted. However, as described above, as the clock selection signal, the clock A selection is continued until the standby clock signal falls, that is, until the timing of T3.

T3 is the falling timing of the clock B. At this timing, the timing generator 6 sets the clock selection signal to the H level (clock B selection), so that the clock B is output as the reference clock. The timing generator 6 asserts a reset signal (L level pulse) at the same timing to clear the counter of the frequency divider. Although the counter operation of the frequency divider is stopped by the pulse width of the reset signal (L level time),
This is the width of the range that does not affect the phase comparison between the reference clock and the comparison clock. Therefore, almost simultaneously with the fall of the reference clock based on the clock B, the comparison clock falls and the counter of the frequency divider 5 starts operating from the beginning. T4, which is the next rising edge of the reference clock
At this timing, the comparison clock rises, so there is no phase shift immediately after switching the reference clock.

FIG. 3 shows a waveform example when the clock switching signal 13 is asserted at time (T6), that is, when both the clock A and the clock B are at the H level. Also in this case, the clock selection signal 8 falls at the falling edge of the clock B (spare clock) 15, that is, T
The reference signal is output when the timing of 7 is reached. Before and after the switching, the reference clock and the comparison clock are not out of phase at the timings of T5 and T8.

In FIG. 4, when the clock switching signal 13 is asserted at time (T10), that is, clock A
Shows an H level and a clock B is at an L level. Also in this case, the clock selection signal 8 falls on the clock B (spare clock) 15, that is,
At the timing of T11, the reference signal is output and switches. Further, before and after the switching, the phases are not deviated at the timings of T9 and T12.

In FIG. 5, when the clock switching signal 13 is asserted at time (T14), that is, clock A
2 shows a waveform when both the clock B and the clock B are at the L level. Also in this case, the clock selection signal 8 falls at the falling edge of the clock B (spare clock) 15, that is, T
At the timing of 15, the reference signal is output and is switched. Further, there is no phase shift before and after the switching and at the timings of T13 and T16.

In the embodiment circuit, the clock switching signal 13
At the first falling edge of the clock B after the assertion of
Asserts. Therefore, the clock switching signal 13
The clock selection signal and the divided cycle reset signal are asserted one cycle after the clock B is asserted at the maximum.

As described above, according to the embodiment, the phase shift between the reference clock and the comparison clock does not occur even when switching to the backup clock, and the PLL circuit can supply a stable clock even after switching. .

[Second Embodiment] Next, a second embodiment of the present invention will be described. FIG. 6 is a schematic block diagram showing a second embodiment of the PLL circuit of the present invention. The schematic configuration of this embodiment is similar to that of FIG. 1 (first embodiment). A selector 20 and a phase comparator 21, which constitutes the PLL circuit main part 26,
The low pass filter 22 and the VCXO 23 are the same as those in the first embodiment, but the functions of the frequency divider 24 and the timing generator 25 are different. In this embodiment, in addition to the configuration described in the first embodiment, not only the reset signal but also the load signal 27 can be newly output from the timing generator 25 to the frequency divider 24.

When the load signal 27 is asserted, the frequency divider 24 loads the internal counter with a value such that the comparison clock 31 starts to rise, and when the reset signal 28 is asserted, the internal counter value is cleared. The comparison clock 31 is at the beginning of the fall.

When the clock B34 is at the H level when the clock switching signal 35 is asserted, the timing generator 25 asserts the clock selection signal 29 and the reset signal 28 at the falling timing of the clock B34, When the clock B34 is at the L level, the clock selection signal 29 and the load signal 28 are asserted at the rising timing of the clock B34.

In the first embodiment described above, it takes a maximum of 1 clock B of the clock B from the assertion of the clock switching signal to the actual switching of the clock selection, but in the present embodiment, it can be shortened by half a clock. .

Next, the operation of this embodiment will be described with reference to FIGS. 6, 7 and 8. In this embodiment, when the clock B34 (standby clock) is at the L level at the time of clock switching, the clock B by the clock selector is generated at the next rising timing of the clock B34.
34, and the internal counter of the frequency divider 24 that generates the comparison clock 31 is loaded with a value such that the comparison clock is at the beginning of rising.

FIG. 7 shows an example of waveforms when the clock A is at the H level and the clock B is at the L level when the clock switching signal 35 is asserted. In this case, the clock selection signal 29 from the timing generator 25 to the selector 20 is switched at the next rising edge of the clock B, that is, at the timing of T22. Further, FIG. 8 shows the clock A when the clock switching signal 35 is asserted.
Shows an example of a waveform when is at L level and clock B is at L level. Also in this case, as in FIG. 7, the clock selection signal is the rising edge of the next clock B, that is, T2.
It switches when the timing of 6 is reached.

When switching clocks, clock B
If 34 (spare clock) is at the H level, clock selection is switched and the frequency divider is reset at the next fall timing of the spare clock as in the previous embodiment. That is, when the clock switching signal is asserted, the waveforms when the clock A is at the L level and the clock B is at the H level are the same as those in the first embodiment (see the waveform example in FIG. 2). The waveforms when the clock A is at the H level and the clock B is at the H level when the clock switching signal is asserted are similar to the waveforms of the first embodiment (see the waveform example of FIG. 3).

As described above, according to the second embodiment, the time from the assertion of the clock switching signal to the actual switching of the clock selection is 1 clock of the clock B at the maximum in the first embodiment. Even under such a condition, the clock is shortened by half in the present embodiment, and therefore, the maximum of clock B is 0.5 after the clock switching signal is asserted.
The effect is that it can be switched by the clock.

[Third Embodiment] Next, a third embodiment of the present invention will be described. FIG. 9 is a schematic block diagram showing a third embodiment of the PLL circuit of the present invention. This embodiment is a PLL circuit in the case where a plurality of clocks (clock A to clock n) are input and all the clocks can be used as a working or a standby.

In this embodiment, for example, when the clock B is the working reference clock, the other clocks can be the spare clocks. Which clock to switch to is determined by a clock switching signal from a clock selection unit (not shown).

The schematic configuration of the circuit of this embodiment is similar to that of the second embodiment, and the phase comparator 41, the low-pass filter 42, the VCXO 43, which constitutes the PLL circuit main section 46,
The frequency divider 44 is the same as that of the second embodiment, but the selector 40
And the function of the timing generator 25 is different. This embodiment is different from the second embodiment in that three or more clocks (clock A to clock n) are input to the selector 40, and each clock is also input to the timing generator 45. ing.

The timing generator 45 in FIG. 9 detects a change in the clock switching signal 56 and changes the clock selection signal 49 at the falling timing of the selected clock after the change (clock selected after switching). The reset signal 48 is asserted, or the clock selection signal 49 is changed and the load signal 47 is asserted at the rising timing of the selected clock after the change. Which operation is performed depends on when the clock switching signal changes, as will be described later.
It depends on the phase state of the clock selected after switching. Further, the selector 40 selects an input signal according to an instruction based on the clock selection signal 49 and outputs it as a reference clock.

FIG. 10 shows an operation waveform example of the third embodiment. In FIG. 10, the switching operation for arbitrary three clocks (clocks X, Y, and Z) of the clocks A to n will be described. According to FIG. 10, at the timing of T30, the clock selection signal selects the clock X, and the reference clock is the timing corresponding to the clock X. Further, the comparison clock also has the same phase as the reference clock (clock X). Next, when the clock switching signal switches from the clock X instruction to the clock Y instruction at the timing of T31, the clock Y is at the H level at this time point, and therefore, the next fall time point T of the clock Y.
Clock selection signal 49 is clock Y at the timing of 32.
And the reset signal is asserted. Since the frequency divider was reset at the timing of T32, the next T3
At the timing of 3, the rising edges of the reference clock (clock Y) and the comparison clock coincide.

Next, when the clock switching signal is switched from the clock Y to the clock Z at the timing of T34, since the clock Z is at the L level, the clock selection signal 4 is generated at the timing of the next rising time T35 of the clock Z.
9 switches to the clock Z, and the load signal is asserted. Since the frequency divider was loaded at the timing of T35,
At the next timing of T36, the rising edges of the reference clock (clock Z) and the comparison clock coincide.

In addition, even when switching from an arbitrary clock to another arbitrary clock is instructed by the clock switching signal, an operation similar to any one of the above-described operations is performed depending on the polarity of the clock selected after the switching. The phase of the reference clock after switching and the phase of the comparison clock match.

As described above, according to the third embodiment, the specific clock is not used as the working clock or the spare clock,
Regardless of which clock is selected from a plurality of clocks, there is no phase shift between the reference clock and the comparison clock, and the PLL can supply a stable clock.

Although not described here, a PLL circuit in the case where a plurality of clocks (clock A to clock n) are input to the timing generator and all the clocks can be used as a working or a standby is described in the first embodiment. In the same manner as described above, after the clock switching instruction, the configuration can be realized by only switching the clock selection signal after waiting for the next falling edge and resetting the frequency divider by the reset signal.

In the PLL circuit of the present invention, even if the reference clock is changed, there is no phase shift between the reference clock and the comparison clock even after the switching, and the PLL can supply a stable clock. Since the frequency divider that performs the phase adjustment by the load is one frequency divider for generating the comparison clock, it can be realized relatively easily.

[0049]

As described above, according to the present invention, the input clock as the reference clock signal is switched by the signal from the timing generator and the phase of the comparison clock output from the frequency divider is controlled. It is possible to realize a PLL circuit in which no phase shift occurs at the time of switching. In particular, compared with the conventional technique, since the frequency divider that performs the phase adjustment by the reset signal or the load signal is only one frequency divider for generating the comparison clock, there is a practical effect that it can be realized relatively easily. can get.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing a first embodiment of a PLL circuit of the present invention.

FIG. 2 is a timing chart (1) showing operation waveforms of respective parts in the PLL circuit of the first embodiment.

FIG. 3 is a timing chart (2) showing operation waveforms of respective parts in the PLL circuit of the first embodiment.

FIG. 4 is a timing chart (3) showing operation waveforms of respective parts in the PLL circuit of the first embodiment.

FIG. 5 is a timing chart (1) showing operation waveforms of respective parts in the PLL circuit of the first embodiment.

FIG. 6 is a schematic block diagram showing a second embodiment of the PLL circuit of the present invention.

FIG. 7 is a timing chart (1) showing operation waveforms of respective parts in the PLL circuit of the second embodiment.

FIG. 8 is a timing chart (2) showing operation waveforms of respective parts in the PLL circuit of the second embodiment.

FIG. 9 is a schematic block diagram showing a third embodiment of the PLL circuit of the present invention.

FIG. 10 is a timing chart showing operation waveforms of respective parts in the PLL circuit of the third embodiment.

FIG. 11 is a schematic block diagram of a conventional PLL circuit.

FIG. 12 is a timing chart showing waveforms at various parts in a conventional PLL circuit.

[Explanation of symbols]

1, 20, 40 ... Switching clock selector (selector) 2, 21, 41 ... Phase comparator 3, 22, 42 ... Filter 4, 23, 43 ... Voltage controlled oscillator (VCXO) 5, 24, 44 ... Divider 6, 25, 45 ... Timing generator 7, 26, 46 ... PLL circuit main part 8, 29, 49 ... Clock selection signal 9, 28, 48 ... Reset signal 10, 30, 50 ... Reference signal 11, 31, 51 ... Comparison signal 12, 32, 52 ... Output clock 13, 35, 56 ... Clock switching signal 14, 33, 53 ... Clock A 15, 34, 54 ... Clock B 27, 47 ... Load signal

Claims (5)

[Claims] 1. A PLL circuit including a clock selector for switching between a working clock signal and a spare clock signal to supply it as a reference clock, and a frequency divider for generating a comparison clock. A PLL circuit comprising a timing generator for switching to the spare clock by the clock selector and resetting the frequency divider at the fall timing of the spare clock when switching. 2. The timing generator switches to the spare clock by the clock selector at the first falling timing of the spare clock when the clock selection signal from the switching instruction means is input. The PLL circuit according to claim 1, wherein the frequency divider is reset. 3. A PLL circuit comprising a clock selector for switching between a working clock signal and a spare clock signal to supply it as a reference clock, and a frequency divider for generating a comparison clock. If the spare clock is H level at the time of switching, the clock selection is switched and the frequency divider is reset at the next fall timing of the spare clock. If the level is the level, at the next rising timing of the spare clock, the comparison clock is switched to the spare clock by the clock selector and the comparison clock becomes the beginning of the rise in the internal counter of the divider that generates the comparison clock. Load a value like
A PLL circuit comprising a timing generator. 4. A switching clock selector for selecting and switching a plurality of clock signals to supply as a reference clock, a switching instruction means, a frequency divider for generating a comparison clock, a clock switching signal from the switching instruction means, and A PLL circuit configured to include a timing generator that inputs each of the plurality of clock signals and outputs a clock selection signal to the switching clock selector, wherein the timing generation circuit switches from a working clock signal. When switching to another clock signal instructed by the means, switching to the instructed clock signal by the clock selector and resetting of the frequency divider are performed at the falling timing of the instructed clock signal. A PLL circuit characterized by the above. 5. A switching clock selector for selecting and switching a plurality of clock signals to supply as a reference clock, a switching instruction means, a frequency divider for generating a comparison clock, a clock switching signal from the switching instruction means, and A PLL circuit configured to include a timing generator that inputs each of the plurality of clock signals and outputs a clock selection signal to the switching clock selector, wherein the timing generation circuit switches from a working clock signal. When switching to another clock signal instructed by the means, if the instructed clock signal is at the H level, switching of clock selection and switching of the frequency divider are performed at the next falling timing of this clock signal. Reset, but if the specified clock signal is L
If the level is the level, at the rising timing of this clock signal, the comparison clock is switched to the clock signal instructed by the clock selector, and the internal counter of the frequency divider for generating the comparison clock starts the rising edge of the comparison clock. PL characterized by loading such values
L circuit.