JP2003229769A - Delta-sigma modulation type noise shaper circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make selectable a frequency band of a delta-sigma modulation type noise shaper circuit, as desired, which reduces quantization noise. <P>SOLUTION: The noise shaper circuit comprises an adder 101 for subtracting an output signal Y from an input signal X delayed by one sampling time through a delay circuit 104; an integrator 102, having a multiplier 105 for integrating output signals from the adder and multiplying the result by a factor R; a differentiator 106, having a multiplier 107 for differentiating the output signal from the adder 101 and multiplying the result by a factor C; an adder 108 for adding the output of the integrator to the output of the differentiator; and a quantizer 103 for quantizing the output thereof. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a delta sigma (Δ
Σ) Modulation type noise shaper circuit.

[0002]

2. Description of the Related Art The delta sigma (ΔΣ) modulation system is widely used in an analog / digital conversion circuit for digital audio as an extremely effective circuit having a noise shaping effect of moving quantization noise to a high frequency range. There is.

FIG. 7 is a block diagram showing the structure of a conventional ΔΣ modulation type noise shaper circuit. Further, FIG. 8 shows a distribution of quantization noise of the ΔΣ modulation type noise shaper circuit having the configuration of FIG. 7. In FIG. 7, 701 is an adder used for subtraction, 702 is an integrating circuit, 703 is a quantizer, and 704 is a delay circuit of 1 sample time.

The operation of this ΔΣ modulation type noise shaper circuit will be described with reference to FIG. 7. First, when the input signal X is given, the difference between the input signal X and the output signal Y delayed by one sample time is calculated in the adder 701, and this difference signal is input to the integrating circuit 702. The quantizer 703 quantizes the output of the integration circuit 702 and outputs it as an output signal Y. The output from this quantizer is input to the delay circuit 704 for use as an approximate signal at the next sample point.

Now, the z-transform of the input sample value series is X-transformed.
(Z), z-transform of the output sample value series is Y (z), quantum
Q (z) is the z-transform of the quantization noise by the digitizer 703.
Then, the transfer function of the integrating circuit 702 is 1 / (1-z^-1),
The transfer function of the delay circuit 704 is z ^-1Therefore, the time of FIG.
The following equation holds as the path equation. Y (z) = X (z) + (1-z^-1) Q (z)

Here, the amplitude frequency characteristic of (1-z ^-1 ) is (1-exp (-j) where z = exp (jωT).
ωT)), it can be seen that it has a characteristic of compressing low frequency components and raising high frequency components. When the order of the integrating circuit is quadratic, that is, when two integrating circuits are cascade-connected, the coefficient applied to the quantization noise is (1
Since -z ^-1 ) ² , the slope of the noise distribution becomes steep.
FIG. 8 shows a quantization noise distribution diagram when the order of the integrating circuit is first to third order.

[0007]

The conventional ΔΣ modulation type noise shaper circuit has two problems. Part 1
That is, the conventional amplitude frequency characteristic can only perform noise compression of low frequency components. The second is that the operation is stable until the order of the integrating circuit constituting the ΔΣ modulation type noise shaper circuit is up to the second order (that is, the number of circuits of the integrating circuit is up to two), but the order of the integrating circuit is higher than the third order. (Ie,
When the number of integrating circuits is 3 or more), the higher the level of the input signal, the easier the oscillation and the unstable operation.

The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a ΔΣ modulation circuit capable of arbitrarily selecting a frequency band capable of compressing quantization noise. A further object of the present invention is to provide a ΔΣ modulation circuit that can stably operate even if the order of the integrating circuit or the differentiating circuit is third or higher.

[0009]

In order to solve this problem, a ΔΣ modulation type noise shaper circuit according to a first aspect of the present invention subtracts an output signal delayed by one sample time from an input signal. An adding means (adder 101) and an integrating means (integrator circuit 102) having a first multiplying means (multiplier 105) for integrating the output of the first adding means and multiplying by a first coefficient (R); Differentiating means (differentiating circuit 106) having second multiplying means (multiplier 107) for differentiating the output of the first adding means and multiplying it by the second coefficient (C), and the output of the integrating means and the differentiating means. Second to add with the output of
Adder (adder 108), a quantizer (quantizer 103) for inputting and quantizing the output of the second adder and outputting an output signal, and delaying the output signal by one sample time. And delay means (delay circuit 104) for inputting to the first adding means.

According to the ΔΣ modulation type noise shaper circuit described in claim 1, the addition value of the integrating means for multiplying and outputting the first coefficient and the differentiating means for multiplying and outputting the second coefficient is used as the quantizing means. By inputting, by adjusting the first coefficient and the second coefficient, it is possible to arbitrarily select the band in which the quantization noise can be compressed.

A ΔΣ modulation type noise shaper circuit method according to a second aspect of the present invention is the ΔΣ modulation type noise shaper circuit according to the first aspect, further comprising third multiplication means for multiplying the third coefficient (1 / K). (Multiplier 309), the second
Instead of inputting the output of the adding means of (3) to the quantizing means, it is input to the third multiplying means and the output thereof is input to the quantizing means.

According to the ΔΣ modulation type noise shaper circuit of the second aspect, by providing the third multiplication means for multiplying the third coefficient, the ΔΣ modulation type noise shaper circuit of the first aspect is arbitrarily selected. In the band, the quantization noise in the band can be further compressed according to the third coefficient.

A ΔΣ modulation type noise shaper circuit according to a third aspect of the present invention is the ΔΣ modulation type noise shaper circuit according to the second aspect, further detects the level of the input signal, and outputs the level according to the detected level. Level detecting means for varying the coefficient of the third multiplying means (level detector 510)
And the integrating means includes at least three cascaded integrating means, and the differentiating means includes at least three cascaded differentiating means.

According to the ΔΣ modulation type noise shaper circuit of the third aspect, by varying the coefficient of the third multiplication means in accordance with the level of the input signal, the order of the integrating circuit is increased when the level of the input signal is high. When the input signal level is small, the characteristics can be made close to the characteristics when the order of the integrating circuit is high, so that the quantization noise in the band can be suppressed as much as possible, and Even if the order is the third order or higher, it is possible to control so as to operate stably without causing oscillation.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. (Embodiment 1) FIG. 1 shows Δ according to Embodiment 1 of the present invention.
It is a block diagram showing a configuration of a Σ modulation type noise shaper circuit. FIG. 2 shows the distribution of quantization noise of the ΔΣ modulation type noise shaper circuit having the configuration of FIG.

In FIG. 1, 101 is an adder used for subtraction, 102 is an integrating circuit, 103 is a quantizer, and 104.
Is a delay circuit of 1 sample time, 105 is an integrating circuit 102
At 106, a multiplier for multiplying the integral value by the coefficient R, 106 is a differentiating circuit, 107 is a multiplier for multiplying the differential value by the coefficient C at the differentiating circuit 106, and 108 is adding the output of the integrating circuit 102 and the output of the differentiating circuit 106. It is an adder circuit.

The operation of this ΔΣ modulation type noise shaper circuit will be described with reference to FIG. First, when the input signal X is given, the difference between the input signal X and the output signal Y delayed by one sample time is calculated in the adder 101, and this difference signal is input to the integrating circuit 102 and the differentiating circuit 106.
The integrating circuit 102 outputs a value obtained by multiplying the integrated value of the difference signal from the adder 101 by the coefficient R. The differentiating circuit 106 outputs a value obtained by multiplying the differential value of the difference signal from the adder 101 by the coefficient C.

The adder 108 adds the outputs of the integrating circuit 102 and the differentiating circuit 106 and outputs the result. Quantizer 103
Then, the output of the adder 108 is quantized and output. At this time, the output signal Y contains the quantization noise Q.
The output from this quantizer is input to the delay circuit 104 for use as an approximate signal at the next sample point.

Now, the z transformation of the input sample value series is X
(Z), the z-transform of the output sample value sequence is Y (z), and the z-transform of the quantization noise by the quantizer 103 is Q (z), the transfer function of the integrating circuit 102 is R / (1-z ^{− 1} ),
The transfer function of the differentiating circuit 106 is 1-Cz ^-1 , and the delay circuit 10 is
Since the transfer function of 4 is z ⁻¹ , the following equation holds as the circuit equation of FIG. 1. Y (z) = X (z) + {R / (1-z- ¹ ) + (1-Cz
^-1 )} Q (z)

Here, {R / (1-z ^-1 ) + (1-Cz
⁻¹ )} to investigate the amplitude frequency characteristic, if z ⁻¹ = exp (−jωT) = 1−jωT by first-order approximation,
The following expression is obtained as the amplitude frequency characteristic. R / (jωT) + (1-C) + jωTC

The outline of the amplitude frequency characteristic is approximately shown in FIG.
Shown in. Next, f1 and f2 are obtained from FIG. When simplified, the following equation holds. For f1, R / (ωT) = 1−C For f2, ωTC = 1−C

Since ω = 2πf, f1, f
The following equation is obtained as 2. f1 = R / (2πT (1-C)) f2 = (1-C) / (2πTC)

From the above equation, by changing the values of the coefficients R and C, the frequency band (the band of f1 to f2 shown in FIG. 2) in which the quantization noise Q is compressed approximately (1-C) times is selected. I see what I can do.

(Embodiment 2) FIG. 3 is a block diagram showing the configuration of a ΔΣ modulation type noise shaper circuit according to Embodiment 2 of the present invention. In addition, FIG. 4 shows Δ by the configuration of FIG.
The distribution of the quantization noise of the Σ modulation type noise shaper circuit is shown.

The second embodiment has a configuration in which a multiplier for multiplying the input of the quantizer by the third coefficient is inserted in the first embodiment. In FIG. 3, reference numerals 101 to 108 have the same functions as the blocks denoted by the same reference numerals in FIG. A multiplier 309 is inserted between the adder circuit 108 and the quantizer 103 and multiplies the output of the adder circuit 108 by the coefficient 1 / K.

The operation of this ΔΣ modulation type noise shaper circuit will be described with reference to FIG. Similar to the first embodiment,
First, when the input signal X is given, the difference between the input signal X and the output signal Y delayed by one sample time is calculated in the adder 101, and this difference signal is input to the integrating circuit 102 and the differentiating circuit 106. In the integrating circuit 102, the adder 1
A value obtained by multiplying the integrated value of the difference signal from 01 by the coefficient R is output. The differentiating circuit 106 outputs a value obtained by multiplying the differential value of the difference signal from the adder 101 by the coefficient C.

The adder 108 adds the outputs of the integrating circuit 102 and the differentiating circuit 106 and outputs the result. This output is multiplied by the coefficient 1 / K by the multiplier 309, and the quantizer 103 quantizes and outputs the output of the multiplier 309. The output from this quantizer is input to the delay circuit 104 for use as an approximate signal at the next sample point.

Now, the z transformation of the input sample value series is X
(Z), the z-transform of the output sample value sequence is Y (z), and the z-transform of the quantization noise by the quantizer 103 is Q (z), the transfer function of the integrating circuit 102 is R / (1-z ^{− 1} ),
The transfer function of the differentiating circuit 106 is 1-Cz ^-1 , and the delay circuit 10 is
Since the transfer function of 4 is z ⁻¹ , the following equation holds as the circuit equation of FIG. Y (z) = X (z) + (1 / K) {R / (1-z- ¹ ) +
(1-Cz ^-1 )} Q (z)

Here, as in the first embodiment, {R
The following expression is obtained as the amplitude frequency characteristic of / (1-z ^-1 ) + (1-Cz ^-1 )}. (1 / K) {R / (jωT) + (1-C) + jωTC}

From the above equation, the quantization noise Q in the band selected by the coefficients R and C becomes (1-C) / K times, and by changing the value of the coefficient K, as shown in FIG. It can be seen that the quantization noise in the selected band (f1 to f2) can be compressed more.

(Third Embodiment) FIG. 5 is a block diagram showing the structure of a ΔΣ modulation type noise shaper circuit according to a third embodiment of the present invention. In addition, FIG. 6 shows Δ by the configuration of FIG.
The distribution of the quantization noise of the Σ modulation type noise shaper circuit is shown.

In the third embodiment, when the order of the integrating circuit or the differentiating circuit constituting the ΔΣ modulation type noise shaper circuit is the third order or more, the higher the level of the input signal, the easier the oscillation and the unstable operation. As a measure against that,
In the second embodiment, a level detector for detecting the level of the input signal is provided, and the third multiplier 1 according to the detection level is provided.
The configuration of varying the coefficient of / K is adopted.

In FIG. 5, an adder 101 and a quantizer 1
03, the delay circuit 104, and the multiplier 108 have the same functions as the blocks denoted by the same reference numerals in FIGS. 1 and 3. Reference numeral 502 denotes a third-order integration circuit, which outputs a value obtained by multiplying the third-order integration value of the difference signal from the adder 101 by a coefficient R. A third-order differentiation circuit 506 outputs a value obtained by multiplying the differential value of the difference signal from the adder 101 by a coefficient C.

Further, reference numeral 510 is a level detector for detecting the level of the input signal, and 509 is a multiplier for multiplying the output of the adder circuit 108 by the coefficient 1 / K as in 309 of FIG. It has a function of varying the coefficient 1 / K according to the detection level of the input signal by the detector 510.

The operation of this ΔΣ modulation type noise shaper circuit will be described with reference to FIG. Although the noise shaping effect is enhanced by setting the order of the integrating circuit and the differentiating circuit to the third order, the coefficient 1 / K depends on the detection level of the input signal.
Since the operation other than changing the value is the same as that of the second embodiment, the description thereof will be omitted.

In the level detector 510, the adder 10
If one of the output signals of 1 and the output signal of the adder 108 is detected to have a relatively high signal level, oscillation is likely to occur, so the coefficient K of the multiplier 509 is set to K.
Change to make the value smaller. As a result, the distribution of the quantization noise in the case of the third order or higher approaches the characteristic when the order of the integrating circuit 502 or the differentiating circuit 506 is less than the third order,
It will not oscillate and the operation will be stable.

On the contrary, when the level detector 510 detects that the level of the signal is a relatively small value, it is difficult to oscillate, so that the coefficient K of the multiplier 509 is changed to be large. As a result, the distribution of the quantization noise approaches the characteristics when the order of the integrating circuit 502 or the differentiating circuit 506 is third or higher, and the quantization noise can be further compressed as shown in FIG.

[0038]

As described above, according to the present invention,
By adjusting the multiplication coefficient R of the integrator and the multiplication coefficient C of the differentiator, the excellent effect that the band in which the quantization noise can be compressed can be arbitrarily selected is obtained.

Furthermore, according to the present invention, by adjusting the coefficient 1 / K of the multiplier inserted before the quantizer,
In the arbitrarily selected band, the excellent effect that the quantization noise in the band can be further compressed according to the coefficient 1 / K is obtained.

Further, according to the present invention, by varying the coefficient 1 / K of the multiplier inserted in the preceding stage of the quantizer in accordance with the level of the input signal, the order of the integrating circuit is increased when the level of the input signal is high. When the input signal level is low, the characteristics can be made close to the characteristics when the order of the integrating circuit is high, so that the quantization noise in the band can be suppressed as much as possible, and Even if the order is the third order or higher, it is possible to obtain an excellent effect that it can be controlled so as to operate stably without causing oscillation.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a delta-sigma modulation type noise shaper circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a distribution of quantization noise in the delta-sigma modulation noise shaper circuit according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a delta-sigma modulation type noise shaper circuit according to a second embodiment of the present invention.

FIG. 4 is a diagram showing the distribution of quantization noise in the delta-sigma modulation noise shaper circuit according to the second embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a delta-sigma modulation noise shaper circuit according to a third embodiment of the present invention.

FIG. 6 is a diagram showing the distribution of quantization noise in the delta-sigma modulation noise shaper circuit according to the third embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a conventional delta-sigma modulation type noise shaper circuit.

FIG. 8 is a diagram showing a distribution of quantization noise of a conventional delta-sigma modulation type noise shaper circuit.

[Explanation of symbols]

101, 108, 701 adder 102, 702 integrating circuit 103,703 Quantizer 104, 704 delay circuit 105, 107, 309, 509 multiplier 106 Differentiation circuit 502 Third integration circuit 506 3rd order differentiation circuit 510 level detector

Claims (3)

[Claims] 1. A first adding means for subtracting an output signal delayed by one sample time from an input signal, and a first multiplying means for integrating an output of the first adding means and multiplying by a first coefficient. An integrating means; a differentiating means having a second multiplying means for differentiating the output of the first adding means and multiplying it by a second coefficient; and a second adding means for adding the output of the integrating means and the output of the differentiating means. An adder; a quantizer for quantizing the output of the second adder and quantizing the output signal; and a delayer for delaying the output signal by one sample time and inputting it to the first adder. And a delta-sigma modulation type noise shaper circuit. 2. A third multiplication means for multiplying a third coefficient is provided, and instead of inputting the output of the second adding means to the quantizing means, the output of the second adding means is changed to the first output. 3. The delta-sigma modulation type noise shaper circuit according to claim 1, wherein the output of the third multiplication means is input to the quantization means. 3. A level detecting means for detecting the level of the input signal and varying a coefficient of the third multiplying means in accordance with the detected level, wherein the integrating means integrates at least three cascaded integrals. 3. The delta-sigma modulation type noise shaper circuit according to claim 2, wherein said differentiating means performs differentiation by at least three cascaded differentiating means.