JP2003224234A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JP2003224234A
JP2003224234A JP2002019537A JP2002019537A JP2003224234A JP 2003224234 A JP2003224234 A JP 2003224234A JP 2002019537 A JP2002019537 A JP 2002019537A JP 2002019537 A JP2002019537 A JP 2002019537A JP 2003224234 A JP2003224234 A JP 2003224234A
Authority
JP
Japan
Prior art keywords
semiconductor element
metal plate
bonding wire
semiconductor
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002019537A
Other languages
Japanese (ja)
Other versions
JP3904934B2 (en
Inventor
Satoshi Miura
聡 三浦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
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Filing date
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Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2002019537A priority Critical patent/JP3904934B2/en
Publication of JP2003224234A publication Critical patent/JP2003224234A/en
Application granted granted Critical
Publication of JP3904934B2 publication Critical patent/JP3904934B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32153Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/32175Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H01L2224/32188Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic the layer connector connecting to a bonding area protruding from the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
    • HELECTRICITY
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • HELECTRICITY
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
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    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

Abstract

<P>PROBLEM TO BE SOLVED: To provide a resin-sealed semiconductor device which is capable of increasing the number of I/Os of an insulating board where a semiconductor element that is improved in heat dissipation properties and mounted through a wire bonding method, can be reduced in thickness and size, and improved in reliability. <P>SOLUTION: A semiconductor device is equipped with a first bonding wire 4 connected between an electrode provided on the periphery of the top surface of a semiconductor element 3 and an electrode pad around a semiconductor element 3 on the top surface of an insulating board 2, a sealing resin layer 6 covering the semiconductor element 3 and the first bonding wire 4, and a metal plate 7 which is arranged over the semiconductor element 3 and provided with an underside that is buried in the upper part of the sealing resin layer 6 and an exposed top surface. The metal plate 7 is equipped with a projection which is located at the center of the underside of the plate 7 and provided with an underside that is adjacent and opposite to the center of the top surface of the semiconductor element 3, and the underside of an overhang of the metal plate 7 is higher than the apex of the first bonding wire 4 and supported by a plurality of second bonding wires 5 which are nearly as high as the first bonding wire 4 and connected to the electrode and/or the electrode pad. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】 【0001】 【発明の属する技術分野】本発明は、放熱用の金属板を
備えているとともに高集積化された半導体素子を搭載し
た樹脂封止型の半導体装置に関する。 【0002】 【従来の技術】近年、IC,LSI等の半導体素子を搭
載する半導体装置は、半導体素子が高集積化してきてい
ることから更なる高密度実装化および小型化が要求され
てきている。また、半導体素子の高集積化に伴ってその
作動中の発熱量が増大してきている。例えば、光通信や
マイクロ波通信、ミリ波通信等の分野で用いられる高周
波信号で作動する半導体素子、MPU(Micro Processi
ng Unit)に代表される高速演算処理をおこなう半導体
素子、および高電流のスイッチングを行なうパワー半導
体素子等では、作動時の発熱量が極めて大きくなってい
る。その結果、半導体素子が正常に作動する温度範囲の
上限である約100℃を超えて温度が上昇するという問題
点があった。 【0003】また、半導体素子とそれを搭載する絶縁基
板との熱膨張差により、半導体素子の接合部に生じる応
力によってその接合部が剥離したり、絶縁基板に亀裂が
発生し、半導体装置の信頼性を維持できなくなるという
問題点もあった。特に高周波信号で作動する半導体素子
の中には、シリコンを素材としたものだけでなく、Ga
As,InP等を素材とした化合物半導体も多く、これ
らの半導体素子は、一般にシリコンを素材とした半導体
素子と比較してI/O数(Input/Output数:入出力端
子数)が少なく、半導体素子の大きさも小さくなり、従
って局部的な熱応力によるストレスが発生しやすい。そ
のため、半導体装置の放熱性を向上させて、半導体素子
の熱を効率良く放熱して冷却する必要があった。 【0004】そこで、放熱特性の向上を図った半導体装
置として、熱伝導性の良好な各種放熱板を設けたものが
知られている。例えば、図4に示す半導体装置401で
は、半導体素子403が金属板407の下面に搭載されてお
り、半導体素子403が絶縁基板402の貫通孔に挿置される
ようにして、金属板407の下面で半導体素子403の周囲が
絶縁基板402の上面に接着されている。半導体素子403は
ボンディングワイヤ404によって絶縁基板402の電極に電
気的に接続されている。また、半導体素子403は、封止
樹脂406によって覆われ保護されている。絶縁基板402の
下面には、外部電気回路基板等に接続するための金属端
子(導体バンプ)408が形成されている。この半導体装
置401では、搭載された半導体素子403の熱は、金属板40
7を通じて半導体素子403の裏面(図4では上面)より直
接外部に放熱され冷却される。 【0005】また、図5に示す半導体装置501では、半
導体素子503が絶縁基板502上に搭載されるとともにボン
ディングワイヤ504によってリード端子508と電気的に接
続されている。また、半導体素子503を保護するために
封止樹脂506によってモールド封止されている。半導体
素子503の上方の封止樹脂506の上面には窪みが設けら
れ、その窪みに金属板507が接着されている。半導体素
子503の熱は金属板507の露出面から外部に放熱され冷却
される。 【0006】これら従来の半導体装置401,501では、い
ずれも金属板407,507が放熱板として機能し、熱抵抗の
低減に有効な構造となっている。 【0007】 【発明が解決しようとする課題】しかしながら、図4の
半導体装置401においては、絶縁基板402の下面の封止樹
脂406が存在する領域には金属端子408を設けることがで
きない。現在、半導体素子の高集積化に伴いI/O数は
増加してきている。また、実装面積を小さくしたいとい
う要求から半導体素子収納用パッケージ(以下、半導体
パッケージともいう)も小さくなる傾向がある。即ち、
小型の絶縁基板402の下面になるべく多くの金属端子408
を設けようとすれば、絶縁基板402の下面全面に金属端
子408を設けることが望ましいが、半導体装置401では、
絶縁基板402の下面全面に金属端子408を設けることがで
きない。そのため、I/O数を増加させることができな
い。また、I/O数を増加させると半導体パッケージも
大きくなる。その結果、半導体装置401自体も大型化さ
れて、小型化の要求を満足できないという問題点があっ
た。 【0008】また、図5の半導体装置501においては、
その製造時に、半導体素子503を搭載した絶縁基板502と
リード端子508の一端部を樹脂封止するために、封止空
間を形成した金型で絶縁基板502とリード端子508を固定
し型締めし、封止樹脂を注入して樹脂封止している。そ
のため、金型とボンディングワイヤ504との間隙が狭く
なると封止樹脂を均一に充填することが困難となった
り、製造後にボンディングワイヤ504が露出したりする
恐れがあった。その他、金型とボンディングワイヤ504
との間隙が狭いことから、注入される封止樹脂の流速が
早くなり、ボンディングワイヤ504が倒れて互いに接触
し短絡するといった問題点があった。その結果、半導体
素子503に入出力される高周波信号を正確に伝達できな
かったり、半導体素子503と金属板507とを十分に近づけ
ることができず、満足できる放熱効果が得られないとい
う問題点があった。 【0009】従って、本発明は上記問題点を解決すべく
完成されたものであり、その目的は、既存のボンディン
グワイヤを用いて半導体素子をワイヤボンディング実装
しながら絶縁基板のI/O数を増加させることができ、
薄型化かつ小型化が可能であり、また半導体素子の放熱
性に優れた高い信頼性を有する樹脂封止型の半導体装置
を提供することにある。 【0010】 【課題を解決するための手段】本発明の半導体装置は、
絶縁基板の上側主面に搭載された半導体素子と、該半導
体素子の上面の外周部に形成された電極および前記上側
主面の前記半導体素子の周囲に形成された電極パッドを
電気的に接続した第1のボンディングワイヤと、前記半
導体素子および前記第1のボンディングワイヤを覆うよ
うに設けられた封止樹脂層と、前記半導体素子の上方に
配置されるとともに下面が前記封止樹脂層の上部に埋め
込まれ上面が露出している金属板とを具備しており、前
記金属板は、その下面の中央部に前記半導体素子の上面
の中央部に近接して対向する下面を有する凸部が形成さ
れているとともに、下面の外周部が前記第1のボンディ
ングワイヤよりも最高位置が高くかつ略同じ高さを有す
るとともに前記電極および/または前記電極パッドに接
続された複数の第2のボンディングワイヤで支持されて
いることを特徴とする。 【0011】本発明は、半導体素子の上方に配置される
とともに下面が封止樹脂層の上部に埋め込まれ上面が露
出している金属板が、第1のボンディングワイヤよりも
高くかつ略同じ高さを有する複数の第2のボンディング
ワイヤで支持されていることから、金属板が第1のボン
ディングワイヤと接触して短絡せず、また金属板を半導
体素子の極めて近くに配置することができる。その結
果、既存のボンディングワイヤを用いて半導体素子をワ
イヤボンディング実装しながらも、半導体素子のワイヤ
ボンディング面(上面)から半導体素子の熱を金属板を
介して外部に効率的に放散して冷却することができる。
半導体素子の熱は、半導体素子の上面に近接している金
属板の下面の凸部を通じて拡散するため、高い放熱効率
が得られる。従って、半導体素子が熱によって特性が劣
化せず、半導体素子に入出力される高周波信号を正確に
伝達でき、高い信頼性が得られる。 【0012】また、金属板の下面を第2のボンディング
ワイヤで支持した構成であることから、半導体装置をき
わめて薄型化することができる。 【0013】また、金属板の下面の中央部に凸部を有し
ているため、半導体素子および第1のボンディングワイ
ヤを覆って液状の封止樹脂層を設けた後に封止樹脂層の
上部に金属板を自重で沈降させたり押し込む際に、凸部
の側面に沿って樹脂が流れていくため、凸部周囲への樹
脂の流れが均等になり、金属板のずれを小さくして精度
良く配置することができる。従って、GaAs,InP
等の化合物半導体素子のように小さい半導体素子に対し
て極めて有効である。 【0014】さらに、半導体素子が搭載された絶縁基板
の下面の全面に金属端子を設けることができ、その結果
I/O数を増加させることができるとともに、金属端子
を設けるために絶縁基板の下面の面積を増大させる必要
がないため半導体装置を小型化することができる。 【0015】 【発明の実施の形態】本発明の半導体装置について以下
に詳細に説明する。図1は、本発明の半導体装置につい
て実施の形態の一例を示す断面図である。図1におい
て、1は、絶縁基板2、半導体素子3、第1のボンディ
ングワイヤ4、第2のボンディングワイヤ5、封止樹脂
層6、金属板7および金属端子8から成る半導体装置で
ある。 【0016】本発明の半導体装置1は、絶縁基板2の上
側主面に搭載された半導体素子3と、半導体素子3の上
面の外周部に形成された電極および上側主面の半導体素
子3の周囲に形成された電極パッドを電気的に接続した
第1のボンディングワイヤ4と、半導体素子3および第
1のボンディングワイヤ4を覆うように設けられた封止
樹脂層6と、半導体素子3の上方に配置されるとともに
下面が封止樹脂層6の上部に埋め込まれ上面が露出して
いる金属板7とを具備しており、金属板7は、その下面
の中央部に半導体素子3の上面の中央部に近接して対向
する下面を有する凸部が形成されているとともに、下面
の外周部が第1のボンディングワイヤ4よりも最高位置
が高くかつ略同じ高さを有するとともに電極および/ま
たは電極パッドに接続された複数の第2のボンディング
ワイヤ5で支持されている。 【0017】金属板7の下面の凸部は、その外周端が半
導体素子3上面の第1のボンディングワイヤ4が接続さ
れる電極よりも半導体素子3上面の中央部側にあるよう
に設けられる。即ち、凸部の下面は、半導体素子3の上
面の中央部(電極が設けられた外周部よりも中央側の領
域)と同程度の面積を有する。そして、金属板7の下面
に上記のような凸部があるので、半導体素子3および第
1のボンディングワイヤ4を覆って液状の封止樹脂層6
を設けた後に封止樹脂層6の上部に金属板7を自重で沈
降させたり押し込む際に、凸部の側面に沿って樹脂が流
れていくため、樹脂の周囲への流れが均等になり、金属
板7をずれを小さくして精度良く配置することができ
る。そのため、金属板7は、第1のボンディングワイヤ
4および第2のボンディングワイヤ5に接触することは
ない。 【0018】凸部の側面に沿った樹脂の流れを良好にす
るために、金属板7下面の凸部は、球面状、逆円錐形状
等の下に凸の曲面形状、逆四角錐等の逆多角錐形状など
の形状、即ち凸部の下面の中心部が突出した形状である
ことが好ましい。具体的には、金属板7下面の凸部の形
状は、凸部側面の金属板7下面に対する角度が0.03°〜
90°である多角柱形状、または金属板7下面の中心部を
頂点とする半球形状であることが好ましい。この場合、
凸部の面に沿って樹脂が速やかに流れていくため、金属
板7を封止樹脂層6上部内に設置する際の樹脂の流れが
さらに均等になり、金属板7をさらに精度良く配置する
ことができる。上記角度が0.03°未満では、均一な樹脂
の流れを形成することが困難となる。また角度が90°を
超える場合、樹脂の流れが阻害されてしまうため、金属
板7の封止樹脂層6中での位置が不安定になり易い。よ
り好ましくは、この角度は3〜60°がよい。 【0019】また、金属板7下面から金属板7上面に達
する貫通孔を形成すると、液状の樹脂が凸部の側面に流
れるとともにその貫通孔内を上方に流れていくため、凸
部の下面に空気溜りができるのを防ぐとともに金属板7
の封止樹脂層6上部への沈降が促進されてその設置を速
やかに行なうことができ、また金属板7の位置ずれがさ
らに小さくなる。 【0020】金属板7下面の中央部の凸部は、金属板7
下面の外周部からの突出長さ(高さ)は0.1mm〜0.6m
mが好ましい。0.1mm未満では、金属板7を精度良く
載置させるのが困難になり、0.6mmを超えると、第2
のボンディングワイヤ5のループ高さの調整が困難にな
る。 【0021】また、金属板7下面の中央部の凸部は、半
導体素子3の上面の中央部に近接して対向する下面を有
しているが、凸部の下面と半導体素子3の上面の中央部
との間隔は500μm以下が好ましい。500μmを超える
と、金属板7を保持する第2のボンディングワイヤ5の
高さが500μmよりもかなり大きくなるため、第2のボ
ンディングワイヤ5にねじれ等が発生して高さの制御が
難しくなる。また、半導体素子3の熱を金属板7を介し
て放熱する際の放熱効率が低下し易くなる。さらに、凸
部の下面が半導体素子3の上面の中央部に接しているこ
と(間隔が0μm)がより好ましく、放熱効率が最も高
くなる。ただし、半導体素子3の表面は一般にパッシベ
ーション膜で保護されているので、凸部の下面が半導体
素子3の上面の中央部に接していても問題ないが、パッ
シベーション膜がない半導体素子3の場合は凸部の下面
が半導体素子3の上面の中央部に接していない方がよ
い。 【0022】金属板7の下面の凸部以外の部分(外周
部)は、第1のボンディングワイヤ4よりも最高位置が
高くかつ略同じ高さを有する複数の第2のボンディング
ワイヤ5で支持されている。従って、金属板7は、下面
が封止樹脂層6の上部に埋設され上面が露出していると
ともに、第1のボンディングワイヤ4に接触せずに第2
のボンディングワイヤ5の頂部で下面の外周部が支持さ
れている。 【0023】本発明の絶縁基板2は、アルミナ(Al2
3)セラミックス、窒化アルミニウム(AlN)セラ
ミックス、炭化珪素(SiC)セラミックス、ガラスセ
ラミックス等のセラミックス、または鉄(Fe)−ニッ
ケル(Ni)−コバルト(Co)合金、Fe−Ni合
金、Al、銅(Cu)等の金属から成る。特に、軽量で
安価である点でセラミックスが好ましい。 【0024】本発明の半導体装置1は放熱性に優れてい
るため、半導体素子4として、光通信、マイクロ波通信
またはミリ波通信等の分野で用いられる高周波信号で作
動する半導体素子、MPU等の高速演算処理を行なう半
導体素子、または高電流のスイッチングを行なうパワー
半導体素子等の作動中の発熱量が極めて大きいものに対
して有効である。 【0025】また本発明の半導体装置1は、ワイヤボン
ディングによる実装であるため、ほとんどの半導体素子
に適応でき、フリップチップ実装ができない半導体素子
へも適応可能である。即ち、フリップチップ実装では一
般に錫(Sn)−鉛(Pb)合金半田を用いて実装して
おり、実装の際に230℃以上の温度を加えてSn−Pb
合金半田を溶融し冷却して接続を行うが、InPを主成
分とする半導体素子3の中には230℃程度の温度に耐え
られないものがあるのに対して、ワイヤボンディングに
よる実装では何ら問題は無い。 【0026】本発明の第1のボンディングワイヤ4は、
半導体素子3の上面の電極と絶縁基板2の上側主面の電
極パッドとを電気的に接続するようにボンディングされ
ている。そして、複数の第2のボンディングワイヤ5
は、それらの最高位置が第1のボンディングワイヤ4よ
り高くなっているとともに、略同じ高さとなるようにワ
イヤリングされている。これにより、第2のボンディン
グワイヤ5は、金属板7を第1のボンディングワイヤ4
に接触させることなく、金属板7を半導体素子3に可能
な限り近づけて支持する支持体として機能する。 【0027】なお、第2のボンディングワイヤ5は、半
導体素子3の上面の電極と絶縁基板2の上側主面の電極
パッドとを接続するもの(図1)、または絶縁基板2の
上側主面の異なる電極パッド同士を接続するもの(図
2)、さらには半導体素子3の上面の異なる電極同士を
接続するものであってもよい。 【0028】第2のボンディングワイヤ5が半導体素子
3の上面の電極に接続される場合、第2のボンディング
ワイヤ5が接続される電極は、接続されても半導体素子
3の性能に影響を及ぼすことのないものであることが良
い。また、第2のボンディングワイヤ5が接続される電
極を、例えばグランドを取るための電極(接地電極)と
してもよく、その場合金属板7を通じて電気的なグラン
ドを取ることが可能になる。 【0029】本発明では、金属板7の上面が半導体素子
3の上面に略平行になるようにして金属板7を支持して
放熱を均一に行なうためには、3本以上の第2のボンデ
ィングワイヤ5を設けるのがよい。また、第2のボンデ
ィングワイヤ5を4本以上設ける場合であっても3本の
第2のボンディングワイヤ5が金属板7に接触していれ
ばよい。勿論第2のボンディングワイヤ5の全てが金属
板7に接触していてもよい。また、第2のボンディング
ワイヤ5は、金属板7の下面の中心に関する角度間隔が
略同じであるのがよく、金属板7を安定的に支持でき
る。例えば、3本の場合、第2のボンディングワイヤ5
の金属板7下面の中心に関する角度間隔は約120°がよ
い。なお、第2のボンディングワイヤ5の本数は多すぎ
ても本数に比例して支持機能が向上するものではないた
め、コスト面からも10本程度以下が好ましい。 【0030】さらに、第2のボンディングワイヤ5が奇
数本の場合、金属板7に対して略等間隔に配置すること
が好ましい。また偶数本の場合、金属板7に対して略等
間隔に配置するか、または2本づつ互いに対向するよう
に配置することが好ましい。 【0031】このように、第2のボンディングワイヤ5
を配置して金属板7を支持することにより、封止樹脂層
6で半導体素子3を保護する際にも、金属板7を安定的
にかつ半導体素子3に略平行にして、さらに第1のボン
ディングワイヤ4と金属板7とを接触させずに信頼性良
く支持することが可能となる。 【0032】また、第1のボンディングワイヤ4と第2
のボンディングワイヤ5との最高位置(頂部)の高さの
差は、熱抵抗の低い金属板7が可能な限り半導体素子3
の近くに配置されるとともに、第1のボンディングワイ
ヤ4と金属板7とが短絡しないように配置されるように
することが必要である。従って、半導体素子3の良好な
放熱性、金属板7との短絡防止および半導体装置1の薄
型化、小型化の点から、第1のボンディングワイヤ4と
第2のボンディングワイヤ5との最高位置の高さの差は
50〜100μm程度であることが好ましい。50μm未満で
は、第1のボンディングワイヤ4が金属板7と短絡し易
くなる。100μm未満を超えると、半導体素子3の放熱
性が低下するとともに半導体装置1が厚くなり易い。 【0033】本発明の第1,第2のボンディングワイヤ
4,5としては、電気伝導率が良くかつボンディング結
合が可能なものを使用する。例えば、その直径が15〜10
0μmの線状のボンディングワイヤ、または厚さが10〜5
0μmで幅が100〜500μmのリボン状のボンディングワ
イヤが好ましい。 【0034】線状のボンディングワイヤの場合、直径が
15μm未満では、ボンディングする際にワイヤが蛇行し
易く、最高位置の高さを制御して金属板7を第1のボン
ディングワイヤ4に短絡させずに支持するのが困難にな
る。直径が100μmを超えると、ボンディングする際に
ボンディングワイヤを簡単に切断することが困難とな
り、作業性に問題がある。リボン状のものの場合、厚さ
が10μm未満または幅が100μm未満では、ボンディン
グワイヤとして腰(強度)が弱くなり金属板7を第1の
ボンディングワイヤ4に短絡させずに支持することが困
難となる。厚さが50μmを超えるかまたは幅が500μm
を超えると、ボンディングする際にボンディングワイヤ
を簡単に切断することが困難となり、作業性に問題があ
る。 【0035】本発明の第1,第2のボンディングワイヤ
4,5としては、半導体素子3の電極および絶縁基板2
の電極パッドも小型化されてきていることから、ファイ
ンピッチボンディングに対応するために、その線径は25
〜32μmがより好ましい。また、第1,第2のボンディ
ングワイヤ4,5の材質としてはAl,Au,Cu等の
電気伝導率の良いものが好ましい。 【0036】本発明の封止樹脂層6は、アクリル系樹
脂、エポキシ系樹脂、シリコーン系樹脂、ポリエーテル
アミン系樹脂等から成る。これらの樹脂が、第2のボン
ディングワイヤ5の最高位置よりも高くなるような厚み
に、プリント法、ポッティング法等により塗布されるこ
とによって、封止樹脂層6が形成される。これらの樹脂
は、半導体素子3および第1,第2のボンディングワイ
ヤ4,5を覆って設けるための作業性の点で、塗布時に
は液状であることが好ましい。勿論塗布後に熱硬化また
は紫外線硬化させる。 【0037】本発明においては、金属板7の下面に凸部
が形成されているため、半導体素子3と第2のボンディ
ングワイヤ5に支持された金属板7との間に介在する熱
伝導率の低い封止樹脂層6の厚さを極めて薄くすること
ができ、封止樹脂層6による熱抵抗を小さくすることが
できる。また、熱伝導性の良い金属板7を、その下面を
封止樹脂層6中に埋設して発熱する半導体素子3に極力
近づけて配置できることから、半導体素子3と金属板7
との間の熱抵抗を効果的に低減させることができる。 【0038】本発明の金属板7は、Al,Cu,Au,
Ag,Pt,Zn,Fe,Mo,Ti,W,Ni,P
d,ステンレススチール,真鍮,Fe−Ni−Co合
金,Fe−Ni合金等から成り、放熱性、加工性、軽
量、低コストの点でAl,Cuが好ましい。この金属板
7は封止樹脂層6の硬化前に封止樹脂層6の上面に載置
されるのがよい。封止樹脂層6が硬化する前であれば、
金属板7は自重によって半導体素子3に近づくように封
止樹脂層6中に沈降することができる。そして、第2の
ボンディングワイヤ5の最高位置の高さが第1のボンデ
ィングワイヤ4の最高位置よりも高くなっているため、
第2のボンディングワイヤ5の最高位置よりも金属板7
が半導体素子3に近づくことはない。また、金属板7が
第1のボンディングワイヤ4と短絡して、高周波信号の
伝送特性を劣化させたり電気的な接地(グランド)を乱
すことはないため、半導体素子3に入出力する高周波信
号の伝送特性が良好に維持される。 【0039】また金属板7の外形寸法は、半導体素子3
の上面に対する角度が45°以下である伝熱経路で放熱さ
れる半導体素子3の熱が金属板7の下面にほとんど到達
することが効果的な放熱の点でよいことから、半導体素
子3の外形寸法より大きく絶縁基板2の外形寸法以下で
あるのが好ましい。金属板7の冷却能力および金属板7
の封止樹脂層6との密着力を考慮すると、上記の通り、
半導体素子3の上方にその上面に対する角度が45°以下
で放散される熱のほとんどが到達する範囲内に、金属板
7を設けることがよい。なお、本発明の金属板7は、放
熱板としての機能に加えて、半導体素子3の電磁的なシ
ールド板として用いることもできる。 【0040】 【実施例】本発明の半導体装置の実施例について以下に
説明する。 【0041】図1の半導体装置1を以下のように構成し
た。縦12mm×横12mm×厚さ0.5mmの外形寸法のア
ルミナセラミックスから成る正方形の絶縁基板2を用
い、その上側主面の中央部に、縦7.5mm×横7.5mm×
厚さ0.3mmの外形寸法であり高周波信号で作動する正
方形の半導体素子3をエポキシ樹脂で接着して搭載し
た。次に、絶縁基板2の上側主面で半導体素子3の周囲
に設けられた電極パッドと、半導体素子3の上面の外周
部の電極とを、第1のボンディングワイヤ4で電気的に
接続した。次に、半導体素子3の上面の四隅に設けら
れ、半導体素子3の機能に影響を及ぼさない電極と、絶
縁基板2の上側主面の電極パッドとを、絶縁基板2上面
の中心に対して120°の等角度間隔で3本の第2のボン
ディングワイヤ5で結線した。 【0042】第1,第2のボンディングワイヤ4,5
は、いずれも25μmの直径を有する金(Au)線とし
た。第1のボンディングワイヤ4の最高位置の高さは半
導体素子3の上面から0.15mmであり、また第2のボン
ディングワイヤ5の最高位置の高さは、第1のボンディ
ングワイヤ4の最高位置よりも0.1mm高くなるように
半導体素子3の上面から0.25mmの高さに設定した。 【0043】その後、封止樹脂層6形成用のエポキシ樹
脂から成る液状の樹脂をプリント法によって、半導体素
子3および第1,第2のボンディングワイヤ4,5が覆
われるように、厚さ0.75mmで塗布した。封止樹脂層6
を硬化させる前に、外形寸法が縦9mm×横9mm×厚
さ0.5mmの正方形であり、下面の中央部に縦6mm×
横6mm×高さ0.3mm、側面の下面に対する角度が90
°である凸部を有するAlから成る金属板7を、絶縁基
板2上面の中心と金属板7下面の中心とが重なるように
位置合わせして封止樹脂層6の上面に載置した。この工
程は、半導体素子3を絶縁基板2に搭載する設備、例え
ばロボットアーム等を有する実装機などと同じ設備を用
いて行うことができる。 【0044】その後、30分間放置して金属板7を封止樹
脂層6上部に所定位置まで沈降させた後、封止樹脂層6
をキュアして硬化させ、半導体素子3の上方にその上面
から約0.25mmの距離に金属板7の凸部が位置するよう
に埋設された半導体装置1(サンプルA)を作製した。 【0045】また、比較例として、金属板7を有してい
ないこと以外は上記実施例の半導体装置1と同様の構成
の半導体装置(サンプルB)と、下面に凸部を有してい
ない金属板(平板)を具備する以外は上記実施例の半導
体装置1と同様の構成の半導体装置(サンプルC)を作
製した。 【0046】そして、サンプルA〜Cにそれぞれ通電し
て半導体素子3を駆動させたところ、半導体素子3はい
ずれも駆動時に3Wの熱を発熱した。サンプルA〜Cの
放熱性を比較するため、半導体素子3の駆動時に、サン
プルAの外表面に露出した金属板7上面の中央部の温度
と、サンプルBの封止樹脂層6上面の中央部の温度と、
サンプルCの外表面に露出した金属板7上面の中央部の
温度をそれぞれ測定した。その結果、サンプルAでは露
出した金属板7上面の中央部の表面温度が38℃であった
のに対して、サンプルBの封止樹脂層6上面の中央部の
表面温度は76℃であり、またサンプルCの金属板7中央
部の表面温度は57℃であった。サンプルAは、サンプル
Bに対して38℃もの放熱性の改善が認められ、サンプル
Cに対して19℃の改善が認められた。 【0047】また、金属板7の配置の精度は、金属板7
下面の中心と半導体素子3上面の中心とのずれについて
測定したところ、サンプルAはサンプルCに対して60%
の改善が認められた。 【0048】なお、本発明は上記実施の形態および実施
例に限定されず、本発明の要旨を逸脱しない範囲内で種
々の変更を施すことは何ら差し支えない。例えば、図2
に示すように、第2のボンディングワイヤ5をボンディ
ングする際に半導体素子3上面の電極が選択できない場
合、第2のボンディングワイヤ5を絶縁基板2の上側主
面の電極パッド間で接続しても良い。また、金属板7は
図1,図2に示すように上面が完全な平板状でなくても
よく、図3に示すように、金属板7の上面に凹凸を設け
て表面積を大きくし、より放熱効果のある形状としても
良い。 【0049】 【発明の効果】本発明の半導体装置は、絶縁基板の上側
主面に搭載された半導体素子と、半導体素子の上面の外
周部に形成された電極および上側主面の半導体素子の周
囲に形成された電極パッドを電気的に接続した第1のボ
ンディングワイヤと、半導体素子および第1のボンディ
ングワイヤを覆うように設けられた封止樹脂層と、半導
体素子の上方に配置されるとともに下面が封止樹脂層の
上部に埋め込まれ上面が露出している金属板とを具備
し、金属板は、その下面の中央部に半導体素子の上面の
中央部に近接して対向する下面を有する凸部が形成され
ているとともに、下面の外周部が第1のボンディングワ
イヤよりも最高位置が高くかつ略同じ高さを有するとと
もに電極および/または電極パッドに接続された複数の
第2のボンディングワイヤで支持されていることによ
り、金属板が第1のボンディングワイヤと接触して短絡
せず、また金属板を半導体素子の極めて近くに配置する
ことができる。その結果、既存のボンディングワイヤを
用いて半導体素子をワイヤボンディング実装しながら
も、半導体素子のワイヤボンディング面(上面)から半
導体素子の熱を金属板を介して外部に効率的に放散して
冷却することができる。半導体素子の熱は、半導体素子
の上面に近接している金属板の下面の凸部を通じて拡散
するため、高い放熱効率が得られる。従って、半導体素
子が熱によって特性が劣化せず、半導体素子に入出力さ
れる高周波信号を正確に伝達でき、高い信頼性が得られ
る。 【0050】また、金属板の下面を第2のボンディング
ワイヤで支持した構成であることから、半導体装置をき
わめて薄型化することができる。 【0051】また、金属板の下面の中央部に凸部を有し
ているため、半導体素子および第1のボンディングワイ
ヤを覆って液状の封止樹脂層を設けた後に封止樹脂層の
上部に金属板を自重で沈降させたり押し込む際に、凸部
の側面に沿って樹脂が流れていくため、凸部周囲への樹
脂の流れが均等になり、金属板をずれを小さくして精度
良く配置することができる。従って、GaAs,InP
等の化合物半導体素子のように小さい半導体素子に対し
て極めて有効である。 【0052】さらに、半導体素子が搭載された絶縁基板
の下面の全面に金属端子を設けることができ、その結果
I/O数を増加させることができるとともに、金属端子
を設けるために絶縁基板の下面の面積を増大させる必要
がないため半導体装置を小型化することができる。
DETAILED DESCRIPTION OF THE INVENTION [0001] The present invention relates to a metal plate for heat radiation.
Equipped with highly integrated semiconductor elements
And a resin-sealed semiconductor device. [0002] 2. Description of the Related Art In recent years, semiconductor devices such as ICs and LSIs have been mounted.
In the semiconductor devices to be mounted, semiconductor elements have become highly integrated.
Requires higher density mounting and smaller size.
Is coming. Also, with the increasing integration of semiconductor devices,
The amount of heat generated during operation is increasing. For example, optical communication
High frequency used in fields such as microwave communication and millimeter wave communication
The semiconductor device that operates by the wave signal, MPU (Micro Processi
ng Unit) semiconductors that perform high-speed arithmetic processing
Element and power semiconductor for high current switching
In the case of body elements, the amount of heat generated during operation is extremely large.
You. As a result, the temperature range in which the semiconductor device operates normally
The problem that the temperature rises above the upper limit of about 100 ° C
There was a point. Also, a semiconductor device and an insulating substrate for mounting the same are provided.
Due to the difference in thermal expansion between the plate and the
The joints peel off due to force or cracks in the insulating substrate
Occurs and the reliability of the semiconductor device cannot be maintained.
There were also problems. In particular, semiconductor devices that operate with high-frequency signals
Among them, not only those made of silicon but also Ga
There are many compound semiconductors made of As, InP, etc.
These semiconductor elements are generally made of silicon
Number of I / Os compared to elements (Inputs / Outputs: input / output end
The number of semiconductor elements) and the size of the semiconductor element
Therefore, stress due to local thermal stress is likely to occur. So
Therefore, the heat dissipation of the semiconductor device is improved, and the semiconductor element is
It was necessary to efficiently radiate the heat and cool it. [0004] Therefore, semiconductor devices with improved heat radiation characteristics have been developed.
Is provided with various heat sinks with good thermal conductivity.
Are known. For example, in the semiconductor device 401 shown in FIG.
The semiconductor element 403 is mounted on the lower surface of the metal plate 407.
The semiconductor element 403 is inserted into the through hole of the insulating substrate 402
Thus, the periphery of the semiconductor element 403 on the lower surface of the metal plate 407 is
It is bonded to the upper surface of the insulating substrate 402. Semiconductor element 403
The electrodes of the insulating substrate 402 are electrically connected by the bonding wires 404.
It is pneumatically connected. The semiconductor element 403 is sealed
It is covered and protected by resin 406. Of the insulating substrate 402
On the underside, metal ends for connecting to external electric circuit boards, etc.
A child (conductor bump) 408 is formed. This semiconductor device
In the device 401, the heat of the mounted semiconductor element 403 is
7 through the back of the semiconductor element 403 (the top in FIG. 4).
Heat is radiated to the outside and cooled. In the semiconductor device 501 shown in FIG.
The conductive element 503 is mounted on the insulating substrate 502 and
Electrical connection with the lead terminal 508 by the
Has been continued. Also, in order to protect the semiconductor element 503,
It is molded and sealed by a sealing resin 506. semiconductor
A recess is provided on the upper surface of the sealing resin 506 above the element 503.
The metal plate 507 is bonded to the depression. Semiconductor element
The heat of the child 503 is radiated to the outside from the exposed surface of the metal plate 507 and cooled.
Is done. In these conventional semiconductor devices 401 and 501,
The metal plates 407 and 507 also function as heat sinks,
The structure is effective for reduction. [0007] However, FIG.
In the semiconductor device 401, the sealing tree on the lower surface of the insulating substrate 402
A metal terminal 408 can be provided in the area where the grease 406 exists.
I can't. At present, the number of I / Os is increasing due to higher integration of semiconductor devices.
It is increasing. Also, if you want to reduce the mounting area
Package for semiconductor device storage (hereinafter referred to as semiconductor
Package) also tends to be smaller. That is,
As many metal terminals 408 as possible on the underside of the small insulating substrate 402
If a metal end is to be provided,
Although it is desirable to provide a child 408, in the semiconductor device 401,
Metal terminals 408 can be provided on the entire lower surface of the insulating substrate 402.
I can't. Therefore, the number of I / Os cannot be increased.
No. Also, as the number of I / Os increases, semiconductor packages also
growing. As a result, the semiconductor device 401 itself becomes larger.
And the demand for miniaturization cannot be satisfied.
Was. In the semiconductor device 501 shown in FIG.
At the time of its manufacture, an insulating substrate 502 on which a semiconductor element 503 is mounted
To seal one end of the lead terminal 508 with resin,
The insulating substrate 502 and the lead terminals 508 are fixed with a mold with a gap between them.
Then, the resin is sealed by injecting a sealing resin. So
Therefore, the gap between the die and the bonding wire 504 is narrow.
It became difficult to uniformly fill the sealing resin
Or the bonding wire 504 is exposed after manufacturing
There was fear. Other molds and bonding wires 504
Is small, the flow rate of the injected sealing resin is
Faster, bonding wire 504 falls down and touches each other
And a short circuit occurs. As a result, semiconductor
The high frequency signal input / output to / from the element 503 cannot be transmitted accurately.
Or close the semiconductor element 503 and the metal plate 507
Not be able to obtain a satisfactory heat dissipation effect.
There was a problem. Accordingly, the present invention has been made to solve the above problems.
It is completed and its purpose is to
Wire bonding mounting of semiconductor elements using wire
While increasing the number of I / Os on the insulating substrate,
Thin and compact, and heat dissipation of semiconductor elements
-Encapsulated semiconductor device with excellent reliability and high reliability
Is to provide. [0010] According to the present invention, there is provided a semiconductor device comprising:
A semiconductor element mounted on an upper main surface of an insulating substrate;
Electrodes formed on the outer peripheral portion of the upper surface of the body element and the upper side
An electrode pad formed around the semiconductor element on the main surface;
An electrically connected first bonding wire;
The conductor element and the first bonding wire are covered.
And a sealing resin layer provided above the semiconductor element.
And the lower surface is buried in the upper part of the sealing resin layer.
And a metal plate having an exposed upper surface.
The metal plate has an upper surface of the semiconductor element at the center of the lower surface.
A convex portion having a lower surface that is close to and opposed to the center of the projection is formed.
And the outer periphery of the lower surface is
Higher than and approximately the same height as
Contact with the electrode and / or the electrode pad
Supported by a plurality of continuous second bonding wires
It is characterized by having. The present invention is arranged above a semiconductor element.
At the same time, the lower surface is embedded in the upper part of the sealing resin layer, and the upper surface is exposed.
The protruding metal plate is larger than the first bonding wire
A plurality of second bondings having a high height and substantially the same height
Since the metal plate is supported by the wire,
No short circuit due to contact with the grounding wire and semiconductive metal plate
It can be located very close to the body element. The result
As a result, the semiconductor element is warped using existing bonding wires.
While using ear bonding
Heat of the semiconductor element is transferred from the bonding surface (top surface) to the metal plate.
It can be efficiently radiated to the outside and cooled.
The heat of the semiconductor element is
High heat dissipation efficiency due to diffusion through the convex part on the lower surface of the metal plate
Is obtained. Therefore, the characteristics of the semiconductor element deteriorate due to heat.
High-frequency signals input to and output from semiconductor elements
Communication is possible, and high reliability is obtained. Further, the lower surface of the metal plate is subjected to a second bonding.
Because the device is supported by wires,
It can be made thinner. Further, the metal plate has a convex portion at the center on the lower surface.
The semiconductor element and the first bonding wire.
After providing a liquid sealing resin layer covering the
When the metal plate is settled or pushed into the upper part by its own weight,
The resin flows along the side of the
The flow of grease is even, minimizing the displacement of the metal plate
Can be arranged well. Therefore, GaAs, InP
For small semiconductor devices such as compound semiconductor devices such as
It is extremely effective. Furthermore, an insulating substrate on which a semiconductor element is mounted
Metal terminals can be provided on the entire lower surface of the
The number of I / Os can be increased and metal terminals
Need to increase the area of the lower surface of the insulating substrate to provide
Since there is no semiconductor device, the size of the semiconductor device can be reduced. [0015] DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to the present invention will be described below.
This will be described in detail. FIG. 1 shows a semiconductor device of the present invention.
1 is a cross-sectional view illustrating an example of an embodiment. Figure 1
1 is an insulating substrate 2, a semiconductor element 3, a first bonder.
Wire 4, second bonding wire 5, sealing resin
A semiconductor device comprising a layer 6, a metal plate 7 and a metal terminal 8;
is there. The semiconductor device 1 according to the present invention is provided on an insulating substrate 2.
The semiconductor element 3 mounted on the side main surface and the semiconductor element 3
Formed on the outer periphery of the surface and the semiconductor element on the upper main surface
The electrode pads formed around the element 3 were electrically connected.
The first bonding wire 4, the semiconductor element 3 and the
Seal provided to cover one bonding wire 4
The resin layer 6 and the semiconductor element 3
The lower surface is embedded in the upper portion of the sealing resin layer 6 and the upper surface is exposed.
Metal plate 7, and the lower surface of the metal plate 7
Facing the central part of the upper surface of the semiconductor element 3
A convex portion having a lower surface is formed.
Is at the highest position than the first bonding wire 4
And the electrodes and / or
Or a plurality of second bondings connected to the electrode pads
It is supported by wires 5. The convex portion on the lower surface of the metal plate 7 has an outer peripheral end that is half.
The first bonding wire 4 on the upper surface of the conductor element 3 is connected.
To the center of the upper surface of the semiconductor element 3 with respect to the electrode to be
Is provided. That is, the lower surface of the projection is located above the semiconductor element 3.
The center of the surface (the area closer to the center than the outer
Area). And the lower surface of the metal plate 7
Has the above-mentioned convex portions, so that the semiconductor element 3 and the
A liquid sealing resin layer 6 covering the bonding wire 4
Is provided, the metal plate 7 is set on the sealing resin layer 6 by its own weight.
When lowering or pushing in, the resin flows along the side of the protrusion.
The flow around the resin becomes even,
The plate 7 can be arranged with high accuracy by minimizing the displacement.
You. Therefore, the metal plate 7 is connected to the first bonding wire.
Contacting the fourth and second bonding wires 5
Absent. The flow of the resin along the side surface of the projection is improved.
The convex part on the lower surface of the metal plate 7 has a spherical shape and an inverted conical shape.
Curved surface, convex polygonal shape such as inverted quadrangular pyramid, etc.
, That is, a shape in which the center of the lower surface of the convex portion protrudes.
Is preferred. Specifically, the shape of the protrusion on the lower surface of the metal plate 7
The shape is such that the angle of the side surface of the convex portion to the lower surface of the metal plate 7 is 0.03 ° or more.
90 ° polygonal column shape or the center of the lower surface of metal plate 7
It is preferable that the shape is a hemispherical shape having a vertex. in this case,
Since the resin flows quickly along the surface of the convex, the metal
When the plate 7 is installed in the upper portion of the sealing resin layer 6, the flow of resin is
It becomes even more, and the metal plate 7 is more accurately arranged.
be able to. If the above angle is less than 0.03 °, uniform resin
It becomes difficult to form the flow of the flow. The angle is 90 °
If it exceeds, the flow of resin will be hindered,
The position of the plate 7 in the sealing resin layer 6 tends to be unstable. Yo
More preferably, this angle is 3-60 degrees. Further, the lower surface of the metal plate 7 reaches the upper surface of the metal plate 7.
When a through hole is formed, the liquid resin flows to the side surface of the projection.
As well as upward through the through-hole,
The air plate is prevented from forming on the lower surface of the part and the metal plate 7
Settling on the upper portion of the sealing resin layer 6 is accelerated, and
This can be done quickly and the metal plate 7
It becomes even smaller. The central convex portion on the lower surface of the metal plate 7 is
The protruding length (height) of the lower surface from the outer periphery is 0.1 mm to 0.6 m
m is preferred. If it is less than 0.1 mm, the metal plate 7 can be precisely
It becomes difficult to place it.
Adjustment of the loop height of the bonding wire 5 becomes difficult.
You. The central convex part on the lower surface of the metal plate 7 is
The lower surface of the conductive element 3 has a lower surface that is close to and opposed to the center of the upper surface.
But the center of the lower surface of the convex portion and the upper surface of the semiconductor element 3
Is preferably 500 μm or less. Over 500μm
Of the second bonding wire 5 holding the metal plate 7
Since the height is much larger than 500 μm, the second
The twisting etc. occurs in the binding wire 5 and the height can be controlled.
It becomes difficult. Further, heat of the semiconductor element 3 is transferred through the metal plate 7.
The heat radiation efficiency when radiating the heat is likely to decrease. Furthermore, convex
That the lower surface of the part is in contact with the center of the upper surface of the semiconductor element 3.
(The interval is 0 μm) is more preferable, and the heat radiation efficiency is the highest.
It becomes. However, the surface of the semiconductor element 3 is generally passive.
The lower surface of the projection is semiconductor
Although there is no problem if it is in contact with the center of the upper surface of the element 3,
In the case of the semiconductor element 3 having no passivation film, the lower surface of the convex portion
Is not in contact with the center of the upper surface of the semiconductor element 3.
No. A portion other than the convex portion on the lower surface of the metal plate 7 (the outer periphery)
Part) has the highest position than the first bonding wire 4.
A plurality of second bondings having a high height and substantially the same height
It is supported by wires 5. Therefore, the metal plate 7 is
Is embedded in the upper portion of the sealing resin layer 6 and the upper surface is exposed.
In both cases, the second bonding wire 4
The outer periphery of the lower surface is supported by the top of the bonding wire 5 of FIG.
Have been. The insulating substrate 2 of the present invention is made of alumina (Al)Two
OThree) Ceramics, aluminum nitride (AlN) ceramic
Mix, silicon carbide (SiC) ceramics, glass
Ceramics such as Lamix or iron (Fe) -Ni
Kel (Ni) -Cobalt (Co) alloy, Fe-Ni alloy
It is made of a metal such as gold, Al, and copper (Cu). In particular, lightweight
Ceramics are preferred because they are inexpensive. The semiconductor device 1 of the present invention has excellent heat dissipation.
Optical communication, microwave communication
Or, it can be made with high-frequency signals used in fields such as millimeter wave communication.
Semiconductor devices, semi-conductors that perform high-speed arithmetic processing such as MPU
Conductive element or power for high current switching
For extremely large heat generation during operation of semiconductor devices, etc.
It is effective. Also, the semiconductor device 1 of the present invention
Almost all semiconductor devices
Semiconductor device that cannot be flip-chip mounted
Is also applicable. That is, in flip chip mounting,
Generally, it is mounted using a tin (Sn) -lead (Pb) alloy solder.
When mounting, a temperature of 230 ° C or higher is applied to make Sn-Pb
The connection is made by melting and cooling the alloy solder.
Some of the semiconductor elements 3 withstand temperatures of about 230 ° C
Can not be used for wire bonding
There is no problem with this implementation. The first bonding wire 4 of the present invention comprises:
The electrodes on the upper surface of the semiconductor element 3 and the upper main surface of the insulating substrate 2
Bonded to make electrical connection with the pole pad
ing. Then, the plurality of second bonding wires 5
Indicate that their highest position is the first bonding wire 4.
As well as at the same height.
Earrings have been. As a result, the second bondin
The wire 5 is formed by connecting the metal plate 7 to the first bonding wire 4.
Metal plate 7 can be used as semiconductor element 3 without contact
It functions as a support that supports as close as possible. Note that the second bonding wire 5 is
Electrode on upper surface of conductive element 3 and electrode on upper main surface of insulating substrate 2
To connect to the pad (FIG. 1)
Connects different electrode pads on the upper main surface (Figure
2) Further, different electrodes on the upper surface of the semiconductor element 3 are connected to each other.
It may be connected. The second bonding wire 5 is a semiconductor element
3 if it is connected to the electrode on the top
The electrode to which the wire 5 is connected is a semiconductor element even if it is connected.
It is good that it does not affect the performance of 3
No. In addition, the voltage to which the second bonding wire 5 is connected is
The pole is connected to, for example, an electrode for grounding (ground electrode).
In such a case, an electric ground
Can be taken. In the present invention, the upper surface of the metal plate 7 is a semiconductor element.
3 and support the metal plate 7 so as to be substantially parallel to the upper surface.
For uniform heat radiation, three or more second
It is preferable to provide a wiring wire 5. Also, the second bond
Even if four or more wirings 5 are provided, three
If the second bonding wire 5 is in contact with the metal plate 7
Just fine. Of course, all of the second bonding wires 5 are made of metal.
It may be in contact with the plate 7. Also, the second bonding
The wire 5 has an angular interval with respect to the center of the lower surface of the metal plate 7.
It is preferable that they are substantially the same, so that the metal plate 7 can be stably supported.
You. For example, in the case of three, the second bonding wire 5
The angle interval about the center of the lower surface of the metal plate 7 should be about 120 °.
No. The number of the second bonding wires 5 is too large.
However, the support function did not improve in proportion to the number
Therefore, from the viewpoint of cost, the number is preferably about 10 or less. Furthermore, the second bonding wire 5 is odd.
In the case of several pieces, they should be arranged at substantially equal intervals with respect to the metal plate 7.
Is preferred. In the case of an even number, approximately
Place them at intervals or face each other two at a time
It is preferable to arrange them. As described above, the second bonding wire 5
Is disposed to support the metal plate 7 so that the sealing resin layer
6, the metal plate 7 can be stably
And substantially parallel to the semiconductor element 3,
Good reliability without contact between the wiring wire 4 and the metal plate 7
It is possible to support well. The first bonding wire 4 and the second bonding wire 4
Of the highest position (top) with the bonding wire 5
The difference is that the metal plate 7 having a low thermal resistance
And the first bonding wire
So that the wire 4 and the metal plate 7 are not short-circuited.
It is necessary to. Therefore, the semiconductor device 3
Heat dissipation, prevention of short circuit with metal plate 7 and thinness of semiconductor device 1
From the viewpoint of miniaturization and miniaturization, the first bonding wire 4 and
The difference in height between the second bonding wire 5 and the highest position is
It is preferably about 50 to 100 μm. Less than 50μm
Means that the first bonding wire 4 is easily short-circuited to the metal plate 7
It becomes. If the thickness exceeds 100 μm, heat radiation of the semiconductor element 3
In addition, the semiconductor device 1 is likely to be thicker while the performance is reduced. First and second bonding wires of the present invention
4 and 5 have good electric conductivity and bonding
Use something that can be combined. For example, its diameter is 15-10
0μm linear bonding wire or 10 ~ 5 thickness
0-μm ribbon-shaped bonding wire with a width of 100-500 μm
Ears are preferred. In the case of a linear bonding wire, the diameter is
If it is less than 15 μm, the wire will meander during bonding.
It is easy to control the height of the highest position
It is difficult to support the shorting wire 4 without causing a short circuit.
You. When the diameter exceeds 100 μm,
It is difficult to cut the bonding wire easily.
Problem with workability. For ribbons, thickness
Is less than 10 μm or less than 100 μm in width.
The waist (strength) is weakened as a wire, and the metal plate 7
Difficult to support without shorting to bonding wire 4
It will be difficult. Thickness over 50μm or width 500μm
Exceeds the bonding wire when bonding
Is difficult to cut easily, and there is a problem with workability.
You. First and second bonding wires of the present invention
4 and 5, the electrodes of the semiconductor element 3 and the insulating substrate 2
Since the electrode pads of
The wire diameter is 25 to support single-pitch bonding.
~ 32 µm is more preferred. Also, the first and second bondies
The materials of the wiring wires 4 and 5 include Al, Au, Cu and the like.
Those having good electric conductivity are preferable. The sealing resin layer 6 of the present invention is made of an acrylic resin.
Fat, epoxy resin, silicone resin, polyether
It is made of an amine resin or the like. These resins are
Thickness that is higher than the highest position of the ding wire 5
Is applied by printing, potting, etc.
Thus, the sealing resin layer 6 is formed. These resins
Are the semiconductor element 3 and the first and second bonding wires.
In terms of workability for covering and providing the yarns 4 and 5,
Is preferably liquid. Of course, after application
Is UV cured. In the present invention, a convex portion is formed on the lower surface of the metal plate 7.
Is formed, the semiconductor element 3 and the second bond
Between the metal plate 7 and the metal wire 7
Extremely thin sealing resin layer 6 having low conductivity
And the thermal resistance by the sealing resin layer 6 can be reduced.
it can. In addition, a metal plate 7 having good heat conductivity is
As much as possible to the semiconductor element 3 buried in the sealing resin layer 6 and generating heat
The semiconductor element 3 and the metal plate 7 can be arranged close to each other.
Can be effectively reduced. The metal plate 7 of the present invention is made of Al, Cu, Au,
Ag, Pt, Zn, Fe, Mo, Ti, W, Ni, P
d, stainless steel, brass, Fe-Ni-Co alloy
Made of gold, Fe-Ni alloy, etc.
Al and Cu are preferred from the viewpoints of quantity and low cost. This metal plate
7 is placed on the upper surface of the sealing resin layer 6 before the sealing resin layer 6 is cured.
Good to be. Before the sealing resin layer 6 is cured,
The metal plate 7 is sealed by its own weight so as to approach the semiconductor element 3.
It can settle in the resin stopper layer 6. And the second
The height of the highest position of the bonding wire 5 is the first bond.
Because it is higher than the highest position of the
The metal plate 7 is higher than the highest position of the second bonding wire 5.
Does not approach the semiconductor element 3. Also, the metal plate 7
Short-circuits with the first bonding wire 4 to transmit a high-frequency signal.
Deterioration of transmission characteristics or disturbance of electrical grounding (ground)
High-frequency signals input to and output from the semiconductor element 3
The transmission characteristics of the signal are well maintained. The external dimensions of the metal plate 7 are
Heat is dissipated in the heat transfer path whose angle with respect to the
Heat of the semiconductor element 3 almost reaches the lower surface of the metal plate 7
Is effective in terms of effective heat dissipation.
When the outer dimensions of the insulating board 2 are larger than the outer dimensions of the
Preferably it is. Cooling capacity of metal plate 7 and metal plate 7
Considering the adhesive force of the sealing resin layer 6 with
The angle with respect to the upper surface of the semiconductor element 3 is 45 ° or less.
Metal plate within the range where most of the heat dissipated by
7 is preferably provided. In addition, the metal plate 7 of the present invention
In addition to the function as a hot plate, the electromagnetic
It can also be used as a cold plate. [0040] DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the semiconductor device of the present invention will be described below.
explain. The semiconductor device 1 of FIG. 1 is configured as follows.
Was. External dimensions of 12 mm (length) × 12 mm (width) × 0.5 mm (thickness)
For square insulating substrate 2 made of lumina ceramics
In the center of the upper main surface, 7.5 mm long x 7.5 mm wide x
0.3mm thick outer dimensions and positive operated by high frequency signal
A rectangular semiconductor element 3 is mounted by bonding with epoxy resin.
Was. Next, the periphery of the semiconductor element 3 on the upper main surface of the insulating substrate 2
And the outer periphery of the upper surface of the semiconductor element 3
Part of the electrode and the first bonding wire 4 electrically
Connected. Next, four corners of the upper surface of the semiconductor element 3 are provided.
Electrodes that do not affect the function of the semiconductor element 3
The electrode pad on the upper main surface of the edge substrate 2 is connected to the upper surface of the insulating substrate 2
Three second holes at equal angular intervals of 120 ° to the center of the
Ding wire 5 was connected. First and second bonding wires 4 and 5
Are gold (Au) wires each having a diameter of 25 μm.
Was. The height of the highest position of the first bonding wire 4 is half
0.15 mm from the upper surface of the conductive element 3
The height of the highest position of the ding wire 5 is the first bondy.
So that it is 0.1 mm higher than the highest position of
The height was set to 0.25 mm from the upper surface of the semiconductor element 3. Thereafter, an epoxy resin for forming the sealing resin layer 6 is formed.
Liquid resin consisting of oil is printed on the semiconductor
The child 3 and the first and second bonding wires 4 and 5 are covered.
It was applied at a thickness of 0.75 mm so as to be covered. Sealing resin layer 6
Before curing, the external dimensions are 9 mm long x 9 mm wide x thickness
0.5mm square, 6mm long at the center of the lower surface
6mm wide x 0.3mm high, 90 degrees to the bottom of the side
°, a metal plate 7 made of Al having a convex portion
The center of the upper surface of the plate 2 and the center of the lower surface of the metal plate 7
It was positioned and placed on the upper surface of the sealing resin layer 6. This work
In the process, equipment for mounting the semiconductor element 3 on the insulating substrate 2, for example,
Use the same equipment as a mounting machine with a robot arm, etc.
Can be done. Thereafter, the metal plate 7 is left standing for 30 minutes to seal the metal plate.
After settling to a predetermined position on the upper portion of the resin layer 6, the sealing resin layer 6
Is cured and cured, and its upper surface is placed above the semiconductor element 3.
So that the convex part of the metal plate 7 is located at a distance of about 0.25 mm from
A semiconductor device 1 (sample A) embedded in the semiconductor device was manufactured. As a comparative example, a metal plate 7 was provided.
The same configuration as the semiconductor device 1 of the above embodiment except that there is no
Semiconductor device (sample B) and a convex portion on the lower surface.
Except that it has no metal plate (flat plate).
A semiconductor device (sample C) having the same configuration as the body device 1 is manufactured.
Made. Then, a current is applied to each of the samples A to C.
When the semiconductor element 3 was driven by the
The displacement also generated 3 W of heat during driving. Samples A to C
In order to compare the heat radiation, when driving the semiconductor element 3,
Temperature at the center of the upper surface of the metal plate 7 exposed on the outer surface of the pull A
And the temperature at the center of the upper surface of the sealing resin layer 6 of the sample B,
The center of the upper surface of the metal plate 7 exposed on the outer surface of the sample C
The temperature was measured in each case. As a result, sample A
The surface temperature at the center of the upper surface of the metal plate 7 was 38 ° C.
On the other hand, in the center part of the upper surface of the sealing resin layer 6 of the sample B,
The surface temperature is 76 ° C and the center of the metal plate 7 of sample C
The surface temperature of the part was 57 ° C. Sample A is a sample
38 ° C improvement in heat dissipation compared to B
An improvement of 19 ° C. was observed for C. The accuracy of the placement of the metal plate 7
Displacement between the center of the lower surface and the center of the upper surface of semiconductor element 3
When measured, sample A was 60% of sample C
Improvement was observed. The present invention is not limited to the above-described embodiment and embodiment.
The present invention is not limited to the examples, and may be any seeds without departing from the gist of the present invention.
Making any changes is fine. For example, FIG.
As shown in FIG.
When the electrode on the upper surface of the semiconductor element 3 cannot be selected during
In this case, the second bonding wire 5 is
It may be connected between the electrode pads on the surface. Also, the metal plate 7
As shown in FIGS. 1 and 2, even if the upper surface is not completely flat
Well, as shown in FIG. 3, unevenness is provided on the upper surface of the metal plate 7.
To increase the surface area and achieve a shape with a more effective heat dissipation
good. [0049] According to the present invention, the semiconductor device is provided on the upper side of the insulating substrate.
The semiconductor element mounted on the main surface and outside the upper surface of the semiconductor element
The electrodes formed on the periphery and the periphery of the semiconductor element on the upper main surface
A first button electrically connected to the electrode pads formed in the surrounding area.
Semiconductor element and first bonder
A sealing resin layer provided to cover the
And the lower surface of the sealing resin layer
A metal plate that is embedded in the upper part and has an exposed upper surface.
The metal plate is located on the upper surface of the semiconductor element in the center of the lower surface.
A convex portion having a lower surface facing and close to the central portion is formed.
And the outer peripheral portion of the lower surface is the first bonding wire.
If the highest position is higher than the ear and it is about the same height
Multiple electrodes connected to electrodes and / or electrode pads
Being supported by the second bonding wire.
The metal plate contacts the first bonding wire and short-circuits
No, and place the metal plate very close to the semiconductor device
be able to. As a result, existing bonding wires
While mounting the semiconductor element by wire bonding
Is also halfway from the wire bonding surface (upper surface) of the semiconductor element.
Efficiently dissipates the heat of the conductive element to the outside via the metal plate
Can be cooled. The heat of the semiconductor element is
Diffuses through the protrusions on the lower surface of the metal plate close to the upper surface of the
Therefore, high heat dissipation efficiency can be obtained. Therefore, the semiconductor element
The characteristics of the element do not deteriorate due to heat,
High-frequency signals can be transmitted accurately, and high reliability can be obtained.
You. The lower surface of the metal plate is subjected to a second bonding.
Because the device is supported by wires,
It can be made thinner. Further, the metal plate has a convex portion at the center on the lower surface.
The semiconductor element and the first bonding wire.
After providing a liquid sealing resin layer covering the
When the metal plate is settled or pushed into the upper part by its own weight,
The resin flows along the side of the
The flow of grease is even and the accuracy of the metal plate is reduced
Can be arranged well. Therefore, GaAs, InP
For small semiconductor devices such as compound semiconductor devices such as
It is extremely effective. Further, an insulating substrate on which a semiconductor element is mounted
Metal terminals can be provided on the entire lower surface of the
The number of I / Os can be increased and metal terminals
Need to increase the area of the lower surface of the insulating substrate to provide
Since there is no semiconductor device, the size of the semiconductor device can be reduced.

【図面の簡単な説明】 【図1】本発明の半導体装置について実施の形態の一例
を示す断面図である。 【図2】本発明の半導体装置について実施の形態の他の
例を示す断面図である。 【図3】本発明の半導体装置について実施の形態の他の
例を示す断面図である。 【図4】従来の半導体装置の断面図である。 【図5】従来の半導体装置の他の例を示す断面図であ
る。 【符号の説明】 1:半導体装置 2:絶縁基板 3:半導体素子 4:第1のボンディングワイヤ 5:第2のボンディングワイヤ 6:封止樹脂層 7:金属板
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view illustrating an example of an embodiment of a semiconductor device of the present invention. FIG. 2 is a cross-sectional view showing another example of the embodiment of the semiconductor device of the present invention. FIG. 3 is a sectional view showing another example of the embodiment of the semiconductor device of the present invention; FIG. 4 is a cross-sectional view of a conventional semiconductor device. FIG. 5 is a sectional view showing another example of a conventional semiconductor device. [Description of Signs] 1: Semiconductor device 2: Insulating substrate 3: Semiconductor element 4: First bonding wire 5: Second bonding wire 6: Sealing resin layer 7: Metal plate

Claims (1)

【特許請求の範囲】 【請求項1】 絶縁基板の上側主面に搭載された半導体
素子と、該半導体素子の上面の外周部に形成された電極
および前記上側主面の前記半導体素子の周囲に形成され
た電極パッドを電気的に接続した第1のボンディングワ
イヤと、前記半導体素子および前記第1のボンディング
ワイヤを覆うように設けられた封止樹脂層と、前記半導
体素子の上方に配置されるとともに下面が前記封止樹脂
層の上部に埋め込まれ上面が露出している金属板とを具
備しており、前記金属板は、その下面の中央部に前記半
導体素子の上面の中央部に近接して対向する下面を有す
る凸部が形成されているとともに、下面の外周部が前記
第1のボンディングワイヤよりも最高位置が高くかつ略
同じ高さを有するとともに前記電極および/または前記
電極パッドに接続された複数の第2のボンディングワイ
ヤで支持されていることを特徴とする半導体装置。
Claims 1. A semiconductor element mounted on an upper main surface of an insulating substrate, an electrode formed on an outer peripheral portion of an upper surface of the semiconductor element, and a semiconductor element on the upper main surface around the semiconductor element. A first bonding wire electrically connecting the formed electrode pads, a sealing resin layer provided so as to cover the semiconductor element and the first bonding wire, and disposed above the semiconductor element; And a metal plate whose lower surface is embedded in the upper portion of the sealing resin layer and whose upper surface is exposed, the metal plate being close to the center of the upper surface of the semiconductor element at the center of the lower surface. And the outer peripheral portion of the lower surface has the highest position higher than the first bonding wire and has substantially the same height as the first bonding wire. Wherein a being supported by a plurality of second bonding wires connected to the electrode pads.
JP2002019537A 2002-01-29 2002-01-29 Semiconductor device Expired - Fee Related JP3904934B2 (en)

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WO2005071743A1 (en) * 2004-01-22 2005-08-04 Renesas Technology Corp. Semiconductor package and semiconductor device
EP2111636A1 (en) * 2006-12-21 2009-10-28 Agere Systems, Inc. High thermal performance packaging for circuit dies
JP2010021515A (en) * 2008-06-12 2010-01-28 Renesas Technology Corp Semiconductor device and its manufacturing method
JP2010161125A (en) * 2009-01-06 2010-07-22 Fujitsu Ltd Mounting structure for package substrate, and electronic component
JP2013141047A (en) * 2013-04-24 2013-07-18 Dainippon Printing Co Ltd Semiconductor device, semiconductor device manufacturing method and shield plate
JP2017168486A (en) * 2016-03-14 2017-09-21 日本電気株式会社 Electronic apparatus and manufacturing method for the same
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Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005071743A1 (en) * 2004-01-22 2005-08-04 Renesas Technology Corp. Semiconductor package and semiconductor device
KR101323978B1 (en) * 2006-12-21 2013-10-30 에이저 시스템즈 엘엘시 High thermal performance packaging for circuit dies
JP2010514208A (en) * 2006-12-21 2010-04-30 アギア システムズ インコーポレーテッド Packaging for high thermal performance of circuit dies
EP2111636A1 (en) * 2006-12-21 2009-10-28 Agere Systems, Inc. High thermal performance packaging for circuit dies
EP2111636A4 (en) * 2006-12-21 2014-09-10 Agere Systems Inc High thermal performance packaging for circuit dies
JP2010021515A (en) * 2008-06-12 2010-01-28 Renesas Technology Corp Semiconductor device and its manufacturing method
JP2010161125A (en) * 2009-01-06 2010-07-22 Fujitsu Ltd Mounting structure for package substrate, and electronic component
JP2013141047A (en) * 2013-04-24 2013-07-18 Dainippon Printing Co Ltd Semiconductor device, semiconductor device manufacturing method and shield plate
JP2017168486A (en) * 2016-03-14 2017-09-21 日本電気株式会社 Electronic apparatus and manufacturing method for the same
WO2018181871A1 (en) * 2017-03-31 2018-10-04 株式会社村田製作所 Module
CN110476245A (en) * 2017-03-31 2019-11-19 株式会社村田制作所 Module
JPWO2018181871A1 (en) * 2017-03-31 2020-01-23 株式会社村田製作所 module
US11177189B2 (en) 2017-03-31 2021-11-16 Murata Manufacturing Co., Ltd. Module including heat dissipation structure
JP2022505927A (en) * 2018-10-30 2022-01-14 長江存儲科技有限責任公司 IC package
JP7303294B2 (en) 2018-10-30 2023-07-04 長江存儲科技有限責任公司 IC package

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