JP2003196149A - Memory control device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To set an optimum weight number in each clock frequency matched to a necessary memory access time between a CPU and a memory in order to reduce the power consumption by changing the clock frequency of a microcomputer for a lower power consumption. <P>SOLUTION: This memory control device 110 comprises a weight number setting circuit 114 and a weight control circuit 115. The weight number setting circuit 114 comprises a weight number setting resistor 116 and a selector line 117. The selector line selectively outputs all m-bits of the weight number setting resistor or the m-bits in which 0 is added by k-bits to the highest-order side of the (m-k) bits except the k-bit of the lowest-order to the weight control circuit 115 according to a clock selection signal S0 showing the change of clock frequency. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device for controlling access to a CPU and a memory circuit built in an LSI.

[0002]

2. Description of the Related Art In recent years, LSIs are becoming faster and lower in power consumption, and the operating frequency of clocks is becoming higher and higher. for that reason,
There is used a method of switching between an operation clock when high-speed processing is required and a clock when sufficient low-speed processing is possible by switching the clock frequency.

FIG. 18 is a block diagram showing the structure of a conventional LSI.

Reference numeral 501 denotes an LSI, which is a microcomputer 502,
The memory 503, the clock input terminal 504, the clock output terminal 505, the clock selection signal terminal 506, the memory address bus 507, and the memory data bus 508.

Reference numeral 502 is a microcomputer, which has a CPU 509,
Memory control device 510, clock control circuit 511, CP
It is composed of a U address bus 512 and a CPU data bus 513.

A memory 503 is connected to the memory address bus 507 and the memory data bus 508 and reads / writes data from / to the memory data bus 508 at an address indicated by the memory address bus 507.

Reference numeral 504 is a clock input terminal, and 505
Is a clock output terminal, and the clock input terminal 504 and the clock output terminal 505 are oscillators or oscillators 52.
Connected to 3 for self-oscillation.

Reference numeral 509 denotes a CPU, which receives an internal clock CLK from the clock control circuit 511 to execute an instruction and is connected to the CPU address bus 512 and the CPU data bus 513, the memory access request signal S1, and the memory access permission signal S2. Memory access request signal S1
Is output to the weight control circuit 515 and the memory access permission signal S2 is input from the weight control circuit 515,
CPU address bus 512 and CPU data bus 513
To perform address and data transfer.

Reference numeral 510 denotes a memory control device which receives the internal clock CLK from the clock control circuit 511 to control memory access, connects the memory address bus 507 and the CPU address bus 512, and connects the memory data bus 508 and the CPU. The data bus 513 is connected, the clock selection signal S0 is input from the clock selection signal terminal 506, the memory access request signal S1 is input from the CPU 509, and the memory access permission signal S2 is output to the CPU 509.

Reference numeral 511 denotes a clock control circuit, which is a low speed clock obtained by dividing the external clock supplied from the clock input terminal 504 and the clock output terminal 505 according to the value of the clock selection signal S0 applied to the clock selection signal terminal 506, or as it is. CP as a high-speed clock for
It is supplied to the U 509 and the memory control device 510.

Reference numeral 515 is a weight control circuit, which is a CPU
When the memory access request signal S1 is input from 509,
It waits for the number of wait cycles input from the wait number setting circuit 514, and outputs a memory access permission signal S2 to the CPU 509 after the wait.

FIG. 19 shows a conventional weight number setting circuit 514.
It is a block diagram showing the structure of.

A weight number setting circuit 514 is composed of a weight number setting register 516, and outputs the set number of weights set in the weight number setting register 516 to the weight control circuit 515 as it is.

Reference numeral 516 is a weight number setting register,
The CPU 509 is an m-bit (m is a natural number) register accessible through the CPU address bus 512 and the CPU data bus 513.

With respect to the LSI configured as described above,
The operation will be described below.

FIG. 20 shows a clock selection signal terminal 506 to a clock control circuit 511 and a weight number setting circuit 514.
To the CPU 509 and the memory control unit 510 from the clock control circuit 511, and the weight number setting circuit 514 to the weight control circuit 515. Number of weights, CPU50
9 to the weight control circuit 515 from the memory access request signal S1, the weight control circuit 515 to the CPU
5 is a timing chart showing a memory access permission signal S2 supplied to 509.

In this case, the memory 503 requires a memory access time of 30 nsec or more, and the CPU 509 is a CPU.
The wait number "2" is set in the wait number setting register 516 via the address bus 512 and the CPU data bus 513.

The external clock is 100 MHz, and the internal clock CLK is 100 MH when the clock selection signal S0 input to the clock selection signal terminal 506 is "0".
The external clock of z is output as it is as a high-speed clock of 100 MHz, and when the clock selection signal S0 is "1", the external clock is divided by 2 to output a low-speed clock of 50 MHz.

The operation of the first phase from time T0 to time T1 and the second phase from time T1 to time T2 will be described below.

In the first phase, the clock selection signal terminal 506 is set to "0". Clock control circuit 51
1 indicates that the clock selection signal S0 is "0", so that the 100 MHz external clock supplied from the clock input terminal 504 and the clock output terminal 505 is 100 MHz as it is.
The z internal clock CLK is output to the CPU 509 and the memory control device 510. When the wait control circuit 515 receives the memory access request signal S1 from the CPU 509, it waits for two cycles corresponding to the number of waits “2” output from the number of waits setting circuit 514, and after waiting,
The memory access permission signal S2 is output to the CPU 509. The memory access time from the rising of the memory access request signal S1 to the rising of the memory access permission signal S2 is 30 nsec. 100 MHz is 10 nsec
Is equivalent to 2 cycles weight, so 10 *
(2 + 1) = 30 nsec.

In the second phase, the clock selection signal terminal 506 is set to "1". Clock control circuit 51
1 indicates that the clock selection signal S0 is "1", so the external clock of 100 MHz supplied from the clock input terminal 504 and the clock output terminal 505 is divided by 2 to obtain 50M.
It is output to the CPU 509 and the memory controller 510 as an internal clock CLK of Hz. Weight control circuit 515
Receives the memory access request signal S1 from the CPU 509, waits for two cycles corresponding to the number of waits “2” output from the number of waits setting circuit 514, and after waiting,
The memory access permission signal S2 is output to the CPU 509. The memory access time from the rise of the memory access request signal S1 to the rise of the memory access permission signal S2 is 60 nsec. 50MHz corresponds to 20nsec, and since it waits for 2 cycles, 20 * (2
+1) = 60 nsec.

[0022]

However, in the conventional configuration, since the memory control device 510 waits at the constant value set in the wait number setting register 516,
When the clock becomes slow, the number of waits corresponding to the required memory access time decreases compared to the case of a high-speed clock, but the wait number remains the same as the number of waits required for a high-speed clock. Access between the CPU 509 and the memory 503 is performed in a redundant memory access time.

In order to avoid this inconvenience, it is necessary to set the number of waits again from the CPU 509 via the CPU address bus 512 and the CPU data bus 513 by a program, but the instruction for setting the number of waits is set in the program. It is necessary to add, and the access time of the CPU 509 for setting the number of waits is consumed, and when the operation clock switching timing is undefined, it is difficult to determine which part of the program corresponds. Therefore, this is a problem in speeding up the operation of the LSI 501 and minimizing the program size.

The present invention solves the above-mentioned conventional problems, and provides a memory control device that automatically changes the number of waits without the need to reset the number of waits by a program even when the operating clock is switched. The purpose is to

[0025]

A memory control device according to the present invention, which is intended to solve the above problems, sets the number of waits required when a CPU accesses a memory and changes the frequency of an operating clock of an LSI. And a wait number setting means for changing the wait number so that an optimum memory access time is obtained, and when a memory access request signal is received from the CPU, wait is performed according to the wait number, and after the wait, the CPU accesses the memory. A weight control means for outputting a permission signal is provided.

By changing the number of waits when the operation clock of the LSI changes, the memory access time between the CPU and the memory is optimized.

The following is a more specific description.

As a first solution, the present invention provides a CPU that executes instructions, a memory that stores data, and an LSI.
A clock selecting means for selecting at least two kinds of frequencies when the operating clock is high speed or low speed, and the number of waits required when the CPU accesses the memory are set by the CPU. A memory controller provided with a wait number setting means and a wait control means for waiting according to the set wait number when a memory access request signal is received from the CPU and outputting a memory access permission signal to the CPU after the wait. Assumption. The present invention, which is the first solution means, solves the above problem by taking the following means. That is, the weight number setting means is the CPU
Reduce the number of waits set in the number of waits setting register for setting the number of waits required when the memory accesses the memory, and the number of waits set in the number of waits setting register when the clock selecting means indicates a low speed operation. And a means for varying the number of weights for outputting.

According to this, when the operating clock of the LSI changes, the number of waits is switched, so that the CP
The memory access time between U and the memory can be optimized.

In the above-mentioned preferred embodiment, the weight number varying means preferably sets all of the m-bit (m is a natural number) set weight number set in the weight number setting register when the operation clock is made high speed. This is to select and output m bits.

Further, in the above, in a preferred mode, the wait number varying means sets the lowest k bits of the m-bit set wait number set in the wait number setting register when the operation clock is slowed down. This is to select and output m bits obtained by adding 0 bits to the most significant side of (m−k) bits excluding (k is a natural number).

As a second solving means, the present invention is similar to the above, in which the CPU for executing the instruction, the memory for storing the data, and the operation clock of the LSI are either high speed or low speed. A clock selection means for selecting a frequency of more than one type, a wait number setting means for setting the number of waits required when the CPU accesses the memory by the CPU, and a memory access request signal from the CPU. In this case, it is assumed that the memory control device is provided with a wait control means that waits according to the set number of waits and outputs a memory access permission signal to the CPU after the wait. The present invention of the second solving means solves the above problems by taking the following means. That is, the number-of-waits setting means sets the number of waits required when the CPU accesses the memory, and the number-of-waits setting when the clock selecting means indicates a high-speed operation. And a weight number varying means for increasing and outputting the set weight number set in the register.

According to this, by changing the number of waits when the operation clock of the LSI changes, the CP
The memory access time between U and the memory can be optimized.

In the above-described preferred embodiment, the wait number varying means excludes the most significant k bits of the set wait number of m bits set in the wait number setting register when the operation clock is speeded up. (mk)
That is, m bits obtained by adding 1 k bits to the least significant bit side are selected and output.

Further, in the above-mentioned preferred mode, the wait number varying means sets all m bits of the set wait number of m bits set in the wait number setting register when the operation clock is slowed down. It is to select and output.

As a third solving means, the present invention is similar to the above, in which the CPU for executing the instruction, the memory for storing the data, and the operation clock of the LSI are either high speed or low speed. A clock selection means for selecting a frequency of more than one type, a wait number setting means for setting the number of waits required when the CPU accesses the memory by the CPU, and a memory access request signal from the CPU. In this case, it is assumed that the memory control device is provided with a wait control means that waits according to the set number of waits and outputs a memory access permission signal to the CPU after the wait. Then, the present invention of the third solving means solves the above-mentioned problems by taking the following means. That is, the weight number setting means corresponds to the plurality of weight number setting registers for setting the number of weights required when the CPU accesses the memory, and the operation clocks indicated by the clock selection means. And a selection means for selecting one of the plurality of weight number setting registers.

According to this, the optimum memory access time can be maintained by switching the number of waits when the operation clock of the LSI changes.

In the above, a preferable mode is that the selecting means corresponds to the operation clock from the n number of weight number setting registers when the operation clock is changed in n ways (n is a natural number of 2 or more). One weight number setting register is selected, and all m bits of the set weight number of the selected weight number setting register are output.

As a fourth solving means, the present invention is similar to the above, in which the CPU for executing the instruction, the memory for storing the data, and the operation clock of the LSI are either high speed or low speed. A clock selection means for selecting a frequency of more than one type, a wait number setting means for setting the number of waits required when the CPU accesses the memory by the CPU, and a memory access request signal from the CPU. In this case, the weight is waited according to the set number of waits, and after the wait, a wait control means for outputting a memory access permission signal to the CPU, and a clock input from the outside are controlled to supply the clock to the CPU and the wait control means. It is premised on a memory control device having a clock control means. And the present invention of the fourth solving means solves the above-mentioned problems by taking the following means. That is, the clock control means divides at least one kind of the input clock and outputs the divided clock to the weight control means, and the input clock or the divided clock according to the operation clock of the LSI. And a selecting means for selecting one or more kinds of frequency-divided clocks by the frequency dividing means and outputting to the CPU.

According to this, by switching the frequency of the clock for the CPU when the operation clock of the LSI changes, it is possible to maintain the optimum memory access time between the CPU and the memory.

In the above, in a preferred aspect, when the selecting means speeds up the operation clock, the C
An input clock is selected and supplied to the PU.

Further, in the above description, a preferred mode is that the selecting means selects and supplies the clock divided by the dividing means to the CPU when the operation clock is slowed down.

As a fifth means for solving the problems, in the present invention, similarly to the above, the CPU for executing an instruction, the memory for storing data, and the case where the power supply voltage of the LSI is high or low depending on the setting by the CPU. Voltage or a regulator for controlling at least two types of voltages and outputting a power supply voltage drop signal, and a weight number setting means for setting the number of weights required when the CPU accesses the memory by the CPU. And a wait control means which waits according to the set number of waits when a memory access request signal comes from the CPU and outputs a memory access permission signal to the CPU after the wait. The present invention as the fifth solving means solves the above-mentioned problems by taking the following means. That is, the number-of-waits setting means sets the number-of-waits setting register for setting the number of waits required when the CPU accesses the memory, and the number-of-waits setting register when the regulator indicates a high voltage. And a weight number varying means for increasing and outputting the set number of set weights.

According to this, when the power supply voltage of the LSI changes, the optimum memory access time between the CPU and the memory can be maintained by switching the number of waits by the power supply voltage drop signal.

In the above-described preferred embodiment, the weight number varying means sets the m-bit (m is a natural number) set weight number set in the weight number setting register when the power supply voltage is set to a high voltage. This is to select and output m bits obtained by adding 1 k bits to the least significant side of (m−k) bits excluding the most significant k bits (k is a natural number).

Further, in the above, in a preferred mode, the weight number varying means sets all the m bits of the set weight number of m bits set in the weight number setting register when the power supply voltage is set to a low voltage. Is to select and output.

[0047]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a memory control device according to the present invention will be described below in detail with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram showing the configuration of an LSI common to the first and second embodiments of the present invention.

Reference numeral 101 is an LSI, and a microcomputer 102,
The memory 103, the clock input terminal 104, the clock output terminal 105, the clock selection signal terminal 106, the memory address bus 107, and the memory data bus 108.

Reference numeral 102 denotes a microcomputer, which is a CPU 109,
Memory control device 110, clock control circuit 111, CP
It is composed of a U address bus 112 and a CPU data bus 113.

Reference numeral 103 denotes a memory, which is connected to the memory address bus 107 and the memory data bus 108 and reads / writes data from / to the memory data bus 108 at an address indicated by the memory address bus 107.

Reference numeral 104 is a clock input terminal, and 105
Is a clock output terminal, and the clock input terminal 104 and the clock output terminal 105 are oscillators or oscillators 12.
Connected to 3 for self-oscillation.

Reference numeral 109 denotes a CPU, which is connected to the CPU address bus 112 and the CPU data bus 113, the memory access request signal S1, and the memory access permission signal S2, receives the internal clock CLK from the clock control circuit 111, and executes an instruction. Memory access request signal S
1 is output to the wait control circuit 115 and the memory access permission signal S2 is input from the wait control circuit 115, the CPU address bus 112 and the CPU data bus 1
13 is used to perform address and data transfer.

Reference numeral 110 denotes a memory control device, which receives supply of the internal clock CLK from the clock control circuit 111 to control memory access, connects the memory address bus 107 and the CPU address bus 112, and connects the memory data bus 108 and the CPU. The data bus 113 is connected, the clock selection signal S0 is input from the clock selection signal terminal 106, the memory access request signal S1 is input from the CPU 109, and the memory access permission signal S2 is output to the CPU 109.

Reference numeral 111 denotes a clock control circuit, which is a low-speed clock obtained by dividing the external clock supplied from the clock input terminal 104 and the clock output terminal 105 according to the value of the clock selection signal S0 input to the clock selection signal terminal 106, or as it is. CP as a high-speed clock for
It is supplied to U109 and the memory control device 110.

Reference numeral 115 is a weight control circuit, which is a CPU
When the memory access request signal S1 is input from 109,
The number of effective weights Dw input from the number-of-waits setting circuit 114 is waited for the number of cycles, and after the wait, the memory access permission signal S2 is output to the CPU 109.

FIG. 2 is a block diagram showing the configuration of the weight number setting circuit 114 according to the first embodiment of the present invention.

Reference numeral 114 is a weight number setting circuit, which comprises a weight number setting register 116 and a selector array 117.

Reference numeral 116 is a weight number setting register,
The CPU 109 is an m-bit (m is a natural number) register accessible by the CPU address bus 112 and the CPU data bus 113.

Reference numeral 117 denotes a selector train, which excludes all m bits of the set weight number held by the weight number setting register 116 or the least significant bit of the set weight number by the clock selection signal S0 supplied from the clock selection signal terminal 106 ( The effective weight number Dw is output by selecting m-1) bits and m bits obtained by adding 1 bit fixed to 0 to the most significant bit side. Here, m = 4. It is fixed to 0 that the 1 input of the uppermost selector (the leftmost selector in the drawing) in the selector row 117 is at the ground level. The selector array 117 corresponds to the "weight number varying means" in the claims.

The "1" in (m-1) and the 1-bit "1" fixed to 0 are added to (m-) in the claims.
This corresponds to an example of “k” in k).

Regarding the LSI configured as described above,
The operation will be described below.

In FIG. 3, the clock selection signal S0 supplied from the clock selection signal terminal 106 to the clock control circuit 111 and the weight number setting circuit 114, the clock control circuit 1
Internal clock CLK supplied from the CPU 11 to the CPU 109 and the memory control device 110, the weight number setting register 1
Number of set weights set to 16 and weight number setting circuit 1
14, the effective weight number Dw supplied from the CPU 14 to the weight control circuit 115, and the weight control circuit 115 from the CPU 109.
6 is a timing chart showing a memory access request signal S1 supplied to the CPU 109 and a memory access permission signal S2 supplied from the wait control circuit 115 to the CPU 109.

Here, the memory 103 requires a memory access time of 30 nsec or more, and the CPU 109 is the CPU.
The number of waits "2" is set in the number of waits setting register 116 via the address bus 112 and the CPU data bus 113.

The external clock is 100 MHz, and the internal clock CLK is 100 M when the clock selection signal S0 input to the clock selection signal terminal 106 is "0".
The external clock of Hz is output as it is as a high-speed clock of 100 MHz, and when the clock selection signal S0 is "1", the external clock is divided by 2 to output a low-speed clock of 50 MHz.

The operation of the first phase from time T0 to time T1 and the second phase from time T1 to time T2 will be described below.

In the first phase, the clock selection signal S0 input to the clock selection signal terminal 106 is set to "0". Since the clock selection signal S0 is "0", the clock control circuit 111 uses the 100 MHz external clock supplied from the clock input terminal 104 and the clock output terminal 105 as it is as the internal clock C of 100 MHz.
It is output to the CPU 109 and the memory control device 110 as LK. Since the clock selection signal S0 of the selector array 117 in the weight number setting circuit 114 is "0", all 4 bits of the weight number setting register 116 are selected and "2" is set as the effective weight number Dw.
Output to 5.

The weight control circuit 115 includes the CPU 109.
When the memory access request signal S1 is received from the wait number setting circuit 114, the wait number setting circuit 114 waits for two cycles corresponding to the effective weight number Dw of "2".
The memory access permission signal S2 is output to the CPU 109. The memory access time from the rising of the memory access request signal S1 to the rising of the memory access permission signal S2 is 30 nsec.

In the second phase, the clock selection signal S0 input to the clock selection signal terminal 106 is set to "1". Since the clock selection signal S0 is "1", the clock control circuit 111 divides the external clock of 100 MHz supplied from the clock input terminal 104 and the clock output terminal 105 by two to divide the internal clock CL of 50 MHz.
It is output as K to the CPU 109 and the memory control device 110. Since the clock selection signal S0 is "1", the selector string 117 selects the upper 3 bits excluding the least significant bit of the wait number setting register 116 and the 4 bits obtained by adding 1 bit fixed to 0 to the most significant bit and is effective. "1" is output to the weight control circuit 115 as the number of weights Dw.

The set weight number “2” is (0010) in binary notation. The upper 3 bits excluding the least significant bit are (001), and the 4 bits obtained by adding 1 bit fixed to 0 to the most significant bit (00) are (00).
01), which is "1". That is, the effective weight number Dw becomes "1".

The weight control circuit 115 includes the CPU 109.
When the memory access request signal S1 is received from the wait number setting circuit 114, the wait number setting circuit 114 waits for one cycle corresponding to the effective weight number Dw of "1".
The memory access permission signal S2 is output to the CPU 109. The memory access time from the rise of the memory access request signal S1 to the rise of the memory access permission signal S2 is 40 nsec. Since 50 MHz corresponds to 20 nsec and one cycle is waited, 20 * (1
+1) = 40 nsec.

Although the external clock and the memory access time and the number of waits set in the number-of-waits setting register 116 are specified here, they can be operated with arbitrary values. The relationship between the clock frequency and the effective weight number Dw when the clock frequency for high-speed operation is f1 (f1 is a natural number) and the minimum number of set weights required for high-speed operation is n1 (n1 is a natural number) It shows in Table 1. However, the effective weight number Dw is a value rounded down after the decimal point.

[0073]

[Table 1] Although the clock selection signal S0 input from the clock selection signal terminal 106 has been described as 1 bit here,
Even when the clock selection signal S0 has a plurality of bits, if the external clock is divided by 2 ^k (k is 0 or a natural number) and input as the internal clock CLK, the selector row 117 is similarly used.
Can be applied by using multiple bits. Table 2 shows the relationship between the clock frequency and the number of effective weights Dw when the clock selection signal S0 has a plurality of bits. However, the effective weight number Dw is a value rounded down after the decimal point.

[0074]

[Table 2] FIG. 4 shows the configuration of the weight number setting circuit 114 when k = 2. Two selectors connected to the ground level, which is fixed to 0, are provided on the uppermost side.

As described above, when the memory controller 110 sets the minimum number of waits corresponding to the memory access time required by the memory 103 when the internal clock CLK operates at high speed, the internal clock CLK becomes slow. Even when the operation is started, the CPU 109 to C by the program
It is not necessary to reset the number of waits in the number-of-waits setting register 116 via the PU address bus 112 and the CPU data bus 113, and the memory access time required by the memory 103 at the internal clock CLK in the low speed operation is always automatically set. Corresponding minimum required number of effective weights D
The CPU 109 and the memory 103 can be accessed by w.

(Embodiment 2) According to the above-described first embodiment of the present invention, the problems of the prior art are solved, but there is still room for improvement. In the case of the first embodiment, because of the error in the memory controller 110, which is obtained by rounding down the effective weight number Dw in the low speed operation,
May require redundant memory access times.
Therefore, there is room for further optimization in optimizing the memory access time. This will be described below as a second embodiment.

FIG. 5 is a block diagram showing the configuration of the weight number setting circuit according to the second embodiment of the present invention. FIG. 1 is referred to for other configurations of the second embodiment.

Reference numeral 114 is a weight number setting circuit, which comprises a weight number setting register 118 and a selector array 119.

Reference numeral 118 is a weight number setting register,
The CPU 109 is an m-bit (m is a natural number) register accessible by the CPU address bus 112 and the CPU data bus 113.

Numeral 119 is a selector array (weight number varying means) consisting of m selectors, and the total number of weights set by the weight number setting register 118 is m by the clock selection signal S0 supplied from the clock selection signal terminal 106. The effective weight number Dw is output by selecting (m-1) bit excluding the most significant bit of the set weight number or m bit obtained by adding one fixed bit to the least significant bit side. Here, m = 4. It is fixed that one input of the lowest selector in the selector array 119 (the selector at the right end in the drawing) is at the power supply level.

The above "m" of (m-1) and the addition of one fixed 1 bit "1" is (m-) in the claims.
This corresponds to an example of “k” in k).

Regarding the LSI configured as described above,
The operation will be described below.

FIG. 6 shows the clock selection signal S0 supplied from the clock selection signal terminal 106 to the clock control circuit 111 and the weight number setting circuit 114, the clock control circuit 1
Internal clock CLK supplied from the CPU 11 to the CPU 109 and the memory control device 110, the weight number setting register 1
Number of set weights to be set to 18, weight number setting circuit 1
14, the effective weight number Dw supplied from the CPU 14 to the weight control circuit 115, and the weight control circuit 115 from the CPU 109.
6 is a timing chart showing a memory access request signal S1 supplied to the CPU 109 and a memory access permission signal S2 supplied from the wait control circuit 115 to the CPU 109.

Here, the memory 103 requires a memory access time of 60 nsec or more, and the CPU 109 is the CPU.
The weight number “2” is set in the weight number setting register 118 via the address bus 112 and the CPU data bus 113.

The external clock is 100 MHz, and the internal clock CLK is 100 M when the clock selection signal S0 input to the clock selection signal terminal 106 is "1".
The external clock of Hz is output as it is as a high-speed clock of 100 MHz, and when the clock selection signal S0 is "0", the external clock is divided by two to output a low-speed clock of 50 MHz. This relationship is opposite to that of the first embodiment, but is the same in that when the clock selection signal S0 is "0", the set weight number set in the weight number setting register is used as it is.

The operation of the first phase from time T0 to time T1 and the second phase from time T1 to time T2 will be described below.

In the first phase, the clock selection signal S0 input to the clock selection signal terminal 106 is set to "1". In the clock control circuit 111, since the clock selection signal S0 is "1", the 100 MHz external clock supplied from the clock input terminal 104 and the clock output terminal 105 is directly used as the internal clock C of 100 MHz.
It is output to the CPU 109 and the memory control device 110 as LK. Since the clock selection signal S0 is "1", the selector string 119 in the weight number setting circuit 114 selects all four bits by adding the lower 3 bits of the weight number setting register 118 and 1 bit fixed to 1 to the least significant bit side. Then, the effective weight number Dw “5” is set to the weight control circuit 115.
Output to.

The lower 3 bits excluding the most significant bit of the set weight number "2", that is, the binary number (0010) is (010), and the least significant bit is fixed to 1 bit for this (010). 4 bits with (0101)
Which is "5". That is, the effective weight number Dw is "5".

The weight control circuit 115 includes the CPU 109.
When the memory access request signal S1 is received from the wait number setting circuit 114, the wait number setting circuit 114 waits 5 cycles corresponding to the effective wait number Dw of "5".
The memory access permission signal S2 is output to the CPU 109. The memory access time from the rise of the memory access request signal S1 to the rise of the memory access permission signal S2 is 60 nsec. 100 MHz is 10 nsec
Is equivalent to 5 cycles, so 10 *
(5 + 1) = 60 nsec.

In the second phase, the clock selection signal S0 is set to "0". Since the clock selection signal S0 is “0”, the clock control circuit 111 divides the external clock of 100 MHz supplied from the clock input terminal 104 and the clock output terminal 105 by 2 to generate the internal clock CLK of 50 MHz as the CPU 109 and the memory control device. Output to 110. Since the clock selection signal S0 is "0", the selector train 119 selects all 4 bits of the weight number setting register 118 and outputs "2" of the effective weight number Dw to the weight control circuit 115.

The weight control circuit 115 includes the CPU 109.
When the memory access request signal S1 is received from the weight number setting circuit 114, the effective weight number Dw is "2".
Corresponding to, wait for 2 cycles, wait, then CPU
The memory access permission signal S2 is output to 109. The memory access time from the rise of the memory access request signal S1 to the rise of the memory access permission signal S2 is 60 nsec.

Although the external clock, the memory access time, and the number of waits set in the number-of-waits setting register 118 are specified here, they can be operated with arbitrary values. The relationship between the clock frequency and the effective weight number Dw when the clock frequency for low speed operation is f1 (f1 is a natural number) and the minimum number of set weights required for low speed operation is n1 (n1 is a natural number) It shows in Table 3.

[0093]

[Table 3] Although the clock selection signal S0 input from the clock selection signal terminal 106 has been described as 1 bit here,
Even when the clock selection signal S0 has a plurality of bits, if the external clock frequency is multiplied by 2 ^k (k is 0 or a natural number) and is input as the internal clock CLK, the selector row 1 is similarly selected.
This can be applied by making the selection input of 19 a plurality of bits. Table 4 shows the relationship between the clock frequency and the number of effective weights Dw when the clock selection signal S0 has a plurality of bits.

[0094]

[Table 4] FIG. 7 shows the configuration of the weight number setting circuit 114 when k = 2. Two selectors connected to the fixed power supply level are provided on the lowest side.

As described above, even when the internal clock CLK operates at low speed, the memory control device 110 does not have the problem of redundancy due to truncation of the set weight number as in the case of the first embodiment. It is possible to access with the minimum necessary effective weight number Dw optimized for the memory access time required by the memory 103 in the clock CLK (the second phase requires 60 nsec, which is the same as in the first phase), and by the program. It is possible to access the CPU 109 and the memory 103 automatically with the minimum necessary effective weight number Dw corresponding to the memory access time required by the memory 103 in the internal clock CLK in the low speed operation without resetting the number of weights. And

(Third Embodiment) According to the second embodiment of the present invention, the memory access time is optimized, but there is still room for improvement. In the case of the second embodiment, the memory control device 110 cannot cope with the frequency change of the internal clock CLK at a magnification other than 2 ^k times. Therefore, there is room for further improvement in dealing with the case where the internal clock CLK changes at an arbitrary rate. This will be described below as a third embodiment.

FIG. 8 is a block diagram showing the configuration of an LSI according to the third embodiment of the present invention.

Reference numeral 201 denotes an LSI, which is a microcomputer 202,
It comprises a memory 203, a clock input terminal 204, a clock output terminal 205, a clock selection signal terminal 206, a memory address bus 207, and a memory data bus 208.

Reference numeral 202 denotes a microcomputer, which is a CPU 209,
Memory control device 210, clock control circuit 211, CP
It is composed of a U address bus 212 and a CPU data bus 213.

Reference numeral 203 denotes a memory, which is connected to the memory address bus 207 and the memory data bus 208 and reads / writes data from / to the memory data bus 208 at an address indicated by the memory address bus 207.

Reference numeral 204 is a clock input terminal, and 205
Is a clock output terminal, and the clock input terminal 204 and the clock output terminal 205 are oscillators or oscillators 22.
Connected to 3 for self-oscillation.

Reference numeral 206 denotes a 2-bit clock selection signal terminal, which supplies a clock frequency selection signal input from the outside to the clock control circuit 211 and the weight number setting circuit 214.

Reference numeral 209 denotes a CPU, which is connected to the CPU address bus 212 and the CPU data bus 213, the memory access request signal S1, and the memory access permission signal S2, and receives the internal clock CLK from the clock control circuit 211 to execute the instruction. Memory access request signal S
When 1 is output to the wait control circuit 215 and the memory access permission signal S2 is input from the wait control circuit 215, the CPU address bus 212 and the CPU data bus 2
13 is used to perform address and data transfer.

Reference numeral 210 denotes a memory control device, which receives the internal clock CLK from the clock control circuit 211 to control memory access, connects the memory address bus 207 and the CPU address bus 212, and connects the memory data bus 208 and the CPU. It connects to the data bus 213, inputs the clock selection signal S0 from the clock selection signal terminal 206, inputs the memory access request signal S1 from the CPU 209, and outputs the memory access permission signal S2 to the CPU 209.

Reference numeral 211 denotes a clock control circuit, which is a low-speed clock obtained by dividing the external clock supplied from the clock input terminal 204 and the clock output terminal 205 according to the value of the clock selection signal S0 input to the clock selection signal terminal 206, or as it is. CP as a high-speed clock for
It is supplied to the U209 and the memory control device 210.

Reference numeral 215 is a weight control circuit, which is a CPU
When the memory access request signal S1 is input from 209,
The effective number of weights Dw input from the number-of-waits setting circuit 214 is waited for the number of cycles, and after the wait, the memory access permission signal S2 is output to the CPU 209.

FIG. 9 is a block diagram showing the configuration of the weight number setting circuit 214 according to the third embodiment of the present invention.

Reference numeral 214 is a weight number setting circuit, which comprises a first weight number setting register 218, a second weight number setting register 219, a third weight number setting register 220, and a selector 221.

Reference numeral 218 is a first weight number setting register, 219 is a second weight number setting register, 22
0 is a third weight number setting register, and all of these three weight number setting registers are
It is an m-bit (m is a natural number) register accessible via the address bus 212 and the CPU data bus 213.

Reference numeral 221 denotes a selector having three inputs and one output,
First weight number setting register 218, second weight number setting register 219, third weight number setting register 220
Is selected to output the effective weight number Dw.
First weight number setting register 218, second weight number setting register 219, third weight number setting register 22
The necessary minimum number of weights corresponding to the frequency of the internal clock CLK to be used is set for each 0, and the effective weight corresponding to the frequency of the internal clock CLK is set by the clock selection signal S0 input from the clock selection signal terminal 206. Output the number Dw.

FIG. 10 shows the clock selection signal terminal 206 to the clock control circuit 211 and the weight number setting circuit 214.
To the CPU 209 and the memory control device 210 from the clock control circuit 211, the first weight number setting register 218, the second weight number setting register 219, and the third weight number setting register. The number of set weights set in 220 and the number of effective weights Dw, CP supplied from the weight number setting circuit 214 to the weight control circuit 215, respectively.
A memory access request signal S1 supplied from the U209 to the weight control circuit 215, and a memory access permission signal S2 supplied from the weight control circuit 215 to the CPU 209.
2 is a timing chart showing

Here, the memory 203 requires a memory access time of 60 nsec or more, and the CPU 209 is the CPU.
Through the address bus 212 and the CPU data bus 213, the weight number "5" is set in the first weight number setting register 218, the weight number "3" is set in the second weight number setting register 219, and the third weight number is set. The weight number “2” is set in the register 220.

The external clock is 200 MHz, and the internal clock CLK is 200 M when the clock selection signal S0 input to the clock selection signal terminal 206 is "0".
The external clock of Hz is divided by 2 to output a clock of 100 MHz, and when the clock selection signal S0 is "1", the external clock is divided by 3 to output a clock of 66.7 MHz to output the clock selection signal S0. When is "2", the external clock is divided by 4 and a 50 MHz clock is output.

The operation of the first phase from time T0 to time T1, the second phase from time T1 to time T2, and the third phase from time T2 to time T3 will be described below.

In the first phase, the clock selection signal S0 input to the clock selection signal terminal 206 is set to "0". Since the clock selection signal S0 is "0", the clock control circuit 211 divides the external clock of 200 MHz supplied from the clock input terminal 204 and the clock output terminal 205 into two, and the CPU 209 and the memory control as the internal clock CLK of 100 MHz. Output to the device 210. Since the clock selection signal S0 is “0”, the selector 221 has the first wait number setting register 218.
To output "5" to the weight control circuit 215 as the effective weight number Dw. Weight control circuit 215
When receiving the memory access request signal S1 from the CPU 209, waits for 5 cycles corresponding to the effective weight number Dw “5” output from the weight number setting circuit 214.
After waiting, the memory access permission signal S to the CPU 209
2 is output. The memory access time from the rise of the memory access request signal S1 to the rise of the memory access permission signal S2 is 60 nsec. 10 * (5+
1) = 60 nsec.

In the second phase, the clock selection signal S0 is set to "1". Since the clock selection signal S0 is "1", the clock control circuit 211 divides the external clock of 200 MHz supplied from the clock input terminal 204 and the clock output terminal 205 by 3 to generate 66.7 MHz.
It is output to the CPU 209 and the memory control device 210 as the internal clock CLK of z. Since the clock selection signal S0 is "1", the selector 221 selects the second weight number setting register 219 and outputs "2" to the weight control circuit 215 as the effective weight number Dw. When the wait control circuit 215 receives the memory access request signal S1 from the CPU 209, the wait control circuit 215 waits for three cycles corresponding to the effective weight number Dw of "3" output from the weight number setting circuit 214, and after the wait, allows the CPU 209 to access the memory. The signal S2 is output. The memory access time from the rise of the memory access request signal S1 to the rise of the memory access permission signal S2 is 60 nsec. 15n for 66.7MHz, which is obtained by dividing 200MHz by 3
It corresponds to sec and waits for 3 cycles, so 15
* (3 + 1) = 60 nsec.

In the third phase, the clock selection signal S0 is set to "2". Since the clock selection signal S0 is "2", the clock control circuit 211 divides the external clock of 200 MHz supplied from the clock input terminal 204 and the clock output terminal 205 by 4 to obtain the internal clock CLK of 50 MHz as the CPU 209 and the memory control device. Output to 210. Since the clock selection signal S0 is "2", the selector 221 selects the third weight number setting register 220 and outputs "2" to the weight control circuit 215 as the effective weight number Dw. The weight control circuit 215 receives the memory access request signal S from the CPU 209.
When 1 is received, the wait number setting circuit 214 waits for two cycles corresponding to the effective weight number Dw of "2", and after the wait, outputs the memory access permission signal S2 to the CPU 209. The memory access time from the rise of the memory access request signal S1 to the rise of the memory access permission signal S2 is 60 nsec. 50M
Since Hz corresponds to 20 nsec and two cycles are weighted, 20 * (2 + 1) = 60 nsec.

As described above, the memory access time is 60 nsec in any phase.

The external clock and the memory access time, the number of weights set in the first weight number setting register 218, the second weight number setting register 219, and the third weight number setting register 220 are designated and explained. Each can be operated with any value. When the internal clock CLK frequency to be used is f1, f2 and f3 and the minimum number of set weights required for each operating frequency is n1, n2 and n3 respectively, the relationship between the clock frequency and the effective weight number Dw is shown. 5 shows.

[0120]

[Table 5] Further, here, the clock selection signal S0 input from the clock selection signal terminal 206 has a 2-bit width of "0",
Although three types of "1" and "2" have been described, even if there are more types of clock selection signals S0, it is possible to apply by increasing the number of wait setting registers and increasing the bit width of the clock selection signal S0. is there.

As described above, the memory controller 210 does not need to reset the number of waits by the program even when the internal clock CLK changes at an arbitrary rate, and always automatically automatically operates the memory 203 at the internal clock CLK in the low speed operation. CPU 209 and the memory 2 with the minimum necessary number of effective weights Dw corresponding to the memory access time required by
03 access is possible.

(Fourth Embodiment) In the third embodiment of the present invention described above, the microcomputer 202 inputs the clock selection signal S0 to the memory control device 210 in order to select the optimum number of waits. . An alternative technique is the fourth embodiment.

FIG. 11 is a block diagram showing the configuration of an LSI according to the fourth embodiment of the present invention.

Reference numeral 301 is an LSI, and the microcomputer 302,
The memory 303, the clock input terminal 304, the clock output terminal 305, the clock selection signal terminal 306, the memory address bus 307, and the memory data bus 308 are included.

Reference numeral 302 denotes a microcomputer, which has a CPU 309,
Memory control device 310, clock control circuit 311, CP
It is composed of a U address bus 312 and a CPU data bus 313.

A memory 303 is connected to the memory address bus 307 and the memory data bus 308, and reads / writes data from / to the memory data bus 308 at the address indicated by the memory address bus 307.

Reference numeral 304 is a clock input terminal, and 305
Is a clock output terminal, and the clock input terminal 304 and the clock output terminal 305 are oscillators or oscillators 32.
Connected to 3 for self-oscillation.

Reference numeral 309 denotes a CPU, which is connected to the CPU address bus 312 and the CPU data bus 313, the memory access request signal S1, and the memory access permission signal S2, and is supplied from the clock control circuit 311 to the CPU internal clock C.
When the instruction is executed by receiving the supply of LK1, the memory access request signal S1 is output to the wait control circuit 315, and the memory access permission signal S2 is input from the wait control circuit 315, the CPU address bus 312 and the CPU data bus 313 are used. Address and data transfer.

Reference numeral 310 denotes a memory control device, which is used by the clock control circuit 311 to output the internal clock CLK of the memory control device.
2 is supplied to control the memory access, connect the memory address bus 307 and the CPU address bus 312, and connect the memory data bus 308 and the CPU data bus 313.
To connect the memory access request signal S1 to the CPU 30
9 and inputs the memory access permission signal S2 to the CPU3.
It outputs to 09.

Reference numeral 311 is a clock control circuit, which divides the external clock supplied from the clock input terminal 304 and the clock output terminal 305 according to the value of the clock selection signal S0 or outputs it as it is, and the CPU internal clock C
It is supplied to the CPU 309 as LK1, and the memory control device 3
10 is a constant memory controller internal clock C
Supplied as LK2.

Reference numeral 315 is a weight control circuit, which is a CPU
When the memory access request signal S1 is input from 309,
The number of effective weights Dw input from the number-of-waits setting circuit 314 is waited for the number of cycles, and after the wait, the memory access permission signal S2 is output to the CPU 309.

FIG. 12 is a block diagram showing the structure of the clock control circuit 311 according to the fourth embodiment of the present invention.

Reference numeral 311 is a clock control circuit, which is composed of a flip-flop 316 and a selector 317.

Reference numeral 316 denotes a flip-flop, which receives the inverted output of the flip-flop 316 as an input, divides the external clock input from the clock input terminal 304 and the clock output terminal 305 by 2 to generate a clock output, and delays the input by one clock. This signal is output to the selector 317 and the weight control circuit 315 as the memory controller internal clock CLK2.

Reference numeral 317 is a selector, which operates according to the value of the clock selection signal S0 input to the clock selection signal terminal 306.
05 from the external clock or the internal clock C of the memory controller output from the flip-flop 316.
LK2 and select the result of the selection CPU internal clock C
It is output to the CPU 309 as LK1.

FIG. 13 shows the clock selection signal S0 supplied from the clock selection signal terminal 306 to the clock control circuit 311, the CPU internal clock CLK1 supplied from the clock control circuit 311 to the CPU 309, and the memory control device 310 from the clock control circuit 311. Memory control device internal clock CLK2 supplied, wait number setting circuit 31
4 is a timing chart showing the number of set weights set to 4, a memory access request signal S1 supplied from the CPU 309 to the weight control circuit 315, and a memory access permission signal S2 supplied from the weight control circuit 315 to the CPU 309.

Here, the memory 303 requires a memory access time of 40 nsec or more, and the CPU 309 is the CPU.
The wait number “1” is set in the wait number setting circuit 314 via the address bus 312 and the CPU data bus 313.

The external clock is 100 MHz and the CPU
When the clock selection signal S0 input to the clock selection signal terminal 306 is "0", the internal clock CLK1 is output as it is at 100 MHz in the selector 317,
When the clock selection signal S0 is "1", the external clock is divided into two and a 50 MHz clock is output. The memory controller internal clock CLK2 is the clock selection signal S0.
The frequency of the external clock is divided into two and a constant clock of 50 MHz is output regardless of the above.

The operation of the first phase from time T0 to time T1 and the second phase from time T1 to time T2 will be described below.

In the first phase, the clock selection signal S0 input to the clock selection signal terminal 306 is set to "0".
Set to. The clock control circuit 311 divides the external clock by 2 to divide the internal clock C of the memory controller of 50 MHz.
It is output to the memory control device 310 as LK2 and the clock selection signal S0 is "0".
4 and 100M supplied from the clock output terminal 305
CPU internal clock CL without changing the external clock of Hz
It is output to the CPU 309 as K1. The weight control circuit 315 receives the memory access request signal S from the CPU 309.
When 1 is received, the memory controller internal clock CLK2 is waited for one cycle in response to "1" of the effective weight number Dw output from the weight number setting circuit 314, and after the wait, the memory access permission signal S2 is output to the CPU 309. . The memory access time from the rise of the memory access request signal S1 to the rise of the memory access permission signal S2 is 40 nsec. 20 * (1 + 1) = 4
It is 0 nsec.

In the second phase, the clock selection signal S0 is set to "1". The clock control circuit 311 divides the external clock by 2 and outputs it as a 50 MHz clock to the memory control device 310. Since the clock selection signal S0 is "1", it is supplied from the clock input terminal 304 and the clock output terminal 305. The 100 MHz external clock is divided by 2 and output to the CPU 309 as the CPU internal clock CLK1. The weight control circuit 315 is
When the memory access request signal S1 is received from the CPU 309, the memory controller internal clock CLK2 is waited for one cycle corresponding to the effective weight number Dw of "1" output from the weight number setting circuit 314.
The memory access permission signal S2 is output to 309. The memory access time from the rise of the memory access request signal S1 to the rise of the memory access permission signal S2 is 40 nsec. 20 * (1 + 1) = 40 nsec.

Although the external clock, the memory access time, and the number of waits set in the number-of-waits setting circuit 314 are specified here, they may be operated with arbitrary values.

As described above, the memory control device 310 uses the internal clock output from the clock control circuit 311 as CP.
The CPU internal clock CLK1 supplied to the U309 and the memory control device internal clock CLK2 supplied to the memory control device 310 are divided into two types. Memory controller 310
It is possible to automatically and automatically access the CPU 309 and the memory 303 in the minimum memory access time required by the memory 303 without inputting the clock selection signal S0 to the CPU and setting the number of waits by the program. To do.

(Embodiment 5) According to the first to fourth embodiments of the present invention described above, it is possible to select the optimum number of waits by the clock selection signal S0.
This is not taken into consideration for changes in voltage. Therefore, next, a fifth embodiment will be described in which the optimum number of weights can be selected even if the voltage changes.

FIG. 14 is a block diagram showing the structure of an LSI according to the fifth embodiment of the present invention.

Reference numeral 401 is an LSI, and the microcomputer 402,
The memory 403, the clock input terminal 404, the clock output terminal 405, the memory address bus 407, the memory data bus 408, the power supply input terminal 418, the regulator output terminal 419, and the regulator input terminal 420.

Reference numeral 402 denotes a microcomputer, which is used as a regulator 4
06, CPU 409, memory control device 410, clock control circuit 411, CPU address bus 412, and CPU data bus 413.

A memory 403 is connected to the memory address bus 407 and the memory data bus 408, and reads / writes data from / to the memory data bus 408 at the address indicated by the memory address bus 407.

Reference numeral 404 is a clock input terminal, and 405
Is a clock output terminal, and the clock input terminal 404 and the clock output terminal 405 are oscillators or oscillators 42.
Connected to 3 for self-oscillation.

A CPU 409 is connected to the CPU address bus 412 and the CPU data bus 413, the memory access request signal S1, and the memory access permission signal S2, and receives the internal clock CLK from the clock control circuit 411 to execute the instruction. Memory access request signal S
When 1 is output to the wait control circuit 415 and the memory access permission signal S2 is input from the wait control circuit 415, the CPU address bus 412 and the CPU data bus 4
13 is used to perform address and data transfer.

Reference numeral 406 is a regulator, which is a C via a CPU address bus 412 and a CPU data bus 413.
According to the value set from the PU 409, the specified voltage obtained by dropping the power supply voltage supplied from the regulator input terminal 420 is output to the regulator output terminal 419, and the power supply voltage drop signal SE is sent to the weight number setting circuit 414 in the memory control device 410. Is output.

Reference numeral 410 denotes a memory control device, which receives the internal clock CLK from the clock control circuit 411 to control memory access, connects the memory address bus 407 and the CPU address bus 412, and connects the memory data bus 408 and the CPU. The power supply voltage drop signal SE is input from the regulator 406 by connecting to the data bus 413, the memory access request signal S1 is input from the CPU 409, and the memory access permission signal S2 is output to the CPU 409.

Reference numeral 411 denotes a clock control circuit, which supplies the external clock supplied from the clock input terminal 404 and the clock output terminal 405 to the CPU 409 and the memory control device 410 as a constant internal clock CLK as it is.

Reference numeral 415 is a weight control circuit, which is a CPU
When the memory access request signal S1 is input from 409,
The effective number of weights Dw input from the number-of-waits setting circuit 414 is waited for the number of cycles, and after the wait, the memory access permission signal S2 is output to the CPU 409.

Reference numeral 418 is a power source input terminal, which inputs the regulator output from the regulator output terminal 419.

A regulator output terminal 419 outputs the regulator output input from the regulator 406 to the power supply input terminal 418.

Reference numeral 420 is a regulator input terminal, which is L
A constant DC voltage input from outside the SI is output to the regulator 406 as a regulator input voltage.

FIG. 15 is a block diagram showing the structure of the weight number setting circuit 414 according to the fifth embodiment of the present invention.

Reference numeral 414 is a weight number setting circuit, which comprises a weight number setting register 416 and a selector column 417.

Reference numeral 416 is a weight number setting register,
The CPU 409 is an m-bit (m is a natural number) register accessible through the CPU address bus 412 and the CPU data bus 413.

Reference numeral 417 denotes a selector array (weight number varying means) consisting of m selectors, and the regulator 406.
All the m bits of the set weight number held by the weight number setting register 416 or the least significant bit of the set weight number are excluded by the power supply voltage drop signal SE supplied from
The effective weight number Dw is selected by selecting (1) bit and m bit in which 1 bit fixed to 0 is added to the most significant bit side. Here, m = 4.

The "1" in (m-1) and the 1-bit "1" fixed to 0 added in (m-) in the claims.
This corresponds to an example of “k” in k).

FIG. 16 shows the power supply voltage drop signal SE supplied from the regulator 406 to the weight number setting circuit 414 of the clock control circuit 411, the internal clock CLK supplied from the clock control circuit 411 to the CPU 409 and the memory control device 410, and the number of weights. The number of set weights set in the setting register 416, and the number of effective weights D supplied from the weight number setting circuit 414 to the weight control circuit 415.
w, the memory access request signal S1 supplied from the CPU 409 to the weight control circuit 415, the weight control circuit 4
15 is a timing chart showing a memory access permission signal S2 supplied from 15 to the CPU 409.

Here, the memory 403 requires a memory access time of 30 nsec or more in the high operating voltage state,
Since the transition time becomes long in the low operating voltage state, the memory access time is required to be 50 nsec or more. CP
U409 sets the number of waits "4" in the number of waits setting circuit 414 via the CPU address bus 412 and the CPU data bus 413.

The regulator 406 sets the power supply voltage drop signal SE to "1" in a high operating voltage state above a certain threshold value, and sets the power supply voltage drop signal SE in a low operating voltage state below a certain threshold value. Is set to "0" and supplied to the weight number setting circuit 414.

The external clock is 100 MHz, and the internal clock CLK outputs the external clock as it is at 100 MHz. The clock selection signal S0 is not used.

The operation of the first phase from time T0 to time T1 and the second phase from time T1 to time T2 will be described below.

In the first phase, the regulator 40
Since 6 is in the high operating voltage state, "1" is output as the power supply voltage drop signal SE. Since the power supply voltage drop signal SE is "1", the selector string 417 selects the upper 3 bits excluding the least significant bit of the wait number setting register 416 and the 4 bits obtained by adding 1 bit fixed to 0 to the most significant bit. “2” of the effective weight number Dw is output to the weight control circuit 415.

The upper 3 bits excluding the least significant bit of the set weight number "4", that is, the binary notation (0100) is (010), and the most significant bit is fixed to 0 for this (010). 4 bits added is (0010)
Which is "2". That is, the effective weight number Dw is "2".

The weight control circuit 415 has a CPU 409.
When the memory access request signal S1 is received from the wait number setting circuit 414, the wait number setting circuit 414 waits for two cycles corresponding to the effective weight number Dw of "2".
The memory access permission signal S2 is output to the CPU 409. The memory access time from the rising of the memory access request signal S1 to the rising of the memory access permission signal S2 is 30 nsec. 10 * (2 + 1) = 30
nsec.

In the second phase, the regulator 40
Since 6 is in a low operating voltage state, the power supply voltage drop signal SE
"0" is output as. Since the power supply voltage drop signal SE is "0", the selector train 417 selects all 4 bits of the weight number setting register 416 and outputs "4" of the effective weight number Dw to the weight control circuit 415. When the wait control circuit 415 receives the memory access request signal S1 from the CPU 409, the wait control circuit 415 waits for four cycles corresponding to the effective weight number Dw of "4" output from the weight number setting circuit 414, and after the wait, allows the CPU 409 to access the memory. The signal S2 is output. The memory access time from the rising of the memory access request signal S1 to the rising of the memory access permission signal S2 is 50 nsec. 10 * (4 + 1) = 50 nsec.

Although the external clock and the memory access time and the number of waits set in the number-of-waits setting circuit 414 have been designated and described here, they can be operated with arbitrary values. Further, when controlling the power supply voltage drop signal SE from the outside of the microcomputer 402, it can be realized by directly inputting the power supply voltage drop signal SE to the weight number setting circuit 414.

Although the power supply voltage drop signal SE supplied from the regulator 406 is used in place of the clock selection signal S0 in the above, it is also possible to use both the clock selection signal S0 and the power supply voltage drop signal SE. , In that case, the power supply voltage drop signal SE and the clock selection signal S0
It is possible to input the signal and to the logical sum circuit and input the output signal to the weight number setting circuit 414 to operate in the optimum wait time.

FIG. 17 shows the configuration of the weight number setting circuit 414 when k = 2. Two selectors connected to the ground level, which is fixed to 0, are provided on the uppermost side.

Thus, not only when the clock selection signal S0 is input to the clock control circuit to change the clock frequency, but also when the power supply voltage drop signal SE from the regulator 406 is input to the weight number setting circuit 414, Memory access required by the memory 403 at the internal clock CLK in low speed operation automatically without resetting the number of waits in the number of waits setting circuit 414 from the CPU 409 via the CPU address bus 412 and the CPU data bus 413 by a program. CPU 409 and memory 4 with the minimum necessary number of effective weights Dw corresponding to time
03 access is possible.

[0176]

As described above, according to the present invention as the first means for solving the problems, in the memory control device, the memory access time required by the memory at the internal clock at the low speed operation is required even when the internal clock is at the low speed operation. It is possible to access with the minimum necessary effective weight optimized for
In addition, the CPU and memory can always be accessed with the minimum necessary effective weight number corresponding to the memory access time required by the memory at the internal clock in the low-speed operation without resetting the number of weights by the program. .

Further, according to the present invention as the second solving means, the memory control device is optimal for the memory access time required by the memory at the internal clock at the low speed operation even when the internal clock is at the low speed operation. It is necessary to support the memory access time required by the memory at the internal clock in low-speed operation without automatically resetting the number of waits by using the optimized minimum number of effective waits. The CPU and memory can be accessed with the minimum number of effective weights.

Further, according to the present invention as the third means for solving the problems, the memory control device always operates automatically at a low speed without resetting the number of waits by the program even when the internal clock changes by an arbitrary multiplication factor. The CPU and the memory can be accessed with the minimum necessary number of effective weights corresponding to the memory access time required by the memory at the internal clock.

Further, according to the present invention as the fourth solving means, the memory control device is configured such that the internal clock output from the clock control means is supplied to the CPU and the memory supplied to the memory control device. The internal clock of the controller is divided into two types, and the internal clock of the memory controller is kept constant so that the number of waits can be set by a program without inputting a clock selection signal to the memory controller even if the frequency of the clock changes. Without doing
The CPU and the memory can always be accessed automatically in the minimum memory access time required by the memory.

Further, according to the present invention as the fifth solving means, the memory control device is not limited to the case where the clock frequency is changed by inputting the clock selection signal to the clock control means, but the power supply voltage drop from the regulator is caused. Even when a signal is input to the clock control means, the program automatically stores the memory at the internal clock in the low speed operation without resetting the number of waits from the CPU to the number of waits setting means via the CPU address bus and the CPU data bus. The CPU and the memory can be accessed with the minimum required number of effective weights corresponding to the required memory access time.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an LSI including a memory control device according to first and second embodiments of the present invention.

FIG. 2 is a block diagram showing a configuration of a weight number setting circuit in the memory control device according to the first embodiment.

FIG. 3 is a timing chart illustrating the operation of the memory control device according to the first embodiment.

FIG. 4 is a block diagram showing a configuration of a weight number setting circuit in a modification of the first embodiment.

FIG. 5 is a block diagram showing a configuration of a weight number setting circuit in the memory control device according to the second embodiment of the present invention.

FIG. 6 is a timing chart illustrating the operation of the memory control device according to the second embodiment.

FIG. 7 is a block diagram showing a configuration of a weight number setting circuit in a modification of the second embodiment.

FIG. 8 is a block diagram showing a configuration of an LSI including a memory control device according to a third embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of a weight number setting circuit in a memory control device according to a third embodiment.

FIG. 10 is a timing chart illustrating the operation of the memory control device according to the third embodiment.

FIG. 11 is a block diagram showing a configuration of an LSI including a memory control device according to a fourth embodiment of the present invention.

FIG. 12 is a block diagram showing a configuration of a clock control circuit in a memory control device according to a fourth embodiment.

FIG. 13 is a timing chart illustrating the operation of the memory control device according to the fourth embodiment.

FIG. 14 is a block diagram showing a configuration of an LSI including a memory control device according to a fifth embodiment of the present invention.

FIG. 15 is a block diagram showing a configuration of a weight number setting circuit in a memory control device according to a fifth embodiment.

FIG. 16 is a timing chart illustrating the operation of the memory control device according to the fifth embodiment.

FIG. 17 is a block diagram showing a configuration of a weight number setting circuit in a modification of the fifth embodiment.

FIG. 18 is a block diagram showing the configuration of a conventional LSI.

FIG. 19 is a block diagram showing a configuration of a conventional weight number setting circuit.

FIG. 20 is a timing chart illustrating the operation of the conventional memory control device.

[Description of Reference Signs] 101, 201, 301, 401 LSI 102, 202, 302, 402 Microcomputer 103, 203, 303, 403 Memory 104, 204, 304, 404 Clock input terminal 105, 205, 305, 405 Clock output terminal 106 , 206, 306 Clock selection signal terminals 107, 207, 307, 407 Memory address buses 108, 208, 308, 408 Memory data buses 109, 209, 309, 409 CPUs 110, 210, 310, 410 Memory control devices 111, 211, 311, 411 Clock control circuits 112, 212, 312, 412 CPU address buses 113, 213, 313, 413 CPU data buses 114, 214, 314, 414 Weight number setting circuits 115, 215, 315, 415 Control circuit 116, 118, 216, 416 weight number setting register 117, 119, 217, 417 selector row 218 first weight number setting register 219 second weight number setting register 220 third weight number setting register 221, 317 selector 316 flip-flop 406 Regulator 418 Power input terminal 419 Regulator output terminal 420 Regulator input terminal

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G06F 15/78 G06F 15/78 510P (72) Inventor Jiro Miyake 1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric Industrial In-house F-term (reference) 5B033 BC02 BC04 BC06 5B060 CC02 CC03 5B062 AA05 CC01 DD02 DD10 HH02 HH06

Claims (15)

[Claims] 1. A weight number setting means for setting the number of waits required when a CPU accesses a memory and changing the number of waits so as to obtain an optimum memory access time corresponding to a frequency change of an operation clock of an LSI. When a memory access request signal is received from the CPU, the CPU waits according to the number of waits, and after waiting, the C
A memory control device comprising a weight control means for outputting a memory access permission signal to the PU. 2. A CPU for executing instructions, a memory for storing data, a clock selecting means for selecting at least two kinds of frequencies depending on whether the operation clock of the LSI is high speed or low speed, and the CPU. Wait number setting means for setting the number of waits required by the CPU by the CPU, and when the memory access request signal is received from the CPU, waits according to the set wait number, and after the wait, A wait control means for outputting a memory access permission signal to the CPU, wherein the wait number setting means is a wait number setting register for setting a wait number required when the CPU accesses the memory; If the selecting means indicates a low speed operation, it is set in the weight number setting register. Memory control apparatus characterized by and a number of wait states varying means for outputting to reduce the set number of weights that. 3. The wait number varying means selects and outputs all m bits of the set wait number of m bits set in the wait number setting register when the operation clock is speeded up. The memory control device according to claim 2. 4. The wait number varying means is the lowest k of the m-bit set wait numbers set in the wait number setting register when the operation clock is slowed down.
3. The memory control device according to claim 2, wherein m bits obtained by adding 0 k bits to the most significant bits of (mk) bits excluding bits are selected and output. 5. A CPU for executing instructions, a memory for storing data, a clock selecting means for selecting at least two kinds of frequencies depending on whether the operation clock of the LSI is high speed or low speed, and the CPU. Wait number setting means for setting the number of waits required by the CPU by the CPU, and when the memory access request signal is received from the CPU, waits according to the set wait number, and after the wait, A wait control means for outputting a memory access permission signal to the CPU, wherein the wait number setting means is a wait number setting register for setting a wait number required when the CPU accesses the memory; If the selection means indicates high-speed operation, it is set in the weight number setting register. Memory control apparatus characterized by and a number of wait states varying means for outputting by increasing the set number of weights that. 6. The weight number varying means sets the highest k of m-bit set weight numbers set in the wait number setting register when the operation clock is made high speed.
6. The memory controller according to claim 5, wherein m bits obtained by adding 1 k bits to the least significant side of (m−k) bits excluding bits are selected and output. 7. The wait number varying means selects and outputs all m bits of the set wait number of m bits set in the wait number setting register when the operation clock is slowed down. The memory control device according to claim 5. 8. A CPU for executing instructions, a memory for storing data, clock selecting means for selecting at least two types of frequencies depending on whether the operation clock of the LSI is high speed or low speed, and the CPU. Wait number setting means for setting the number of waits required by the CPU by the CPU, and when the memory access request signal is received from the CPU, waits according to the set wait number, and after the wait, Weight control means for outputting a memory access permission signal to the CPU, wherein the weight number setting means has a plurality of weight number setting registers for setting the number of weights required when the CPU accesses the memory; The plurality of wait number setting levels are set in correspondence with the respective operation clocks indicated by the clock selecting means. Memory control apparatus characterized by and a selection means for selecting one of a register. 9. The selecting means sets the operating clock to n.
When the number of weights is changed (n is a natural number of 2 or more), one weight number setting register corresponding to the operation clock is selected from the n number of weight number setting registers, and the selected weight number setting register is set. Total number of weights m
9. The memory controller according to claim 8, wherein the memory controller outputs bits. 10. A CPU for executing instructions, a memory for storing data, a clock selecting means for selecting at least two kinds of frequencies depending on whether the operation clock of the LSI is high speed or low speed, and the CPU. Wait number setting means for setting the number of waits required by the CPU by the CPU, and when the memory access request signal is received from the CPU, waits according to the set wait number, and after the wait, The CPU includes a weight control unit that outputs a memory access permission signal to the CPU, and a clock control unit that controls a clock input from the outside to supply a clock to the CPU and the weight control unit. At least one type of clock is divided and the divided clock is used as the way. A frequency dividing means for outputting to the control means, and a selecting means for selecting the input clock or one or more kinds of frequency-divided clocks by the frequency dividing means according to an operation clock of the LSI and outputting the selected clock to the CPU. And a memory control device. 11. The memory control device according to claim 10, wherein the selecting means selects and supplies an input clock to the CPU when the operation clock is speeded up. 12. The memory according to claim 10, wherein the selecting means selects and supplies the clock divided by the dividing means to the CPU when the operation clock is slowed down. Control device. 13. A CPU executing instructions, a memory storing data, and controlling at least two kinds of voltages depending on whether the power supply voltage of the LSI is a high voltage or a low voltage according to the setting by the CPU. A regulator that outputs a power supply voltage drop signal, a weight number setting means that sets the number of weights required by the CPU when the CPU accesses the memory, and a memory access request signal from the CPU. Wait weight control means for outputting a memory access permission signal to the CPU after the weight is waited according to the set number of waits, and the weight number setting means is a weight required when the CPU accesses the memory. The number of weights setting register to set the number, and if the regulator shows high voltage, Memory control apparatus characterized by and a number of wait states varying means for outputting by increasing the set number of wait set in the wait number setting register. 14. The weight number varying means sets the highest k of m-bit set weight numbers set in the weight number setting register when the power supply voltage is set to a high voltage.
14. The memory control device according to claim 13, wherein m bits obtained by adding 1 k bits to the least significant side of (m−k) bits excluding bits are selected and output. 15. The weight number varying means selects and outputs all m bits of the set weight number of m bits set in the weight number setting register when the power supply voltage is set to a low voltage. 14. The memory controller according to claim 13, wherein the memory controller is a memory controller.