JP2002100488A - Discharge lamp lighting control pulse generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate a pulse signal for highly accurately controlling pulse width. SOLUTION: This discharge lamp lighting control pulse generator is provided with an A/D converter 2 for performing A/D conversion on a control signal, a register 3 for setting this value, a clock generator 4, a counter 5 for counting clock signal and a comparator 6 for outputting a signal for regulating the rise time when there is coincidence in time by comparing a count value of the counter 5 with a preset value of the register. The register 3 uses a ninth bit for judging positive or negative, and uses remaining bits for comparison in the counter 5. AND circuits 8 to 11 and an OR circuit 12 are provided for outputting signals which agree with the count value of the counter 5 at one time of the positive, and the negative corresponding to the content of the ninth bit of the register 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control pulse generator for driving and driving a discharge lamp.

[0002]

2. Description of the Related Art A discharge lamp is driven by a pulse width modulated pulse signal from a lighting circuit. In particular, it is required that the power be set high at the start of driving and be controlled with high precision so that the power gradually decreases after lighting.

Conventionally, an analog circuit has been employed as a pulse width modulation circuit for obtaining such pulse width modulated pulse signals. Explaining the principle of operation, when a constant current Ic [A] flows through a capacitor having a capacitance C [F], the voltage Vc [V] of the capacitor after t [sec] is Vc = Q / C = Ic · t
/ C (Expression 1) Therefore, a constant current Ic [A] is supplied to the capacitor having the capacitance C [F], and the voltage of the capacitor is changed to V.
Time t12 [sec] required to change from c1 [V] to Vc2 [V]
Is t12 = C. (Vc1-Vc2) / Ic (Equation 2).

FIG. 8 shows a waveform of a signal generated in each section of a conventional analog pulse width modulation circuit. The analog pulse width modulation circuit periodically repeats an operation of charging a constant current Ic of a predetermined level obtained from a power supply through a resistor having a predetermined resistance value through a capacitor, and an operation of discharging after charging. Triangular wave (FIG. 8 (b), B1; FIG.
(A) generates a current flowing through the capacitor, and the voltage level of this triangular wave is the threshold voltage level for modulation (FIG. 8 (b),
It is configured to output a high-level signal only during a period exceeding v). Then, by adjusting the threshold voltage level (FIG. 8 (b), v1 and v2), a required pulse width (FIG. 8 (c), D1, D2) is obtained.

[0005]

The analog pulse width modulation circuit requires a capacitor. By the way, as can be seen from (Equation 2), time depends on the capacitance, voltage, and current of the capacitor, so that it is not easy to control the time with high accuracy. In particular, since the capacitance, voltage, and current of a capacitor have temperature characteristics, there is a problem that variations in temperature must be considered in actual circuit operation. Similarly, in a mode in which a resistance element is adopted, this variation in resistance value,
Temperature characteristics also need to be considered. If the pulse width is not accurately controlled, quality problems such as a difference in brightness of the discharge lamp and occurrence of flicker occur.

[0006] The present invention has been made in view of the above,
It is an object of the present invention to provide a discharge lamp lighting control pulse generation device that generates a pulse signal whose pulse width is controlled with high precision by counting a clock signal having a fixed period and comparing the count value with a set value.

[0007]

According to a first aspect of the present invention, there is provided a discharge lamp lighting control pulse generating apparatus for generating a pulse signal having a predetermined width by defining a rising edge and a falling edge of a pulse using a timer circuit. A timer for generating a clock signal having a predetermined period, a counter for counting the clock signal, and a first setting in which a value corresponding to a rising edge of a pulse is set using a predetermined number of bits. And a first comparison circuit that compares a count value of the counter with a set value of the first setting device, and outputs a signal that defines a rising time point when the values match with each other, and the first comparison circuit The setter uses the bit of the predetermined digit for positive / negative judgment, and uses the remaining bits for comparison in the first comparison circuit. It is characterized in that it has a decision circuit for outputting a coincidence signal while the time of the positive and negative in accordance with the contents.

According to this configuration, the rise and fall of the lighting control pulse are defined by the timer circuit, and a pulse signal having a predetermined width is generated. In the timer circuit, a clock signal from a clock generator is counted by a counter, and the count value of the counter is compared with a value corresponding to a rising edge of a pulse using a predetermined number of bits set in a first setting device. And when they match,
A signal defining the rising point is output. In the first setting device, a bit of a predetermined digit is used for positive / negative judgment, and the remaining bits are used for comparison in the first comparison circuit. The determination circuit of the timer circuit outputs a coincidence signal at one of the positive and negative times according to the content of the bit of the predetermined digit. Thus, the pulse width adjustment setting is accurately performed within the range between the minimum pulse width and the maximum pulse width according to the value set by the first setting device.

According to a second aspect of the present invention, the timer circuit includes a second setter for setting a value corresponding to a falling edge of the pulse using a predetermined number of bits, a count value of the counter and a second setter. And a second comparator circuit for comparing the set value of the setter and outputting a signal specifying the falling time point when they match. According to this configuration, the falling time point is also specified as desired. It is possible to do.

According to a third aspect of the present invention, there is provided a switching circuit for alternately switching the counting operation of the counter between an up direction and a down direction. According to this configuration, in the case of a counter that counts only in one direction, The number of bits for counting from the start of the counting operation to the falling edge of the counter is required, but by switching the counting direction, a double time width can be counted. The bit of the counter is reduced by one.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a waveform chart for explaining an outline of a basic operation in a discharge lamp lighting control pulse generating apparatus according to the present invention. The discharge lamp lighting control pulse generation device includes a clock pulse generator, a counter for counting the clock pulse, a setter in which thresholds 1 and 2 are set, and a comparator, as described in FIG. It is prepared as. As shown in FIG.
The clock pulse train is counted by the counter,
Assume that count values are obtained as in 19, 20, 24, 25, 27, 28,. Then, when the count value matches the value “24” set as the threshold 1 (at time t1), the output rises, and then the value “2” set as the threshold 2
7 "(at time t2), the output pulse having the pulse width corresponding to three periods of the clock pulse is generated in this manner. FIG. 2 shows a discharge lamp lighting control pulse according to the present invention. Fig. 2 is a block diagram showing a first embodiment of the generating apparatus, wherein a control signal output unit 1 is provided in a control unit (not shown) for controlling a lighting driving operation, and a level signal corresponding to a pulse width to be set. Is output.
The conversion circuit 2 converts the level signal from the control signal output unit 1 into a 9-bit digital value as described later. The register 3 stores the output value of the A / D conversion circuit 2 so as to be output in 9 bits.

The clock generator 4 outputs a clock signal having a predetermined period. The cycle of the clock signal is set to a required cycle because it becomes a reference width for pulse width adjustment. The counter 5 counts a clock signal from the clock generator 4, and starts a counting operation in response to an input reset signal. In this embodiment, the count value is output in 12 bits. The comparator 6 compares the count value of the counter 5 with the set value of the register 3, and outputs a high signal, that is, “1” from the terminal GT while the count value of the counter 5 exceeds the set value of the register 3. Things. The lower 6 bits of the register 3 and the count value of the lower 8 bits of the counter 5 are input to the comparator 6. The AND circuit 7 receives the count value from the counter 5, and the most significant bit of the 12 bits is "0".
When all the rest are "1", "1" is output.

That is, as shown in the time chart of FIG. 5A, the upper 3 bits of the counter 5 are "0", "1",
When it is "1" (and when the lower 9 bits are all "1"), it returns from "1" to "0".

The AND circuits 8 to 11 and the OR circuit 12 constitute a determination circuit. The upper 4 bits of the counter 5 and the positive / negative determination bit of the register 3 are connected to the AND circuits 8 and 9. Specifically, the AND circuit 8
At its input end are "0", "1", "0", "0" from the upper bit side of the counter 5 and "1" from the positive / negative determination bit of the register 3, that is, "0",
When "1", "0", "0", and "1" are input, "1" is output. The AND circuit 9 has "0", "1", "0",
“1” and “0” of the positive / negative determination bit of the register 3 are
That is, when "0", "1", "0", "1", and "0" are input, the output "1" is output. The AND circuit 10 receives the output of the AND circuit 8 and the output of the comparator 6. The output of the AND circuit 9 and the output of the comparator 6 are input to the AND circuit 11. OR circuit 12 is AND circuit 1
Outputs 0 and 11 are input. The hold circuit 13 holds this level when "1" is output from the OR circuit 12. The output circuit 14 returns the output terminal Pout to "0" when "1" is input from the AND circuit 7. That is, the present device receives the output “1” from the comparator 6, changes the output terminal Pout of the output circuit 14 from “0” to “1”, receives the output “1” from the AND circuit 7, The output terminal Pout of the output circuit 14 is "1"
To “0”, and the output terminal Pout of the output circuit 14
To generate a pulse having a width corresponding to the period during which "1" is output from.

Here, the positive / negative determination bit of the register 3 will be described. In the present apparatus, when the analog value output from the control signal output unit 1 is within a certain range, a pulse having a width corresponding to the level is output at a constant cycle. At this time, a maximum pulse width Dmax and a minimum pulse width Dmin are set for the output pulse width. In the present embodiment, for example, 23% to 43% (<50%).
%). When the analog value is out of the range, the maximum pulse width Dmax or the minimum pulse width Dmin is set.

FIG. 3 is a diagram showing the relationship between the analog value, the A / D conversion value of the A / D conversion circuit 2, and the pulse width. As shown in this figure, the analog value is expressed as a voltage, and -1 to +1
[V], when the A / D conversion circuit 2 has 9 bits,
The accuracy of the conversion circuit 2 is {1-(-1)} / (512-1) = 0.00391
[V]. Here, the register 3 for setting a value corresponding to the width of the pulse to be generated uses the most significant bit for positive / negative determination (see line L1 in FIG. 2) and compares the remaining 8 bits with the count value of the counter 5. It is used for business purposes.

In FIG. 3, 0 [V] corresponds to the A / D converted value (000000000), -0.00391 [V] corresponds to the A / D converted value (111111111), and -1 [V]. In response to the A / D conversion value (100000000), +1 [V] is the A / D conversion value (01
A / D conversion is performed so as to correspond to (1111111). further,
The most significant bit is "1", corresponding to a negative analog value, and the most significant bit is "0", corresponding to a positive analog value. Then, -1 [V] (A / D conversion value (10000000
0)) corresponds to a ratio of 43% (maximum pulse width Dmax), and +
1 [V] (A / D conversion value (011111111)) is 23% of the ratio
(Minimum pulse width Dmin), and 0 [V] (A / D conversion value (000000000)) corresponds to an intermediate ratio. Therefore, the sign is expressed as a sign relative to the reference pulse width at 0 [V].

FIG. 4 is a view showing the contents of FIG. 3 as a whole of one pulse period. In one period outputted from the output terminal Pout of the output circuit 14, the maximum pulse width Dmax and the minimum pulse A control region where the pulse width can be adjusted is set between the width Dmin. Explaining this control region in an enlarged manner in the time axis direction, the contents of the positive / negative judgment bit of the register 3 are “1”, that is, the first half of the negative value, and the contents of the positive / negative judgment bit of the register 3 are “0”, that is, It can be seen that it is composed of the positive second half.

In FIG. 2, in order to make the pulse width controllable in the control region shown in FIG. 4, as described above, the positive / negative judgment bit of the register 3 and the upper 4 bits of the counter 5 are used for the AND circuits 8 and 9. Connected to input terminal. Here, the operation in the control region shown in FIG. 4 will be described. FIGS. 5A and 5B show the control area in association with the bits. FIG. 5A is a time chart corresponding to the contents of the upper three bits of the counter, and FIG. 5B is an extracted control area. It is a time chart corresponding to the content of a bit. That is, the counter 5 shown in FIG.
Are "0", "1", and "0", the AND circuits 8 and 9 are both in a state of waiting for input to the other two input terminals. If the bit is “0”, it becomes “0”, “1”, “0”, “0” as shown by using the AND circuit 8 in FIG. If the upper 4th bit is "1", on the contrary, "0", "1", "0", "1" as shown by using the AND circuit 9 in FIG. This corresponds to the latter half of the control area. An A / D conversion value corresponding to a negative analog value is set in the first half of the control region, and an A / D conversion value corresponding to a positive analog value is set in the second half of the control region. Circuit 8, 9
Input terminal side is set.

Next, the operation of the circuit configuration of FIG. 2 will be described.
Now, it is assumed that -0.00391 [V], that is, the A / D conversion value (111111111) is set in the register 3. At this time,
The positive / negative determination bit is “1”.

First, the counter 5 is reset, and the counting operation starts. The reset signal is output as a one-cycle setting signal from a controller (not shown) or the like.
The signal is output at least after "1" is output from the AND circuit 7 and before the counter 5 reaches the full count value.

The counter 5 has 8 bits, that is, "255".
Until the counting is performed, the upper 4 bits of the counter 5 are all “0”. When the counting operation for “255” is repeated five times as shown in FIG. 5A, the upper 4 bits become “0”. "," 1 "," 0 "," 0 "(see FIG. 5B)
And the positive / negative determination bit of the register 3 is “1”, so that the input terminal side of the AND circuit 8 is “0”,
"1", "0", "0", "1" and the AND circuit 8
Outputs "1". During the period in which the upper 4 bits are "0", "1", "0", and "0", the input terminals of the AND circuit 9 do not all become "1". Is not output.

In this state, when the count value of the lower 8 bits of the count 5 reaches (11111111), the comparator 6 outputs "1" to the AND circuits 10 and 11. Since “1” is input to the other input terminal, the AND circuit 10 receives “1” input from the comparator 6 and outputs “1”. On the other hand, the output side of the AND circuit 11 remains “0” because the other input terminal is “0”. The output "1" of the AND circuit 10 is guided to the hold circuit 13 via the OR circuit 12, and as a result, "1" is output from the output terminal Pout of the output circuit 14.

As the counter 5 continues the counting operation, the upper 4 bits become "0", "1", "0",
Although it becomes "1" (see FIG. 5B), in this period, the output of the AND circuit 9 remains "0" as long as the positive / negative judgment bit of the register 3 is "1". On the other hand,
In the AND circuit 8, the upper 4 bits are "0", "1",
Since it is no longer “0” or “0”, the output is “0”.
Back to. Therefore, in the control area, the OR circuit 12 does not output “1” except when the count value of the lower 8 bits of the count 5 reaches (11111111). The AND circuit 8 outputs the upper four bits “0”,
As a result of the output becoming “1”, “0” and “1” and the output returning to “0”, the AND circuit 10 outputs “0”. Pou
The output “1” from t is held.

Further, the counter 5 counts,
Upper 3 bits of counter 5 are “0”, “1”, “1”
When the count value of 12 bits of the counter 5 reaches (011111111111) in the state in the period of FIG. 5A, “1” is output from the AND circuit 7 to the reset terminal of the output circuit 14, The output "1" resets the output circuit 14, and the output terminal Pout of the output circuit 14
Is inverted to “0”. As a result, a high-level pulse signal is output from (010011111111) to (011111111111) with the count value of the counter 5.

Next, 0.99609 [V],
That is, it is assumed that the A / D conversion value (011111111) is set. At this time, the positive / negative determination bit is “0”.

As described above, the counter 5 is reset, and the counting operation starts. Until the counter 5 counts 8 bits, that is, “255”, the upper 4 bits of the counter 5 are all “0”.
When the count operation for 5 "is repeated five times as shown in FIG. 5A, the upper 4 bits are" 0 "," 1 "," 0 ",
It becomes "0" (see FIG. 5B). In this area, since the positive / negative determination bit of the register 3 is “0”, the AND circuit 8 outputs “0”. On the other hand, this top 4
In the area where the bits are "0", "1", "0", and "0", the input terminal side of the AND circuit 9 does not all become "1", so that the AND circuit 9 also outputs "0". .

Further, the counting operation is performed, and the upper 4 bits of the counter 5 are set to "0", "1", "0", "1".
5 (see FIG. 5B), since the positive / negative determination bit of the register 3 is “0”, the AND circuit 8 outputs
While “0” is output, the input terminals of the AND circuit 9 all become “1”, so that “1” is output from the AND circuit 9.

In this state, when the count value of the lower 8 bits of the count 5 reaches (01111111), the comparator 6 outputs "1" to the AND circuits 10 and 11. Since “1” is input to the other input terminal, the AND circuit 11 receives “1” input from the comparator 6 and outputs “1”. On the other hand, the output side of the AND circuit 10 remains “0” because the other input terminal is “0”. The output "1" of the AND circuit 11 is guided to the hold circuit 13 via the OR circuit 12, and as a result, "1" is output from the output terminal Pout of the output circuit 14.

Even if the counter 5 continues the counting operation, the output of the AND circuit 8 remains "0" during this period as long as the positive / negative judgment bit of the register 3 is "0". Therefore, in the control area, the OR circuit 12 does not output “1” except after the count value of the lower 8 bits of the count 5 reaches (01111111).

Further, the counter 5 counts,
Upper 3 bits of counter 5 are “0”, “1”, “1”
When the count value of 12 bits of the counter 5 reaches (011111111111) in the state in the period of FIG. 5A, “1” is output from the AND circuit 7 to the reset terminal of the output circuit 14, The output "1" resets the output circuit 14, and the output terminal Pout of the output circuit 14
Is inverted to “0”. As a result, with the count value of the counter,
During the period from (010111111110) to (011111111111), a high-level pulse signal is output.

In this way, it is possible to control the increase and decrease of the pulse width according to the signal level from the control signal output unit 1 within the period of the control area using the positive / negative determination bit.

Next, FIG. 6 is a block diagram showing a second embodiment of the discharge lamp lighting control pulse generator according to the present invention. FIG. 6 differs from the first embodiment shown in FIG. 2 in that a register 15 is added and a comparator 16 is provided in place of the AND circuit 7. The operation of the same components as those in FIG. Are identical.

Referring to FIG. 7, the operation of the second embodiment will be described. In the first embodiment, the output terminal Pout of the output circuit 14
The falling time of the pulse output from the counter 5 is uniformly set to the time when the count value of the counter 5 becomes (011111111111). However, in the second embodiment, the falling time of this pulse is determined by the count value ( [011111111111) It is possible to shift by ± α with respect to the time point. At this time, the pulse width is from the maximum pulse width Dmax ± α to the minimum pulse width Dmin ±
It can be set between α and the controllable width is the same as in the first embodiment.

Returning to FIG. 6, the register 15 has 12 bits, and {(011111111111) ± α} is set as a numerical value, that is, a count value of the counter 5 from a level setting unit (not shown) in order to define the fall of the pulse. (However, the number in parentheses is a binary number). The comparator 16 outputs "1" while the 12-bit count value from the counter 5 exceeds the 12-bit set value from the register 15, and the output "1" causes the output terminal Pout of the output circuit 14 to output "1". 1 "
To "0". This makes it possible to shift the falling point of the pulse to {(011111111111) ± α}. Also in this case, one cycle is defined by the reset signal input timing of the counter 5 as in the first embodiment.

The present invention can adopt the following modified embodiments. That is, when the control range of the output pulse width is 50% or less of the pulse width, a counter (counter) capable of performing a counting operation in both directions of up and down is adopted instead of the counter 5, and the counting direction is changed. The same operation result as in the first and second embodiments can be obtained by using a switching circuit that switches alternately.
Specifically, the switching circuit includes a detecting unit that detects a point in time when all bits of the counter become “0” or “1”, and receives a detection result from the detecting unit, and counts up / down of the counter.
It is sufficient to provide a switching unit that switches down in the inversion direction and a comparison unit that outputs a signal that defines the falling time of the pulse when the count value returns to the start value (or a predetermined value) after inversion. In the first and second embodiments, after the rising point of the pulse is defined, the counting operation is performed in the same direction in order to define the falling point of the pulse. After defining the rising time point, the counter reverses the counting direction when the counter outputs “0” or “1” from all the bits as described above. For example, when the count value returns to the initial value, What is necessary is just to make the comparison part output a signal defining the falling time point. In this embodiment, since the counting operation is reversed halfway, the number of bits of the counter is set to 1
Can be reduced.

[0037]

According to the first aspect of the present invention, the period of the clock generator is stable and the variation is extremely small, and the temperature characteristic also depends only on this clock generator. You can do it. If a temperature compensated clock generator is used, higher accuracy can be obtained.

According to the second aspect of the present invention, the falling point can be specified, and the pulse can be shifted with high accuracy.

According to the third aspect of the present invention, in the conventional case using a counter that counts in one direction, the number of bits for counting from the start of the count operation of the counter to the fall is required. By switching the counting direction, the number of bits of the counter can be reduced by one bit and the number of bits of the counter can be reduced by one.

[Brief description of the drawings]

FIG. 1 is a waveform diagram for explaining an outline of a basic operation in a discharge lamp lighting control pulse generation device according to the present invention.

FIG. 2 is a block diagram showing a first embodiment of a discharge lamp lighting control pulse generation device according to the present invention.

FIG. 3 is a diagram showing a relationship between an analog value, an A / D conversion value of the A / D conversion circuit 2, and a pulse width.

FIG. 4 is a diagram showing the contents of FIG. 3 for one cycle of a pulse.

5A and 5B are diagrams showing a control area in association with bit contents, wherein FIG. 5A is a time chart corresponding to the contents of the upper three bits of the counter, and FIG. 5B is an extracted control area;
6 is a time chart corresponding to the contents of the upper 4 bits of the counter.

FIG. 6 is a block diagram showing a second embodiment of the discharge lamp lighting control pulse generation device according to the present invention.

FIG. 7 is a pulse 1 for explaining the operation of the second embodiment.
It is a figure showing a cycle.

FIG. 8 is a diagram showing a waveform of a signal generated in each section of a conventional analog pulse width modulation circuit.

[Explanation of symbols]

 2 A / D conversion circuit 3, 15 register 4 clock generator 5 counter 6, 16 comparator 7 to 11 AND circuit 12 OR circuit 13 hold circuit 14 output circuit

Claims (3)

[Claims] 1. A discharge lamp lighting control pulse generation device that generates a pulse signal having a predetermined width by defining a rising edge and a falling edge of a pulse using a timer circuit, wherein the timer circuit includes a clock signal having a predetermined period. , A counter for counting the clock signal, a first setting device for setting a value corresponding to the rising edge of the pulse using a predetermined number of bits, a count value of the counter and the first And a first comparator for comparing the set value of the first setter and outputting a signal defining a rising point when they match, the first setter sets a bit of a predetermined digit to positive or negative The remaining bits are used for comparison in the first comparison circuit, and the timer circuit determines whether the remaining bits are positive or negative at one of the positive and negative times according to the contents of the bits of the predetermined digit. A discharge lamp lighting control pulse generation device, comprising a determination circuit for outputting a threshold signal. 2. The method according to claim 1, wherein the timer circuit sets a value corresponding to a falling edge of the pulse using a predetermined number of bits.
And a second comparator circuit that compares the count value of the counter with the set value of the second setter, and outputs a signal that defines a falling time point when they match. 2. The discharge lamp lighting control pulse generator according to claim 1. 3. The discharge lamp lighting control pulse generation device according to claim 2, further comprising a switching circuit for alternately switching a counting operation by said counter between an up direction and a down direction.