JP2002084170A - Variable delay circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a variable delay circuit, capable of changing delay times over a wide range of time. SOLUTION: In a digital PLL circuit, a first variable delay circuit 4 has four delay unit circuits 22 to 25, each of which has at least two delay elements(DE) and two switches. A delay time of the delay circuit 4 can be changed at five stages by selectively setting on/off of switches SW1 to SW8. Since the output load will not increase, even if the number of the delay unit circuits 22 to 25 is increased, the delay times can be changed in the wire time range.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable delay circuit, and more particularly to a variable delay circuit having a plurality of stages of delay unit circuits, the delay time of which can be controlled in a plurality of stages.

[0002]

2. Description of the Related Art FIG. 13 shows a conventional digital PLL (Phas
3 is a block diagram illustrating a configuration of a variable delay circuit 80 included in an e Lock Loop (e Lock Loop) circuit. FIG. Such a variable delay circuit 80
Is disclosed in, for example, JP-A-11-0
No. 17531.

In FIG. 13, a variable delay circuit 80
Are the delay unit circuits 81 to 87 of seven stages and the inverter 8
8 is provided. Delay unit circuit 81 includes an input node N1, two output nodes N2 and N3, and a control node N4.
Each of delay unit circuits 82 to 87 includes an input node N1, two output nodes N2 and N3, and control nodes N4 and N5. The internal clock signal CLK is input to the input node N1 of the first-stage delay unit circuit 81. Delay unit circuit 81
Output nodes N3 to 86 are respectively connected to input nodes N1 of delay unit circuits 82 to 87 at the subsequent stage. Control nodes N4 of delay unit circuits 81-86 are connected to control nodes N5 of delay unit circuits 82-87 at the subsequent stage, respectively.
Select signals S1 to S7 are applied to nodes N4 of delay unit circuits 81 to 87, respectively. Delay unit circuits 81-8
7 are both connected to the input node of the inverter 88. The output signal of inverter 88 becomes output signal CLK 'of variable delay circuit 80.

The delay unit circuit 82 includes a delay element 91, inverters 92 and 93, an output fixing circuit 94 and an output circuit 98, as shown in FIG. Delay element 91 and inverters 92 and 93 are connected between input node N1 and node N6.
To delay the input signal by a predetermined delay time.

[0005] Output fixing circuit 94 includes a transmission gate 95, an N-channel MOS transistor 96 and an inverter 97. Transmission gate 95
Is connected between the node N6 and the output node N3.
N-channel MOS transistor 96 is connected to output node N3
And a line of ground potential GND. The selection signal S1 input via the node N5 is
The signal is directly input to the gate of the OS transistor 96 and the gate of the transmission gate 95 on the P-channel MOS transistor side, and is input to the gate of the transmission gate 95 on the N-channel MOS transistor side via the inverter 97.

When selection signal S1 is at "L" level, transmission gate 95 is turned on and N-channel MOS transistor 96 is turned off, and the signal input to node N1 is delayed by delay element 91, inverters 92, 9
3. Transmission gate 95 and output node N
3 to the delay unit circuit 83 at the next stage. When selection signal S1 is at "H" level, transmission gate 95 is turned off and N-channel MOS transistor 96 is turned on, and input node N1 of delay unit circuit 83 at the next stage is at "L" level via output node N3. (Ground potential GND).

Output circuit 98 includes P-channel MOS transistors 99 and 100 and N-channel MOS transistors 101 and 102 connected in series between a power supply potential VCC line and a ground potential GND line, and an inverter 1.
03 is included. The gates of MOS transistors 99 and 102 are connected to node N6. Signal S2 input via node N4 is input to the gate of P-channel MOS transistor 100 via inverter 103 and to the gate of N-channel MOS transistor 101. The drains of MOS transistors 100 and 101 become output node N2.

When selection signal S2 is at "L" level, MO
The S transistors 100 and 101 are turned on, and the output circuit 98
Operates as an inverter. When the selection signal S2 is at "H" level, the MOS transistors 100 and 101 are turned off, and the node N2 enters a floating state. Delay unit circuits 83 to 87 have the same configuration as delay unit circuit 82. The delay unit circuit 81 is obtained by omitting the output fixing circuit 94 of the delay unit circuit 82 and directly connecting the nodes N6 and N3.

Next, the operation of the digital PLL circuit including the variable delay circuit 80 will be described. This digital P
In the LL circuit, the external clock signal and the internal clock signal C
The phases of LK are compared, and when the phase of the internal clock signal CLK is behind the phase of the external clock signal, the selection signals S1 to S are set so that the delay time of the variable delay circuit is shortened.
7 is set, and when the phase of the internal clock signal CLK is ahead of the phase of the external clock signal, the selection signal S1 is set so that the delay time of the variable delay circuit 80 becomes longer.
To S7 are set.

For example, when only the selection signal S2 of the selection signals S1 to S7 is at "H" level, only the output circuit 98 of the delay unit circuit 82 is activated and the delay unit circuit 83 Output node N3 is fixed at "L" level, and internal clock signal CLK is delayed by delay unit circuits 81 and 82 and inverter 88 to become clock signal CLK '.

If the phase of the internal clock signal CLK is behind the phase of the external clock signal, the selection signal S2
, The selection signal S1 goes high, only the output circuit 98 of the delay unit circuit 81 is activated, the output node N3 of the delay unit circuit 82 is fixed at the low level, and the clock signal CLK Is delayed by delay unit circuit 81 and inverter 88 to generate clock signal CLK '.
Becomes As a result, the delay time of the variable delay circuit 80 is shortened, and the frequency of the internal clock signal CLK is increased.
The phase advances.

When the phase of the internal clock signal CLK is ahead of the phase of the external clock signal, the selection signal S2
, The selection signal S3 goes high, only the output circuit 98 of the delay unit circuit 83 is activated, the output node N3 of the delay unit circuit 84 is fixed at the low level, and the clock signal CLK Are the delay unit circuits 81 to
83 and the clock signal C delayed by the inverter 88
LK '. As a result, the delay time of the variable delay circuit 80 increases, the frequency of the internal clock signal CLK decreases, and the phase is delayed. Therefore, the internal clock signal C
LK and the phase of the external clock signal coincide.

[0013]

However, in the conventional variable delay circuit 80, since the output nodes N2 of the delay unit circuits 81 to 87 are commonly connected, the delay unit circuits 81 to 8 are not connected.
Increasing the number of nodes 7 increases the capacitance value of the node N2, causing a problem that the delay time per one delay unit circuit increases.

If the size of the MOS transistors 99 to 102 of the output circuits 98 of the delay unit circuits 81 to 87 is reduced, the capacitance value of the node N2 is reduced, but the current driving capability of the MOS transistors 99 to 102 is reduced. Time does not shorten.

Conversely, if the size of the MOS transistors 99 to 102 of the output circuits 98 of the delay unit circuits 81 to 87 is increased, the current driving capability of the MOS transistors 99 to 102 is increased, but the capacitance value of the node N2 is increased. Therefore, the delay time is not shortened.

Therefore, the conventional variable delay circuit 80 cannot change the delay time in a wide time range from a short time to a long time. Therefore, in the digital PLL circuit using such a variable delay circuit 80, the frequency cannot be changed in a wide frequency range from a low frequency to a high frequency.

As a method of changing the frequency range in a conventional analog PLL circuit, a VCO (Voltage Controlled Oscillato) is used depending on whether a metal wiring is cut or not.
r) how to change the number of stages in the inverter chain,
There is a method in which a plurality of VCOs having different frequency ranges are provided in advance and one of the VCOs is selectively used. However, the conventional method has a problem that the layout area increases and the power consumption increases.

Therefore, a main object of the present invention is to provide a variable delay circuit which can change a delay time in a wide time range, has a small layout area, and has low power consumption.

[0019]

A variable delay circuit according to the present invention is a variable delay circuit having a plurality of stages of delay unit circuits, the delay time of which can be controlled in a plurality of stages. A first delay element for delaying a signal input to one input node and providing the delayed signal to a first output node; and an output signal of the first delay element and a signal input to the second input node. The first for selecting one of the signals
And a second delay element for delaying the signal selected by the first switching circuit and providing the delayed signal to the second output node. The input signal of the variable delay circuit is input to the first input node of the first stage delay unit circuit. The first of each delay unit circuit
Is input to the first input node of the subsequent delay unit circuit. A second output node of each delay unit circuit is connected to a second input node of the preceding delay unit circuit. An output signal of the variable delay circuit is output from a second output node of the first delay unit circuit.

Preferably, each of the first and second delay elements includes an inverter. The first switching circuit has a first transmission gate having one terminal receiving an output signal of the first delay element, the other terminal connected to an input node of the second delay element, and one terminal connected to the first transmission gate. A second transmission gate connected to the second input node and the other terminal connected to the input node of the second delay element.

Preferably, the current driving capability of the inverter is controllable. Preferably, the delay unit circuit further includes a third delay element for delaying an output signal of the first delay element. The first switching circuit receives the output signal of the third delay element instead of the output signal of the first delay element, and outputs the output signal of the third delay element and the signal input to the second input node. Select one of the signals.

Preferably, the delay unit circuit further selectively supplies an output signal of the first delay element to one of the first output node and an input node of the third delay element. A second switching circuit is included.

Preferably, each of the first to third delay elements includes an inverter. The first switching circuit has one terminal receiving the output signal of the third delay element, the other terminal connected to the input node of the second delay element, a first transmission gate, and one terminal connected to the first transmission gate. And a second transmission gate having the other terminal connected to the input node of the second delay element. The second switching circuit has one terminal receiving the output signal of the first delay element, the other terminal connected to a third transmission gate connected to the first output node, and one terminal connected to the first delay node. The fourth terminal receives the output signal of the third delay element and has the other terminal connected to the input node of the third delay element.
Transmission gate.

Preferably, the current driving capability of the inverter is controllable. Also preferably, the delay unit circuit is further connected between the other terminal of the third transmission gate and the first or second logical potential line, and the third transmission gate becomes non-conductive. A first transistor that is turned on in response to the
And a second transistor that is connected between the other terminal of the transmission gate and the first or second logical potential line and that is turned on when the fourth transmission gate is turned off.

Preferably, the variable delay circuit is provided in an oscillator whose oscillation frequency can be controlled. The oscillator includes a feedback circuit for feeding back a signal output from a second output node of the first-stage delay unit circuit to a first input node of the first-stage delay unit circuit.

Preferably, the variable delay circuit is provided in a synchronous clock generation circuit for generating an internal clock signal in synchronization with an external clock signal. The synchronous clock generation circuit includes a phase comparator for comparing the phases of the external clock signal and the internal clock signal, and controlling the delay time of the variable delay circuit based on the comparison result.

[0027]

[First Embodiment] FIG. 1 is a circuit block diagram showing a configuration of a digital PLL circuit according to a first embodiment of the present invention. 1, this digital PLL circuit includes a phase comparator 1, a first control circuit 2, a second control circuit 3, a first variable delay circuit 4, a second variable delay circuit 5, and a clock stop circuit 6.

The phase comparator 1 receives an external clock signal RCL
K, the phases of the internal clock signal CLK and the external clock signal RCLK are compared based on the internal clock signal CLK and the signal φ5, and if the phase of the internal clock signal CLK is behind the external clock signal RCLK, the signal UP
1 and DOWN1 are set to "H" level and "L" level, respectively. When the phase of internal clock signal CLK is ahead of external clock signal RCLK, signals UP1 and D
OWN1 is set to “L” level and “H” level, respectively. Further, the phase comparator 1 receives the external clock signal RCL
Internal clock signal CLK in response to the rising edge of K
Is counted, and when the count value reaches a predetermined value (for example, 3), signal φ1 is set to “H” level, and internal clock signal CLK is fixed to “H” level.

The first control circuit 2 counts down by one in response to the signal UP1 attaining the "H" level, and counts up by one in response to the signal DOWN1 attaining the "H" level. And controls the delay time of the first variable delay circuit 4 based on the count value.
The first control circuit 2 sets the signals UP2 and DOWN2 to “H” when overflow occurs due to down-counting.
The signals UP2 and DOWN2 are set to the "L" level and the "H" level, respectively.

The second control circuit 3 counts down by one in response to the signal UP2 attaining the "H" level, and counts up by one in response to the signal DOWN2 attaining the "H" level. And controls the delay time of the second variable delay circuit 5 based on the count value.

First variable delay circuit 4 delays internal clock signal CLK to generate signal φ4. As shown in FIG. 2, the first variable delay circuit 4 includes delay elements 11 to 21 and switches SW1 to SW8. Delay elements 11 to 21
Specifically, as shown in FIG.
21 ', and the switches SW1 to SW8 are formed by transmission gates G1 to G8. Returning to FIG. 2, delay elements 11 and 12 and switches SW1 and SW2, delay elements 13 and 14 and switches SW3 and SW4, delay elements 15 and 16 and switches SW5 and SW6, and delay elements 17 to 20 and switches SW7 and SW8. Constitute delay unit circuits 22 to 25, respectively.

The internal clock signal CLK is input to the input node 22a of the first-stage delay unit circuit 22. Delay element 11, switch SW1, and delay element 12 are connected between input node 22a and output node 22b of delay unit circuit 22. The output signal of the delay unit circuit 22 is delayed by the delay element 21 and the output signal φ4 of the first variable delay circuit 4 is output.
Becomes

The delay element 13, the switch SW3 and the delay element 14 are connected in series between the input node 23a and the output node 23b of the delay unit circuit 23. Switch SW
2 is connected between the output node 23b of the delay unit circuit 23 and a node between the switch SW1 and the delay element 12.

The delay element 15, switch SW5 and delay element 16 are connected in series between the input node 24a and the output node 24b of the delay unit circuit 24. Switch SW
Reference numeral 6 is connected between the output node 25b of the delay unit circuit 25 and a node between the switch SW5 and the delay element 16. Delay elements 19 and 20 and switch SW8 are connected to a node between delay element 17 and switch SW7 and switch S.
It is connected in series between W7 and a node between the delay elements 18. The switches SW1 to SW8 are controlled by the first control circuit 2. The first variable delay circuit 4 has five states 1 to 5 as shown in Table 1.

[0035]

[Table 1]

In the state 1, the switch SW1 turns on and the switch SW2 turns off. Other switches SW3 to SW8
ON / OFF is optional. In this state 1, the internal clock signal CLK is input to the second variable delay circuit 5 via the delay element 11, the switch SW1, and the delay elements 12, 21. In this state 1, the delay time of the first variable delay circuit 4 is the shortest.

In the state 2, the switches SW1 and SW4 are turned off, and the switches SW2 and SW3 are turned on. ON / OFF of the other switches SW5 to SW8 is optional. In this state 2, the internal clock signal CLK is applied to the delay elements 11, 1
3, the switch SW3, the delay element 14, the switch SW2 and the delay elements 12 and 21 are input to the second variable delay circuit 5. In the state 2, the delay time of the first variable delay circuit 4 is longer than that in the state 1 by the delay elements 13 and 14 and the switch SW2. Note that the delay time of the switch SW3 is offset by the delay time of the switch SW1.

In state 3, the switches SW1, SW3, S
W6 turns off, and switches SW2, SW4, and SW5 turn on. ON / OFF of the other switches SW7 and SW8 is arbitrary. In this state 3, the internal clock signal CLK is
Delay elements 11, 13, 15, switch SW5, delay element 16, switch SW4, delay element 14, switch SW2
And second variable delay circuit 5 via delay elements 12 and 21
Is input to In the state 3, the delay time of the first variable delay circuit 4 is longer than that in the state 2 by the delay elements 15, 16 and the switch SW4.

In state 4, switches SW1, SW3, S
W5 and SW8 are turned off and switches SW2, SW4 and SW
6, SW7 is turned on. In this state 4, the internal clock signal CLK is output to the delay elements 11, 13, 15, and 17, the switch SW7, the delay element 18, the switch SW6, the delay element 16, the switch SW4, the delay element 14, and the switch SW2.
And second variable delay circuit 5 via delay elements 12 and 21
Is input to In the state 4, the delay time of the first variable delay circuit 4 is longer than that in the state 3 by the delay elements 17, 18 and the switch SW6.

In state 5, switches SW1, SW3, S
W5 and SW7 are turned off and switches SW2, SW4 and SW
6, SW8 is turned on. In this state 5, the internal clock signal CLK is applied to the delay elements 11, 13, 15, 17, 1
9, 20, switch SW8, delay element 18, switch S
W6, delay element 16, switch SW4, delay element 14,
The second through the switch SW2 and the delay elements 12 and 21
The signal is input to the variable delay circuit 5. In this state 5, the delay time of the first variable delay circuit 4 is longer than that of the state 4 by the delay element 1
It is longer by 9,20.

Each of the signals UP1 and DOWN1 is "H".
Each time the level and the “L” level are reached, the state number is 1
Only smaller. That is, the states 2 to 5 change to the states 1 to 4. Thereby, the delay time of the first variable delay circuit 4 is shortened, and the frequency of the internal clock signal CLK is increased. In state 1, the signals UP1 and DOWN1 are each at “H”.
When the level becomes the "L" level, the state returns to the state 5, and the signals UP2 and DOWN2 become the "H" level and the "L" level, respectively.

Each of the signals UP1 and DOWN1 is "L".
Each time the level and the “H” level are reached, the state number is 1
Just get bigger. That is, states 1-4 change to states 2-5. As a result, the delay time of the first variable delay circuit 4 increases, and the frequency of the internal clock signal CLK decreases. In state 5, the signals UP1 and DOWN1 are each "L".
When the level becomes the “H” level, the state returns to the state 1, and the signals UP2 and DOWN2 become the “L” level and the “H” level, respectively.

Returning to FIG. 1, the second variable delay circuit 5 delays the output signal φ4 of the first variable delay
Generate The second variable delay circuit 5 basically includes the first
The configuration is the same as that of the variable delay circuit 4. However, the switches SW1 to SW8 of the second variable delay circuit 5 are connected to the second control circuit 3
Is controlled by The delay time of the delay elements 11 to 21 of the second variable delay circuit 5 is four times that of the delay elements 11 to 21 of the first variable delay circuit 4. The output signal φ5 of the second variable delay circuit 5 is input to the phase comparator 1 and the clock stop circuit 6.

Clock stop circuit 6 includes a transmission gate 7, an N-channel MOS transistor 8, and inverters 9 and 10. Transmission gate 7
And inverter 10 are connected in series between input node 6a and output node 6b of clock stop circuit 6. The output signal of inverter 10 becomes internal clock signal CLK. N-channel MOS transistor 8 is connected to inverter 1
0 and the ground potential GND line. Signal φ1 is output from N-channel MOS transistor 8
Of the transmission gate 7 and the gate of the transmission gate 7 on the side of the P-channel MOS transistor, as well as via the inverter 9 to the gate of the transmission gate 7 on the side of the N-channel MOS transistor.

When signal φ1 is at "H" level, transmission gate 7 is turned off and N channel M
The OS transistor 8 is turned on and the internal clock signal CLK
Are fixed at the “H” level.

When signal φ1 is at "L" level, transmission gate 7 is turned on and N channel M
The OS transistor 8 is turned off, and the first variable delay circuit 4, the second variable delay circuit 5, the transmission gate 7, and the inverter 10 are connected in a ring to form a ring oscillator. This ring oscillator oscillates at a frequency corresponding to the delay time of the first variable delay circuit 4 and the second variable delay circuit 5, and generates an internal clock signal CLK.

Next, the operation of the digital PLL circuit will be described. In the initial state, the total delay time of the first variable delay circuit 4 and the second variable delay circuit 5 is sufficiently small, and the frequency of the internal clock signal CLK is sufficiently higher than the frequency of the external clock signal RCLK. Shall be.

The phase comparator 1 receives the external clock signal RCL
Internal clock signal CLK in response to the rising edge of K
, The signal φ1 is set to the “H” level and the internal clock signal CLK is fixed at the “H” level in response to the count value reaching a predetermined value (here, 3). I do. In this state, the phase comparator 1 itself determines that the phase of the internal clock signal CLK is ahead of the phase of the external clock signal RCLK. Therefore, signals UP1 and DOWN1 become "L" level and "H" level, respectively. As a result, the count value of the first control circuit 2 is incremented by one, the state of the first variable delay circuit 4 changes from 1 to 2, and the first variable delay circuit 4 and the second
The total delay time of the variable delay circuit 5 increases, and the frequency of the internal clock signal CLK decreases.

When the signals UP1 and DOWN1 go to the "L" level and "H" level respectively when the first variable delay circuit 4 is in the state 5, the first variable delay circuit 4 goes into the state 1 and the signals UP2 and DOWN2 are changed to the state 1. Each "L"
Level and “H” level, and the second variable delay circuit 5
Changes from state 1 to state 2. Thus, the frequency of the internal clock signal CLK is
When the frequency becomes three times the frequency of K, the signals UP1, DO
WN1 both attain an "L" level, and this PLL circuit enters a locked state.

If the phase of internal clock signal CLK lags behind the phase of external clock signal RCLK for some reason, signals UP1 and DOWN1 become "H" level and "L" level, respectively, and count value of first control circuit 2 And the total delay time of the first variable delay circuit 4 and the second variable delay circuit 5 is shortened to reduce the internal clock signal CLK.
Frequency rises. Therefore, the internal clock signal C
The phase of LK and the phase of external clock signal RCLK are kept in agreement.

In the first embodiment, the delay unit circuit 23
Since the output load does not change even if the number of the delay unit circuits 81 to 87 is increased, it is possible to operate at a higher frequency as compared with the conventional case where the output load increases.
The frequency range can be widened. Also, the power consumption is small.

Further, since the output load of each of the delay elements 11 to 21 can be made constant, the delay elements 11 to 21
Can be made constant, and can be arranged regularly. Therefore, the layout efficiency is increased, and the layout area can be reduced.

In the first embodiment, four delay unit circuits 23 to 26 are provided, but it goes without saying that the number of delay unit circuits is arbitrary.

The delay elements 11 to 21 are each composed of one stage of inverters 11 'to 21', but may be composed of two or more stages of inverters.

Hereinafter, a modification of the first embodiment will be described. In the modification of FIG. 4, delay elements 31 to 35 are added to the first variable delay circuit 4 of FIG. Delay elements 31 to
35 is a delay element 11, 13, 15, 17, 2
0 and switches SW1, SW3, SW5, SW7, SW8
Connected between As shown in FIG. 5, delay elements 31-35 are each formed of, for example, inverters 31'-35 '. In this modified example, since the delay elements 31 to 35 are provided, the input-side delay elements 11, 13, 15, 1
It is possible to reduce the output load of 7, 20. In this modification, the delay elements 11, 13, 15, 17, 20
And the switches SW1, SW3, SW5, SW7, SW8 are provided with one-stage delay elements 31 to 35, respectively.
Two or more stages may be provided.

In the modification of FIG. 6, switches SW11 to SW18 are added to the first delay circuit of FIG. Switch S
W11 to SW18 are delay elements 11, 31 and 1 respectively.
1 and 13, 13 and 32, 13 and 15, 15 and 33, 15
, 17, 17 and 34, 17 and 19 are connected. The switches SW11 to SW18 are respectively connected to the switches SW1 to SW18.
The operation is the same as that of SW8. For example, in state 1, the switches SW1 and SW11 are turned on, and the switches SW2 and SW11 are turned on.
12 turns off. Thereby, the delay elements 11, 31, 1
2, 21 operate, and unnecessary delay elements 13 to 20, 3
Since 2 to 35 do not operate, power consumption can be reduced.

In the modification of FIG. 7, the delay elements 11 to 21, 31 to 35 of the first variable delay circuit of FIG. 6 are constituted by inverters 11 'to 21', 31 'to 35', respectively, and switches SW1 to SW1 SW8, SW11 to SW18 are connected to transmission gates G1 to G8, G11 to G11, respectively.
G18, and an N-channel MOS transistor QN1
To QN8. N channel MOS transistors QN1 to QN8 are connected to inverter 3
1 ', 13', 32 ', 15', 33 ', 17', 3
The gates are connected between the input nodes 4 'and 19' and the line of the ground potential GND, and the respective gates are connected to the gates of the transmission gates G11 to G18 on the P-channel MOS transistor side.

Therefore, the transmission gate G
When 11 to G18 are turned off, N channels M
OS transistors QN1 to QN8 are turned on, and inverters 31 ', 13', 32 ', 15', 33 ', 17', 3
4 'and 19' are at "L" level (ground potential G
ND). Therefore, an inverter unnecessary for operation in each of states 1 to 5 (for example, 1 in state 1)
Since the output signal of 3 ') can be fixed at the "H" level, the circuit operation can be stabilized. Further, for example, in state 1, if the transmission gates G3 to G8 and G13 to G18, which are turned on / off arbitrarily (*), are turned on, the output signals of the inverters 13 'to 20' and 32 'to 35' are changed to " Since it can be fixed to the “H” level or the “L” level, the circuit operation can be further stabilized.

In the modification of FIG. 8, the N-channel MOS transistors QN1 to QN8 of the modification of FIG.
It is replaced by S transistors QP1 to QP8.
P channel MOS transistors QP1-QP8 are connected to inverters 31 ', 13', 32 ', 15', 3 respectively.
3 ', 17', 34 'and 19' are connected between the input nodes and the line of the power supply potential VCC, and each gate is connected to the N-channel MO of the transmission gates G11 to G18.
Connected to the gate on the S transistor side. Therefore,
When transmission gates G11-G18 are turned off, P-channel MOS transistors QN1-QN1, respectively.
QN8 turns on, and inverters 31 ', 13', 32 ',
Input nodes 15 ', 33', 17 ', 34', and 19 'are fixed at "H" level (power supply potential VCC). Therefore, in each of states 1 to 5, the output signal of an inverter unnecessary for operation (for example, 13 'in state 1) becomes "L".
Since the level can be fixed to the level, the circuit operation can be stabilized. Further, for example, in the state 1, the gates G3 to G8 and G13 to G1 whose on / off are arbitrary (*)
8, the inverters 13 'to 20' and 32 'to
Since the output signal of 35 'can be fixed at "L" level or "H" level, the circuit operation can be further stabilized.

[Second Embodiment] FIG. 9 is a block diagram showing a configuration of an analog PLL circuit according to a second embodiment of the present invention. 9, the analog PLL circuit includes a phase comparator 41, a charge pump 42, a loop filter 43, a VCO 44, and a frequency divider 45.

The phase comparator 41 receives the external clock signal RC
LK and the phase of the feedback clock signal FCLK are compared. If the phase of the feedback clock signal FCLK is behind the phase of the external clock signal RCLK, the signals UP and DOWN are set to the “H” level and the “L” level, respectively. Feedback clock signal FCL
When the phase of K is ahead of the phase of external clock signal RCLK, signals UP and DOWN are set to "L" level and "H" level, respectively. Further, the phase comparator 41
Detects the frequency of the external clock signal RCLK, and sets the states 1 to 5 of the VCO 44 based on the detection result.

The charge pump 42 outputs signals UP and DOW.
A current is supplied to the loop filter 43 in response to N going to the “H” level and “L” level, respectively, and in response to the signals UP and DOWN going to the “L” level and “H” level, respectively. The current is caused to flow out of the loop filter 43.

Loop filter 43 includes a resistance element and a capacitor connected in series between a predetermined node and a ground potential GND line, integrates current from charge pump 42 to generate control voltage VC, and generates a control voltage VC to VCO 44. give.

VCO 44 includes a ring oscillator 50. As shown in FIG. 10, ring oscillator 50 replaces inverters 11 ′ to 21 ′ of first variable delay circuit 4 of FIG. 3 with gated inverters 51 to 61, respectively, and outputs the output node of gated inverter 61 and gated inverter 51. It is connected to an input node. The output clock signal of gated inverter 61 becomes internal clock signal CLK.

As shown in FIG. 11, gated inverter 51 includes P-channel MOS transistors 62 and 63 and N-channel MOS transistors 64 and 65 connected in series between a power supply potential VCC line and a ground potential GND line. Including. The gates of MOS transistors 63 and 64 become input node 51a, and MOS transistor 6
The drains 3 and 64 become output nodes 51b. MOS
The gates of transistors 62 and 65 receive bias potentials VL and VH, respectively. VCC-VL, VH-GND
Becomes larger, the current driving capability of the gated inverter 51 becomes larger, the delay time becomes shorter, and VCC-V
As L, VH-GND decreases, the current driving capability of gated inverter 51 decreases and the delay time increases. Other gated inverters 52 to 61 have the same configuration as gated inverter 51.

FIG. 12 is a circuit diagram showing a configuration of the bias potential generating circuit 70. In FIG. 12, the bias potential generating circuit 70 includes a P-channel MOS transistor 7
1, 72, N-channel MOS transistors 73 and 74, and a resistance element 75 are provided in the VCO 44.
MOS transistors 71 and 73 and a resistance element 75;
MOS transistors 72 and 74 are connected in series between the line of power supply potential VCC and the line of ground potential GND, respectively. The gate of N-channel MOS transistor 73 receives control voltage VC. The gates of P channel MOS transistors 71 and 72 are both P channel MOS.
Connected to the drain of transistor 71. P-channel MOS transistors 71 and 72 form a current mirror circuit. The gate of N-channel MOS transistor 74 is connected to its drain. The gate potential of P channel MOS transistors 71 and 72 is set to bias potential VL
And the gate potential of the N-channel MOS transistor 74 becomes the bias potential VH.

The N-channel MOS transistor 73 includes:
A current of a level corresponding to the control voltage VC flows. N channel MOS transistor 73 and P channel MOS transistor 71 are connected in series, P channel MOS transistors 71 and 72 form a current mirror circuit, and P channel MOS transistor 72 and N channel MOS transistor 74 are connected in series. A current of a level corresponding to the control voltage VC flows through the MOS transistors 71 to 74. When the control voltage VC increases, the current flowing through the MOS transistors 72 and 74 increases, the current flowing through the MOS transistors 62 and 65 in FIG. 11 also increases, and the delay time of the gated inverters 51 to 61 decreases. When the control voltage VC decreases, the current flowing through the MOS transistors 72 and 74 decreases, and the MOS transistors 62 and 6 in FIG.
5 also decreases and the gated inverters 51-
61, the delay time becomes longer.

The transmission gates G1 to G8 are
It is controlled by the phase comparator 41. By turning on / off the transmission gates G1 to G8 (switches SW1 to SW8), the ring oscillator 50 takes five states 1 to 5 as shown in Table 1. In the case of state 1,
Three gated inverters 51, 52, 61 are connected in a ring. In the case of states 2 to 5, five gated inverters 51, 53, 54, 52, 61, respectively,
The seven gated inverters 51, 53, 55, 56,
54, 52, 61, 9 gated inverters 51,
53, 55, 57, 58, 56, 54, 52, 61, 1
1 gated inverter 51, 53, 55, 57, 5
9, 60, 58, 56, 54, 52 and 61 are connected in a ring shape. Therefore, the oscillation frequency of the ring oscillator 50 becomes highest in the state 1 and becomes lowest in the state 5. In each of States 1 to 5, the higher the control voltage VC, the higher the oscillation frequency of ring oscillator 50.

Returning to FIG. 9, frequency divider 45 divides internal clock signal CLK by N (where N is an integer of 2 or more) to generate feedback clock signal FCLK and provides it to phase comparator 41. . Feedback clock signal FCLK has a frequency 1 / N times that of internal clock signal CLK. Since control voltage VC is controlled such that the frequency and phase of feedback clock signal FCLK and external clock signal RCLK match, the frequency of internal clock signal CLK is N times the frequency of external clock signal RCLK.

Next, the operation of the analog PLL circuit will be described. When the external clock signal RCLK is input, the phase comparator 41 outputs the external clock signal RCLK.
Is detected, and based on the detection result, VCO4
The transmission gates G1 to G8 of the ring oscillator 50 of No. 4 are controlled, and the ring oscillator 50 is in the state 1
5 is set. For example, when set to state 1, three gated inverters 51, 52, and 61 are connected in a ring and oscillate. The output clock signal CLK of the ring oscillator 50 is frequency-divided by N in the frequency divider 45 and fed back to the phase comparator 41.

When the phase of feedback clock signal FCLK lags behind the phase of external clock signal RCLK, signals UP and DOWN become "H" level and "L" level, respectively, and charge pump 42 transfers the signal to loop filter 43. The current is supplied, and the control voltage VC increases. As a result, VCC-VL and VH-GND increase, the delay time of gated inverters 51 to 61 decreases, and the frequencies of clock signals CLK and FCLK increase.

Conversely, the feedback clock signal FCL
When the phase of K is ahead of the phase of external clock signal RCLK, signals UP and DOWN become "L" level and "H" level, respectively, and current flows out of loop filter 43 to charge pump 42, and control is performed. Voltage VC decreases. As a result, VCC-VL and VH-GND decrease, the delay time of gated inverters 51 to 61 increases, and the frequencies of clock signals CLK and FCLK decrease. Therefore, the frequency and phase of external clock signal RCLK and feedback clock signal FCLK match, and internal clock signal CLK is a clock signal obtained by dividing external clock signal RCLK by 1 / N.

In the second embodiment, the same effect as in the first embodiment can be obtained, and the frequency range can be changed by one VCO 44. Therefore, the layout area can be smaller than that in the conventional case where a plurality of VCOs are provided. .

In the second embodiment, the first of FIG.
Although the ring oscillator 50 is configured by modifying the variable delay circuit 4, the ring oscillator 50 may be configured by modifying the first variable delay circuit illustrated in FIGS. 2 and 4 to 8.

The embodiments disclosed this time are illustrative in all aspects and are not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0076]

As described above, in the variable delay circuit according to the present invention, each delay unit circuit delays the signal input to the first input node and provides the delayed signal to the first output node.
, A first switching circuit for selecting any one of an output signal of the first delay element and a signal input to the second input node, and a first switching circuit And a second delay element for delaying the signal selected in (1) and providing the delayed signal to a second output node. An input signal of the variable delay circuit is input to a first input node of the first delay unit circuit, and a first output node of each delay unit circuit is connected to a first input node of the subsequent delay unit circuit. Second delay unit circuit
Is connected to the second input node of the preceding delay unit circuit, and the output signal of the variable delay circuit is output from the second output node of the first delay unit circuit. Therefore,
Since the output load does not change even if the number of delay unit circuits is increased, the delay time can be changed over a wider time range and the power consumption can be changed as compared with the conventional case where the output load increases when the number of delay unit circuits is increased. Can be small. Further, since the size of the first and second delay elements can be made constant and can be arranged regularly, the layout efficiency is increased and the layout area can be reduced.

[0077] Preferably, each of the first and second delay elements includes an inverter, and the first switching circuit includes first and second transmission gates. In this case, the first and second delay elements and the first switching circuit can be easily configured.

Preferably, the current driving capability of the inverter is controllable. In this case, the delay times of the first and second delay elements can be changed continuously.

Preferably, the delay unit circuit further includes a third delay element for delaying an output signal of the first delay element, and the first switching circuit includes an output signal of the third delay element and a second delay element. One of the signals input to the input node is selected. In this case, the output load of the first delay element can be reduced by the third delay element.

Preferably, the delay unit circuit is configured to selectively apply the output signal of the first delay element to one of the first output node and the input node of the third delay element. Is further included. in this case,
Unnecessary first and third delay elements can be prevented from operating, and power consumption can be reduced.

Preferably, each of the first to third delay elements includes an inverter, the first switching circuit includes first and second transmission gates, and the second switching circuit includes third and fourth transmission gates. Transmission gate. In this case, the first to third delay elements and the first and second switching circuits can be easily configured.

Preferably, the current drive capability of the inverter is controllable. In this case, the delay times of the first to third delay elements can be continuously changed.

Preferably, the delay unit circuit further includes the other terminal of the third transmission gate and the first terminal.
Alternatively, the third logic potential line is connected between the third logic potential line and the third logic potential line.
A fourth transistor connected between the other terminal of the fourth transmission gate and the first or second logical potential line, the first transistor being turned on in response to the transmission gate becoming non-conductive; A second transistor that becomes conductive in response to the transmission gate becoming non-conductive. In this case, the input levels of the unnecessary first and third delay elements can be fixed at the first or second logic potential, and the circuit operation can be stabilized.

Preferably, the variable delay circuit is provided in an oscillator whose oscillation frequency can be controlled.
A feedback circuit is included for feeding back a signal output from a second output node of the first-stage delay unit circuit to a first input node of the first-stage delay unit circuit. In this case, the oscillation frequency of the oscillator can be changed in a wide frequency range.

Preferably, the variable delay circuit is provided in a synchronous clock generating circuit for generating an internal clock signal in synchronization with the external clock signal, and the synchronous clock generating circuit is configured to control the phase of the external clock signal and the phase of the internal clock signal. And a phase comparator for controlling the delay time of the variable delay circuit based on the comparison result. in this case,
The frequency of the internal clock signal can be changed in a wide frequency range.

[Brief description of the drawings]

FIG. 1 is a digital PL according to a first embodiment of the present invention.
FIG. 3 is a circuit block diagram illustrating a configuration of an L circuit.

FIG. 2 is a circuit block diagram showing a configuration of a first variable delay circuit shown in FIG.

FIG. 3 is a circuit diagram specifically showing a configuration of a first variable delay circuit shown in FIG. 2;

FIG. 4 is a circuit block diagram showing a modification of the first embodiment.

FIG. 5 is a circuit diagram specifically showing a configuration of a modification shown in FIG. 4;

FIG. 6 is a circuit block diagram showing another modification of the first embodiment.

FIG. 7 is a circuit diagram showing still another modification of the first embodiment.

FIG. 8 is a circuit diagram showing still another modification of the first embodiment.

FIG. 9 shows an analog PL according to a second embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of an L circuit.

FIG. 10 is a circuit diagram showing a configuration of a ring oscillator included in the VCO shown in FIG.

11 is a circuit diagram showing a configuration of the gated inverter shown in FIG.

FIG. 12 is a circuit diagram showing a configuration of a bias potential generating circuit included in the VCO shown in FIG.

FIG. 13 is a circuit block diagram showing a configuration of a variable delay circuit included in a conventional digital PLL circuit.

14 is a circuit block diagram illustrating a configuration of a delay unit circuit illustrated in FIG.

[Explanation of symbols]

1, 41 phase comparator, 2 first control circuit, 3 second control circuit, 4 first variable delay circuit, 5 second variable delay circuit, 6 clock stop circuit, 7, G1 to G8, G11 to
G18,95 Transmission gate, 8, QN1
QN8, 64, 65, 73, 74, 96 N-channel MOS transistors, 9, 10, 11 'to 21', 2
6'-30 ', 88,92,93,97,103 Inverter, 11-21,26-30,91 Delay element, 2
2 to 25, 81 to 87 delay unit circuit, SW1 to SW
8, SW11 to SW18 switches, QP1 to QP8,
61, 62, 71, 72, 99, 100 P channel M
OS transistor, 42 charge pump, 43 loop filter, 44 VCO, 45 divider, 50 ring oscillator, 51 to 61 gated inverter, 7
0 bias potential generation circuit, 80 variable delay circuit, 94
Output fixing circuit, 98 output circuit.

Claims (10)

[Claims] 1. A variable delay circuit having a plurality of stages of delay unit circuits, the delay time of which can be controlled in a plurality of stages, wherein the delay unit circuit delays a signal input to a first input node. A first delay element applied to a first output node, and a first signal for selecting one of an output signal of the first delay element and a signal input to a second input node. And a second delay element for delaying the signal selected by the first switching circuit and providing the delayed signal to a second output node, wherein the first input node of the first stage delay unit circuit has the variable An input signal of the delay circuit is input, a first output node of each delay unit circuit is connected to a first input node of a subsequent delay unit circuit, and a second output node of each delay unit circuit is connected to a preceding delay unit Connected to a second input node of the circuit, A variable delay circuit, wherein an output signal of the variable delay circuit is output from a second output node of a first-stage delay unit circuit. 2. The first and second delay elements each include an inverter, the first switching circuit has one terminal receiving an output signal of the first delay element,
A first transmission gate having the other terminal connected to the input node of the second delay element, and one terminal connected to the second input node, and the other terminal connected to the input of the second delay element; The second connected to the node
The variable delay circuit according to claim 1, further comprising: 3. The variable delay circuit according to claim 2, wherein the current drive capability of said inverter is controllable. 4. The delay unit circuit further includes a third delay element for delaying an output signal of a first delay element, wherein the first switching circuit is configured to output a signal of the first delay element. Alternatively, receiving the output signal of the third delay element and selecting one of the output signal of the third delay element and the signal input to the second input node. 2. The variable delay circuit according to 1. 5. The delay unit circuit according to claim 1, further comprising:
5. A second switching circuit for selectively providing an output signal of the first delay element to one of the first output node and an input node of the third delay element.
3. The variable delay circuit according to claim 1. 6. The first to third delay elements each include an inverter, and the first switching circuit has one terminal receiving an output signal of the third delay element,
A first transmission gate having the other terminal connected to the input node of the second delay element, one terminal of which is input to the second input node, and the other terminal connected to the input of the second delay element The second connected to the node
The second switching circuit has one terminal receiving an output signal of the first delay element,
A third terminal whose other terminal is connected to the first output node;
6. The transmission gate of claim 5, further comprising a fourth transmission gate having one terminal receiving the output signal of the first delay element and the other terminal connected to an input node of the third delay element. A variable delay circuit as described. 7. The variable delay circuit according to claim 6, wherein a current driving capability of said inverter is controllable. 8. The delay unit circuit further includes:
A first transistor connected between the other terminal of the transmission gate and a line of the first or second logic potential, which is turned on when the third transmission gate is turned off; and A second transistor connected between the other terminal of the fourth transmission gate and the line of the first or second logic potential, the second transistor being turned on when the fourth transmission gate is turned off, The variable delay circuit according to claim 6. 9. The variable delay circuit is provided in an oscillator whose oscillation frequency can be controlled, and the oscillator converts a signal output from a second output node of the first-stage delay unit circuit to the first-stage delay unit circuit. 1st unit circuit
9. The variable delay circuit according to claim 1, further comprising a feedback circuit for feeding back to an input node of the variable delay circuit. 10. The variable delay circuit is provided in a synchronous clock generation circuit for generating an internal clock signal in synchronization with an external clock signal, wherein the synchronous clock generation circuit includes the external clock signal and the internal clock signal. 9. The variable delay circuit according to claim 1, further comprising: a phase comparator for comparing the phases of the variable delay circuits and controlling a delay time of the variable delay circuit based on a comparison result.