JP2001111399A - Output circuit for capacitor charging/discharging and timer/reset circuit using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an output circuit for capacitor charging/discharging in which the bias currents and saturated voltage of an output circuit in a Darlington constitution can be reduced and a timer circuit and a reset circuit using the output circuit. SOLUTION: This output circuit for capacity charging/discharging is provided with a capacitor 5, Darlington output circuits 27 and 29 for instantaneously charging or discharging large currents from the capacitor, and a low saturated output circuit connected in parallel with the Darlington output circuit for charging or discharging a charge of the capacitor until the saturated voltage of a single transistor. In this case, the low saturated output circuit is constituted of the single transistor 36 or a fixed current circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit for charging / discharging a capacitor, and more particularly to an output circuit for charging / discharging a capacitor in which a bias current and a saturation voltage of an output circuit having a Darlington configuration are reduced, and a timer circuit using the same. It relates to a reset circuit.

[0002]

2. Description of the Related Art FIG. 1 shows a configuration example of a power-on reset circuit 1 provided with a low-voltage reset circuit and a runaway detection reset circuit (watchdog circuit) in a microcomputer circuit or the like. 2 and 3 show FIG.
5 shows an example of an operation waveform of a main part of the circuit of FIG. Here, the operation of the entire circuit of FIG. 1 will be briefly described in relation to the present invention.

In the example shown in FIG. 1, the power-on reset circuit 1 is realized by an analog IC, and the reset time is obtained by charging / discharging time of an externally attached large-capacity capacitor 5. First, the watchdog operation will be described with reference to FIG. A microcomputer (not shown) supplies a watchdog clock (WD) indicating the normal operation of the microcomputer.
C) is always input (). In the differential signal passing through the external differentiating circuit (), the excessive signal level portion is clamped by the clamp circuit 2 and input to the window comparator 3.

The window comparator 3 has two thresholds, plus and minus, with respect to an input reference voltage obtained by resistance division, and outputs a differential signal portion exceeding each of the thresholds to a pulse signal of a ground-power supply voltage (V _DD ). (). The switch 22 is turned on by the pulse signal,
Thereby, the capacitor 5 is periodically charged, and the constant current source 6 is not charged except for the charging period (the period when the switch 22 is on).
Switch 23 which is normally ON (other than the reset period)
Gradually discharge through ().

As a result, during normal operation of the microcomputer, the negative output of the capacitor 5 does not exceed the threshold voltage (Vth0) of the comparator 8, and the reset output (RESET) maintains a high level ().
FIG. 3 also shows an operation example when the input of the watchdog clock is interrupted due to the occurrence of a failure in the microcomputer circuit or the like. In this case, the discharge by the constant current source 6 proceeds to reach the threshold voltage.

As a result, the output of the comparator 8 is inverted, and the reset signal (RESET) goes low. Further, the switch 25 is turned on by the inverted signal, and the resistors 15 and 16 are connected in parallel, whereby the threshold potential decreases by a predetermined level. At the same time, when the switch 23 is turned off and the switch 24 is turned on, the constant current source 6
, The charging by the constant current source 7 is started.

When the charging potential reaches the lowered threshold potential, the output of the comparator 8 is inverted again to return the reset signal to a high level. At the same time, the threshold potential is restored to the original level. In this way, a reset signal having a predetermined time width is output (and) based on the switching between charging and discharging and the threshold potential having the hysteresis (Schmitt) characteristic.

Next, the low voltage reset operation will be described with reference to FIG. The comparator 4 outputs the threshold potential (V.sub.V) of the reference power supply 13 created using the diode characteristics and the like.
th1) and the power supply voltage (V _DD ) by the resistors 11 and 12
Then, when the potential of the resistance bleeder falls below the threshold potential, the switch 21 is turned on to discharge the capacitor 5 (). As a result, the negative potential of the capacitor 5 instantaneously exceeds the threshold voltage (Vth0) of the comparator 8 described above, and at the same time, the reset signal (R
ESET) is output (and). Note that a Schmitt type comparator is used for the comparator 4 in order to improve a noise margin.

[0009]

FIGS. 4 and 5 show an example of the configuration of a conventional switch 21. FIG. FIG. 4 shows an example of the simplest configuration using one transistor switch 27. When the output of the comparator 4 changes to a high level due to a decrease in the power supply voltage (V _DD ), the switch drive transistor 28 is turned on, and the PNP transistor 27 is also turned on by the on current (I ₁ ). As a result, the potential at both ends of the capacitor 5 is short-circuited by the power supply voltage (V _DD ) via the turned-on transistor 27.

The circuit configuration of FIG. 4 has the advantage that it is simple and requires a small number of elements. However, in this configuration, even after the discharge of the capacitor 5 is completed, the bias current (I ₁ ) in millimeters continues to flow while the transistor 28 is on, so that the discharge operation needs to be completed instantaneously by the transistor 27, so that the current can be reduced. There was a limit. That is, this configuration has a problem in that when the current capability is reduced, the time until the reset output is delayed, while when the current output is large, the current consumption increases accordingly.

FIG. 5 shows an example in which the transistor switch has a Darlington configuration using transistors 27 and 29 to solve the above problem. The bias current (I ₂ ) in this case is 1 / h _fe compared to FIG.
Clearly, the effect of reducing current consumption can be expected. However, in the case of the Darlington configuration, the saturation voltage between the collector and the emitter of the transistor 29 in the input stage is about 0.1.
V, and the base-emitter voltage of the transistor 27 in the output stage is about 0.7 V, and the ON voltage of the switch 21 is as large as about 0.8 V.

This is because, as shown in FIG. 3, the saturation voltage (V _sat ) of the switch 21 is determined based on the power supply voltage (V _DD ) in the case of the low voltage reset operation.
= Approximately 0.8 V), and the capacitor 5 is charged to a potential that has dropped by about 0.8 V. For example, when the voltage reduction phenomenon is instantaneously recovered, the charging operation by the constant current source 7 is started from the potential (V _DD −V _sat ). Be started. On the other hand, in the case of the power-on reset operation, the operation immediately returns to the power supply under-voltage recovery operation. At this time, the capacitor 5 is completely charged (V _sat = 0).
_{Therefore, the} charging operation by the constant current source 7 starts from the power supply voltage (V _DD ).

As is apparent from the operation shown in FIG. 2, the time width of the reset signal due to the reduced voltage reset operation is greatly different from the time width of the reset signal due to the power-on reset operation. The former is smaller and the latter is larger. Become. As a result, at the time of reset due to reduced voltage, the charge of the capacitor is changed to the same state as when the power is turned on (at least
Unless the voltage is set to about 0.1 V as in the conventional example of FIG. 4, resetting does not work properly.

In view of the above problems, an object of the present invention is to reduce the bias current for controlling the charge / discharge of the capacitor and reduce the saturation voltage of the switch for controlling the charge / discharge of the capacitor. An object of the present invention is to provide an output circuit for discharge / discharge, and a timer circuit and a reset circuit using the same.

[0015]

According to the present invention, a capacitor, a Darlington output circuit for instantaneously charging or discharging a large current from the capacitor, and a capacitor connected in parallel to the Darlington output circuit for discharging the electric charge of the capacitor. A low-saturation output circuit for charging or discharging up to the saturation voltage of a single transistor is provided.

Further, according to the present invention, a capacitor, a Darlington output circuit for charging or discharging a large current from the capacitor instantaneously, and a capacitor connected in parallel to the Darlington output circuit to charge the capacitor with a saturation voltage of a single transistor A low-saturation output circuit for charging or discharging up to and a comparator that outputs a reset signal or a timer signal having a predetermined time width by comparing the voltage of the capacitor with a predetermined Schmitt-configured threshold voltage. / Timer circuit is provided. Any of the above circuits can include a power down circuit.

[0017]

FIG. 6 shows a first embodiment of an output circuit for charging / discharging a capacitor according to the present invention. In each of the following embodiments, the output circuit for discharging the capacitor is described. However, it is apparent that the output circuit for charging the capacitor can be similarly configured by setting the reference potential of the capacitor to the ground side.

In FIG. 6, an output of a comparator 4 for detecting a reduced voltage is supplied to an IN terminal. However, unlike the examples of FIGS. 1, 4, and 5, in this example, a low-level signal is input at the time of detecting a reduced voltage. This change is for achieving logical matching with the increased transistor inside the switch 21, and can be easily realized by simply connecting the plus / minus inputs of the comparator 4 in FIGS. 1, 4 and 5 in reverse.

Therefore, the transistors (Q1, Q4) 32 and 34 to which the input signal of the IN terminal is supplied are turned on when the power supply voltage (V _DD ) is normal. The load of each of the transistors 32 and 34 is composed of the constant current sources 13 and 33, and their current values are as small as microampere, so that this does not pose a problem. At this time, the transistors (Q2, Q5) 35 and 28 in the next stage are both off. Further, the transistor (Q3) 36 for low-saturation output and the Darlington output transistors (Q6, Q7) 27 and 29 according to the present invention described below are also off.

The reason why the drive path of the transistor 36 for low saturation output and the bias path of the Darlington output transistors 27 and 29 are separately provided as described above is as follows.
This is for optimizing a bias current necessary for driving each transistor.

Darlington output transistors 27 and 2
Reference numeral 9 is provided to provide a large current capability with a small bias current as described with reference to FIG. In this example, the Darlington output transistors 27 and 29 have their saturation voltages (V
To reduce sat), a transistor 36 for low saturation output according to the invention is further provided, which operates as follows.

When the input signal at the IN terminal becomes low due to the detection of the reduced voltage, the transistors 32 and 34 are turned off, thereby turning on the transistors 35 and 28 in the next stage. Transistor 28 drives Darlington output transistors 27 and 29 to discharge a large current from capacitor 5 instantaneously as described in FIG. At the same time, the low-saturation output transistor 36 connected in parallel with the Darlington output transistors 27 and 29 also turns on. The transistor 36 has an on-state saturation voltage of about 0.1 V, and increases the on-state saturation voltage of the switch 21 to that voltage.

FIG. 7 is an explanatory diagram of the operation of FIG. FIG.
FIG. 3A is an enlarged drawing of the vicinity of the central portion in FIG. By detecting the undervoltage, first, the low-impedance Darlington output transistors 27 and 29
Large current flows instantaneously from the capacitor 5, and the negative potential of the capacitor 5 rises rapidly. It exceeds the threshold voltage (Vth0) of the comparator 8 (the reset signal is immediately output here), and still exceeds its saturation voltage (Vth0).
sat = 0.8 V).

Thereafter, a lower saturation voltage (Vsa
t = 0.1 V) for low-saturation output transistor 3
6 more slowly raises the negative potential of the capacitor 5 to the power supply voltage (V _DD ), more precisely V _DD -V sat (= 0.1 V). Since the reset signal has already been output, a very large current capability is not required for the transistor 36.

According to the present embodiment, the bias current is reduced by the Darlington output transistors 27 and 29, and the charge / discharge of the capacitor by the transistor 36 for low saturation output is reduced.
Low saturation voltage of the discharge control switch is achieved at the same time. In FIG. 7B, the Darlington output transistors are PNP-type transistors 27 'and 29'.
2 shows an example of a circuit configured with. It goes without saying that this operates similarly to FIG.

FIG. 8 shows a second embodiment of the capacitor charging / discharging output circuit according to the present invention. FIG.
Is basically the same as that of FIG. 6, and the operation is the same as that shown in FIG. However, in FIG. 8, the transistor 36 for low saturation output in FIG. 6 is replaced with a current mirror type transistor (Q3, Q4) 4
1 and 42. The current mirror has the following advantages.

That is, in the case of switching of the transistor 36 for low saturation output shown in FIG. 6, when it is turned on simultaneously with the Darlington output transistors 27 and 29, a large current flows to the transistor 36 side. Therefore, the element size of the transistor 36 also needs to be set to a corresponding size. On the other hand, if the low-saturation output transistor is a constant current source as in this embodiment, the current is limited at any time, and the element size of the low-saturation output side transistor 42 can be reduced. Further, the reliability can be further improved.

FIGS. 9 and 10 correspond to FIGS. 6 and 8, respectively.
Is another embodiment of the present invention. 9 and 10, the output of the comparator 4 for detecting a low voltage is directly supplied to the IN terminal. In each of FIGS. 6 and 8, the bias path of the transistor for low saturation output and the bias path of the Darlington output transistor are separately separated to optimize the respective bias currents.
In this example, emphasis is placed on simplification of the circuit, and a single bias path is used. As a result, a transistor for separating the bias path into two is not required, and FIGS.
As in the examples of FIGS. 5 and 6, a high-level signal is input at the time of voltage reduction detection.

FIGS. 9 and 10 show that a single bias current path is switched to simultaneously drive the low saturation output transistor 36 or both the constant current sources 41 and 42 and the Darlington output transistors 27 and 29. (Q1) 43 is provided. When the transistor 43 is turned on by the detection signal of the reduced voltage, the bias current flows through the transistor 36 for low saturation output or both the constant current sources 41 and 42 and the Darlington output transistors 27 and 29 via the transistor 43 to turn them on. . Conversely, when transistor 43 turns off, they also turn off. Other operations are the same as those in FIG. 6 and FIG.

FIG. 11 is a diagram showing a charge / discharge of a capacitor according to the present invention.
9 shows a third embodiment of the discharge output circuit. FIG. 11 has a circuit configuration similar to that of FIG. 8, but a power down function is newly added. When a high-level power-down signal is externally applied to the power-down terminal (PD), the transistor (Q4) 44 turns on, thereby turning off the transistor (Q5) 28 to completely remove the bias current of the Darlington output transistors 27 and 29. To shut off.

When this power-down function is used, in the reset state after the detection of the voltage decrease, unnecessary current consumption on the Darlington output transistor side requiring a large bias current as compared with the transistor for low saturation output is externally indicated. Can be reliably reduced. For example, an ignition (IG) signal of an automobile is provided from outside. In the case of the design specification in which reset is performed when the IG is turned off to reduce dark current, the IG off detection signal is output from the power-down terminal (PD).
To power down the high current output side.

FIG. 12 is a circuit diagram showing the charging / charging of a capacitor according to the present invention.
9 shows a fourth embodiment of the discharge output circuit. In FIG. 11, the power down is instructed from the outside. In FIG. 12, the power supply is automatically set to the power down by detecting that the negative potential of the capacitor 5 has risen to a predetermined potential. Therefore, a comparator 45 and a reference power supply 46 are newly provided.

The reference power supply 46 has, for example, the saturation voltage Vsat of the Darlington output transistors 27 and 29.
A reference voltage slightly smaller than 0.8V is applied. When the negative potential of the capacitor 5 exceeds the reference voltage (the Darlington output transistor 27)
And 29), a power down signal (high level signal) is output to turn on the transistor 44. Subsequent operations are the same as in FIG.

FIGS. 13 and 14 show another embodiment of FIG. 12, respectively. In FIG. 13, the reference voltage of the reference power supply 46 of FIG. 12 is generated by the forward potential (about 0.7 V) of the diode 46, and the bias current is given by the constant current source 47. Other operations are the same as those in FIG. Also, in FIG. 14, a similar function is realized only by the power-down transistor 44 as a simpler configuration instead of the comparator and the reference power supply 46 of FIG. Here, an example using the configuration of FIG. 8 is shown.

The PNP transistor 44 itself turns on when an on-voltage (about 0.7 V) is applied to the base-emitter voltage V _BE , and turns off when the on-voltage is less than that. Therefore, the negative potential of the capacitor 5 is equal to the ON potential (strictly speaking, V _BE +
When the voltage rises above the saturation voltage of the constant current source 33), the transistor 44 is turned off and shifts to a power down state. As is clear from this, the operation itself of this example is the same as that of FIG.

FIGS. 15 to 17 show examples in which the above-described capacitor discharge output circuit according to the present invention is applied to the power-on reset circuit of FIG. In FIG. 15, the example of FIG. 11 is used as a capacitor discharge output circuit, and a reset signal (high level at reset) of the comparator 8 is input as a power down (PD) input. This is also
It can be seen that the comparator 45 in the example of FIG. 12 is also used as the reset comparator 8.

According to this configuration, when the reset signal is output upon detecting the reduced voltage, the bias currents on the Darlington output transistors 27 and 29 which are no longer needed at that time are cut off. Also, constant current sources 41 and 4 for low saturation output
2, the saturation voltage is reduced to about 0.1 V, and the conventional discharge of the capacitor 5 shown in FIG. 1 is completed. In addition,
If the reset signal is replaced with a timer output signal, this example can be regarded as an example in which the capacitor discharge output circuit according to the present invention is applied to a timer circuit. The same applies to the following examples.

FIG. 16 further includes a power down terminal (PD) in the example of FIG. 15 so that a power down signal can be independently input from the outside. Here, the logical product (AND) of the internal PD (reset signal) and the external PD (for example, IG signal or the like) is calculated. When the logical AND is used, even if a power-down signal is input at an arbitrary time from the outside, the power-down does not become effective until the reset signal is output, so the undervoltage detection signal and the external power-down signal are output simultaneously. When this occurs, the side of the reduced voltage detection signal is prioritized, and the reset signal is reliably output.

In the example of FIG. 17, the reduced voltage detection signal is given as a set signal of the S-RF / F circuit 52 via the input terminal (IN). The set holding signal (Q) of the S-RF / F circuit 52 turns on the transistor (Q1) 43 to drive the capacitor discharge output circuit, and simultaneously turns on the transistor 53 connected to the collector of the reset output transistor 9 by a wired OR connection. Output the reset signal forcibly. The S-RF / F circuit 52 is reset by a reset signal from the comparator 8.

According to this configuration, the steps from the detection of the reduced voltage to the output of the reset signal due to the discharge of the capacitor 5 are reliably executed. In the case where the reset output control is performed directly using the reduced voltage detection signal, if the power supply voltage recovers before the reset signal is output, the reset circuit does not operate and malfunctions. According to this example, such malfunctions do not occur. Absent. Further, since the reset signal is immediately output from the transistor 53 described above, the Darlington output transistors 27 and 29
Can also be reduced. Therefore, the current consumption of the output circuit for discharging the capacitor can be reduced accordingly.

[0041]

As described above, according to the present invention, the bias current for controlling the charge / discharge of the capacitor is reduced and the saturation voltage of the switch for controlling the charge / discharge of the capacitor is also reduced. An output circuit and a timer circuit and a reset circuit using the output circuit can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration example of a power-on reset circuit including a low-voltage reset circuit and a runaway detection reset circuit.

FIG. 2 is a diagram showing an example of an operation waveform of the runaway detection reset circuit of FIG. 1;

FIG. 3 shows an example of an operation waveform of the low voltage reset circuit of FIG. 1;

FIG. 4 is a diagram illustrating a configuration example (1) of a conventional switch.

FIG. 5 is a diagram illustrating a configuration example (2) of a conventional switch.

FIG. 6 is a diagram showing a first embodiment of a capacitor charging / discharging output circuit according to the present invention.

FIG. 7 is an operation explanatory diagram of FIG. 6;

FIG. 8 is a diagram showing a second embodiment of the capacitor charging / discharging output circuit according to the present invention.

FIG. 9 is a diagram showing another example of the embodiment shown in FIG. 6;

FIG. 10 is a diagram showing another example of the embodiment of FIG. 8;

FIG. 11 is a diagram showing a third embodiment of the capacitor charging / discharging output circuit according to the present invention.

FIG. 12 is a diagram showing a fourth embodiment of the capacitor charging / discharging output circuit according to the present invention.

FIG. 13 is a diagram showing another example (1) of FIG. 12;

FIG. 14 is a diagram showing another example (2) of FIG. 12;

FIG. 15 is a diagram showing an application example (1) to a power-on reset circuit.

FIG. 16 is a diagram showing an application example (2) to a power-on reset circuit.

FIG. 17 is a diagram showing an application example (3) to a power-on reset circuit.

[Explanation of symbols]

 3, 4, 8, 45 Comparator 5 Capacitor 6, 7, 31, 33, 47 Constant current source 13, 46 Reference power supply 21, 22, 23, 24, 25 Switch 51 AND gate 52 S- RF / F circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J055 AX12 AX37 AX44 AX47 AX64 BX24 BX42 BX47 CX27 DX04 DX05 DX53 DX55 DX75 EX06 EY01 EY10 EY12 EY17 EZ03 EZ04 EZ10 EZ25 EZ32 EZ51 GX01 5J056 CC04 CCB CC CC CC DD25 DD51 FF08 GG06

Claims (17)

[Claims] 1. A capacitor, a Darlington output circuit that instantaneously charges or discharges a large current from the capacitor, and is connected in parallel to the Darlington output circuit, and charges or discharges the charge of the capacitor to the saturation voltage of a single transistor. And an output circuit for charging / discharging the capacitor. 2. The circuit according to claim 1, wherein said low saturation output circuit is constituted by a single transistor or a constant current circuit. A bias circuit for the Darlington output circuit and a bias circuit for the low saturation output circuit having different bias current paths; and a first switch for simultaneously switching the two bias currents. The circuit according to claim 1 or 2. 4. A bias circuit for the Darlington output circuit and a bias circuit for the low-saturation output circuit having the same bias current path, and a second switch inserted into the bias current path and switching the bias current path. The circuit according to claim 1 or 2. 5. The circuit according to claim 1, further comprising a power-down circuit for switching a bias current flowing through a bias circuit for said Darlington output circuit. 6. The circuit according to claim 5, further comprising a terminal for externally supplying a power down instruction signal to said power down circuit. 7. The power down circuit according to claim 5, further comprising a comparator for outputting a power down instruction signal by comparing the voltage of the capacitor with a predetermined threshold voltage, and supplying a power down instruction signal from the comparator to the power down circuit. circuit. 8. The predetermined threshold voltage is set near a saturation voltage value of the Darlington output circuit, and the comparator outputs a power down instruction signal when the voltage of the capacitor falls within the predetermined threshold value voltage. The circuit according to claim 7. 9. A capacitor, a Darlington output circuit that instantaneously charges or discharges a large current from the capacitor, and is connected in parallel to the Darlington output circuit, and charges or discharges the charge of the capacitor to the saturation voltage of a single transistor. And a comparator for outputting a reset signal or a timer signal having a predetermined time width by comparing the voltage of the capacitor with a predetermined Schmitt threshold voltage. Timer circuit. 10. The circuit according to claim 9, wherein said low saturation output circuit is constituted by a single transistor or a constant current circuit. 11. A bias circuit for the Darlington output circuit and a bias circuit for the low saturation output circuit having different bias current paths, and a first switch for simultaneously switching the two bias currents. The circuit according to claim 9 or claim 10. 12. A bias circuit for the Darlington output circuit and a bias circuit for the low-saturation output circuit having the same bias current path, and a second switch inserted into the bias current path and switching the bias current path. The circuit according to claim 9 or claim 10. 13. The circuit according to claim 9, further comprising a power-down circuit for switching a bias current flowing in a bias circuit for said Darlington output circuit. 14. A power supply circuit according to claim 1, further comprising a terminal for externally supplying a power down instruction signal to said power down circuit.
3. The circuit according to 3. 15. The circuit according to claim 13, wherein a reset signal or a timer signal from said comparator is supplied to said power down circuit instead of a power down instruction signal from said terminal. 16. An AN that supplies the power-down circuit with a logical product signal of a power-down instruction signal from the terminal and a reset signal or a timer signal from the comparator.
14. The circuit according to claim 13, comprising a D circuit. 17. A power down instruction signal is temporarily stored from the outside, the reset signal or the timer signal is forcibly output at the same time as the storage, and a power down instruction signal is supplied to the power down circuit. 14. The circuit according to claim 13, further comprising a temporary storage circuit for canceling the storage in response to a reset signal or a timer signal output.