JP2001101155A - Arithmetic unit and its method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of pins to be prepared in an ASIC. SOLUTION: An A/D converter 12 generates parallel digital data by encoding an analog signal inputted to an input terminal 11b into n bits. An operation testing serial digital signal inputted to the input terminal 11b is converted into an n-bit parallel digital signal through a serial/parallel converter 17, an n-bit counter 18 and a flip flop(FF) 19. A selector 13 is switched correspondingly to a test mode selection signal inputted to an input terminal 11e. A digital operation processing part 14 applies digital signal processing to the inputted n-bit parallel digital signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic device and a method, and more particularly, to an arithmetic device and a method capable of executing an operation test without providing a dedicated terminal for inputting an operation test signal.

[0002]

2. Description of the Related Art When designing an application-specific IC (hereinafter referred to as an ASIC) for executing digital signal processing with an analog signal as an input, for example, a configuration as shown in FIG. 1 can be considered. The ASIC 1 of FIG. 1 converts an analog signal input from an input terminal 2 into a digital signal and outputs the digital signal to a digital signal processing unit 4, and performs a predetermined operation on the input digital signal. And a digital signal processing unit 4 for outputting the obtained processed signal from an output terminal 5.
Consists of The input terminal 6 is directly connected to the digital signal processing unit 4.

In the process of designing the ASIC 1 of FIG. 1 and before shipping the manufactured ASIC 1 as a product, the manufactured ASIC 1 (particularly, the digital signal processing unit 4) is connected to the input terminal 6 by the designer. When testing whether or not to operate as intended, a test digital signal is input. Therefore, in this operation test, mainly the operation of the digital signal processing unit 4 is verified.

Of course, mainly the digital signal processing unit 4
When an analog signal for test is input from the input terminal 2 and the processing signal output from the output terminal 5 is verified for the purpose of performing the operation test, even if the processing signal is unintended, It cannot be determined whether the cause is the A / D conversion unit 3 or the digital signal processing unit 4, so that the purpose of the operation test cannot be achieved.

[0005]

Generally, an IC (Integrated Circuit) such as the ASIC 1 has a larger size as the number of pins corresponding to input / output terminals increases.
Also, if the size of the IC is limited, wiring and the like must be integrated in the limited space, which makes designing and manufacturing difficult.

Therefore, input pins and the like corresponding to the input terminals 6 which are used only during the operation test and are not used when the ASIC 1 is used for its intended purpose are provided, and the number of pins is reduced. It is desirable to minimize as much as possible.

The present invention has been made in view of such a situation, and is intended to reduce the number of pins provided in an ASIC by using a commonly used input terminal also during an operation test. is there.

[0008]

According to a first aspect of the present invention, in a normal operation mode, a first input means for inputting an analog signal, and the analog signal input by the first input means are converted into n bits. Encoding means for encoding to generate a first parallel digital signal; second input means for serially inputting a digital signal in an operation test mode; and a digital signal serially input by the second input means to n bits. A conversion unit for performing a parallel conversion to generate a second parallel digital signal; a calculation unit for performing digital calculation processing on the input n-bit parallel digital signal; and a selection signal for selecting a normal operation mode or an operation test mode And a first or second parallel digital signal corresponding to the selection signal. And a supply means for the first input means and second input means, characterized in that it is made of the same input terminal.

The operation device according to the first aspect of the present invention can further include a clock signal input unit for inputting a clock signal as a reference for operation, and a frequency dividing unit for dividing the period of the clock signal. In the mode, the clock signal input means can input a clock signal of n times speed of the clock signal input in the normal operation mode, and the frequency dividing means reduces the clock signal of n times speed to 1 / n. The frequency can be divided.

According to a third aspect of the present invention, in the normal operation mode, a first input step of inputting an analog signal and an analog signal input in the processing of the first input step are encoded into n bits. An encoding step of generating a first parallel digital signal, a second input step of serially inputting a digital signal in an operation test mode, and converting the digital signal serially input in the processing of the second input step to n bits. A conversion step of performing parallel conversion to generate a second parallel digital signal, a selection signal input step of inputting a selection signal for selecting a normal operation mode or an operation test mode, and a first or second signal corresponding to the selection signal. Supplying a parallel digital signal to the arithmetic means. When the input at the second input step,
The operation is performed from the same input terminal.

According to the first aspect and the third aspect of the present invention, in the normal operation mode, an analog signal is input and the input analog signal is encoded into n bits. Is generated. In the operation test mode, a digital signal is serially input, and the serially input digital signal is converted into n bits in parallel to generate a second parallel digital signal. Further, a selection signal for selecting the normal operation mode or the operation test mode is input, and the first or second parallel digital signal is supplied to the arithmetic means in accordance with the selection signal.

[0012]

FIG. 2 shows an ASIC 1 to which the present invention is applied.
0 shows a configuration example. The ASIC 10 mainly encodes an analog signal input to the input terminal 11b into n bits and outputs an A / D signal as parallel digital data.
The conversion unit 12, the serial / parallel conversion unit 17 to the flip-flop 19 for converting an operation test serial digital signal input to the input terminal 11b into an n-bit parallel digital signal, and a test mode selection signal input to the input terminal 11e. When active, input terminal b
Side and when inactive, the input terminal a
And a digital signal processing unit 14 that performs digital signal processing on an n-bit parallel digital signal input through the selector 13 and outputs the digital signal from an output terminal 15.

An A / D converter 12 has an input terminal 11 to which a reference signal A is input in a normal operation mode.
a, an input terminal 11 to which an analog signal (normal operation mode) or a digital signal (operation test mode) is input
b, an input terminal 11c to which a reference signal B is input in a normal operation mode, and an input terminal 11d to which a clock signal as a reference for operation is input.

The input terminal 11b is also connected to the serial / parallel converter 17. The clock signal input to the input terminal 11d is also supplied to the 1 / n frequency dividing section 20 and the AND section 16. The test mode selection signal input to the input terminal 11 e is supplied to the selector 13, the AND unit 16, and the 1 / n frequency dividing unit 20. A reset signal for resetting the serial / parallel converter 17 and the n-bit counter 18 is input to the input terminal 11f.

The AND section 16 outputs the clock signal from the input terminal 11d to the serial / parallel conversion section 17 and the n-bit counter 18 only when the test mode selection signal from the input terminal 11e is active. The serial / parallel converter 17 converts the digital signal from the input terminal 11b into a 0.5 clock cycle, a 1.5 clock cycle,
.., (N−0.5) clock cycles, and outputs the obtained n digital signals delayed by one clock cycle to the flip-flop 19 as n-bit parallel digital signals. .

The n-bit counter 18 counts the clock signal from the AND unit 16, generates a latch timing pulse and outputs it to the flip-flop 19 every time the count value becomes a multiple of n. The flip-flop 19
The n-bit parallel digital signal from the serial / parallel converter 17 is latched in synchronization with the latch timing pulse from the n-bit counter 18 and output to the input terminal b of the selector 13.

When the test mode selection signal is active, the 1 / n frequency dividing section 20 frequency-divides the cycle of the clock signal from the input terminal 11d to 1 / n and outputs the frequency to the digital signal processing section 14 for testing. When the mode selection signal is inactive, the signal is output to the digital signal processing unit 14 without dividing the frequency.

FIGS. 3 and 4 show the operation of the ASIC 10.
This will be described with reference to FIG. In the following, an example in which n bits are 4 bits is described.

First, the normal operation mode will be described.
In the normal operation mode, the input terminal 11a is
Reference signal A having a constant potential as shown in FIG.
Is input to the input terminal 11b, and an analog signal as shown in FIG.
Reference signal B having a constant potential as shown in FIG.
And a clock signal as shown in FIG. 3D is input to the input terminal 11d. The test mode selection signal input to the input terminal 11e and the input terminal 1
The reset signals input to 1f are both inactive.

In response to the test mode selection signal being inactive, the selector 13 switches to the input terminal a side, and the 1 / n frequency divider 20 does not divide the clock signal from the input terminal 11d. Is output to the digital signal processing unit 14 as it is.

The A / D converter 12 sets the analog signal from the input terminal 11b to the upper limit of the potential of the reference signal A from the input terminal 11a and the lower limit to the potential of the reference signal B from the input terminal 11c. 4-bit ADRC (Ada
Ptive Dynamic Range Coding) processing is performed to encode it into 4 bits, and the obtained 4-bit parallel digital signal is output to the input terminal a of the selector 13.

At this time, since the selector 13 is switched to the input terminal a side, the digital signal processing unit 14
The 4-bit parallel digital signal generated by the A / D converter 12 is processed.

Next, the operation test mode will be described. In the operation test mode, the input terminal 11b has:
A digital signal as shown in FIG. 4B is input, a clock signal as shown in FIG. 4D is input to the input terminal 11d, and an active test mode selection signal is input to the input terminal 11e. Then, a reset signal is input to the input terminal 11f only once at the start of the operation test mode.

In response to the test mode selection signal being active, the selector 13 switches to the input terminal b side, and the 1 / n frequency divider 20 sets the cycle of the clock signal to 1
The signal is divided into / 4 and output to the digital signal processing unit 14.

The serial / parallel converter 17 and the n-bit counter 18 are reset in response to the input reset signal.

Note that the input terminals 11a and 11c are
As shown in (A) and (C), no signal is input.

Since the test mode selection signal is active, the AND unit 16 outputs a clock signal from the input signal 11d to the serial / parallel converter 17 and the n-bit counter 18.

The serial / parallel converter 17 receives an input terminal 11b based on a clock signal from the logical product unit 16.
The digital signal input from the above is divided into 0.5 clock cycle, 1.5 clock cycle, 2.5 clock cycle, and 3.5 clock cycle.
The four digital signals delayed by one clock cycle and delayed by one clock cycle as shown in FIG.
Output to

The n-bit counter 18 counts the clock signal from the AND unit 16 and generates a latch timing pulse as shown in FIG. 19 is output. The flip-flop 19 latches the 4-bit parallel digital signal from the serial / parallel converter 17 in synchronization with the latch timing pulse from the n-bit counter 18, and outputs the 4-bit parallel digital signal as shown in FIG. To the input terminal b of the selector 13.

At this time, since the selector 13 has been switched to the input terminal b side, the digital signal processor 14
Processes the 4-bit parallel digital signal generated by the serial / parallel converter 17 through the flip-flop 19.

As is apparent from FIG. 4, the timing at which the 4-bit parallel digital signal is input to the digital signal processor 14 in the operation test mode is １ ／ of the frequency of the clock signal.
An accurate operation test cannot be executed.

Therefore, in the operation test mode, a clock signal having a cycle four times faster than that in the normal operation mode is input to the input terminal 11d. At this time, a clock signal (a clock signal having a frequency equal to the frequency of the normal operation mode) divided by a factor of 4 by the 1 / n frequency divider 20 is input to the digital signal processor 14.

As described above, the ASIC 10 according to the present embodiment is
In the operation test mode, the timing at which the 4-bit parallel digital signal is input to the digital signal processing unit 14 and the period of the input clock signal are exactly the same as those in the normal operation mode. It is possible to execute.

The present invention is applicable not only to ASICs but also to other electronic circuits.

[0035]

As described above, according to the arithmetic processing method according to the first aspect and the arithmetic method according to the third aspect, the first or second parallel digital signal is calculated in accordance with the selection signal. Since the power is supplied to the means, the number of pins provided on the ASIC can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a configuration of a conventional ASIC 1.

FIG. 2 is a block diagram illustrating a configuration example of an ASIC 10 according to an embodiment of the present invention.

FIG. 3 is a diagram for explaining processing in a normal operation mode of the ASIC 10.

FIG. 4 is a diagram for explaining processing in an operation test mode of the ASIC 10.

[Explanation of symbols]

10 ASIC, 11 input terminals, 12 A / D converter, 13 selector, 14 digital signal processor,
15 output terminal, 16 logical product section, 17 serial / parallel conversion section, 18 n-bit counter, 19
Flip-flop, 20 1 / n frequency divider

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G06F 11/22 330 G06F 11/22 330B H03M 1/10 H03M 1/10 C 9/00 9/00 C

Claims (3)

[Claims] 1. An arithmetic processing for performing digital arithmetic processing on an input analog signal, wherein in a normal operation mode, first input means for inputting the analog signal, and wherein the first input means Encoding means for encoding an analog signal into n bits to generate a first parallel digital signal; second operation means for serially inputting a digital signal in an operation test mode; Converting means for converting the digital signal into n bits in parallel to generate a second parallel digital signal; calculating means for performing digital processing on the input n-bit parallel digital signal; Selection signal input means for inputting a selection signal for selecting an operation test mode; And a supply means for supplying the first or second parallel digital signal to the arithmetic means. The first input means and the second input means are constituted by the same input terminal. An arithmetic unit characterized by the following. 2. The system further comprises: clock signal input means for inputting a clock signal as a reference for operation; and frequency dividing means for dividing the cycle of the clock signal. In the operation test mode, the clock signal input means 2. The apparatus according to claim 1, wherein a clock signal having an n-times speed of the clock signal input in the normal operation mode is input, and the frequency dividing means divides the n-times clock signal into 1 / n. Arithmetic unit. 3. An operation method of an operation including an operation step of performing digital operation processing on an input n-bit parallel digital signal, comprising: a first input step of inputting the analog signal in a normal operation mode; An encoding step of encoding the analog signal input in the processing of the first input step into n bits to generate a first parallel digital signal; and a second step of serially inputting a digital signal in an operation test mode. An input step; a conversion step of converting the digital signal serially input in the processing of the second input step into n bits to generate a second parallel digital signal; and the normal operation mode or the operation test A selection signal input step of inputting a selection signal for selecting a mode; Supplying the first or second parallel digital signal to the arithmetic means in response to the selection signal; and inputting at the first input step and inputting at the second input step Is an operation method performed from the same input terminal.