JP2001068993A5

JP2001068993A5 -

Info

Publication number: JP2001068993A5
Application number: JP1999238384A
Authority: JP
Filing date: 1999-08-25
Publication date: 2004-10-28
Anticipated expiration: 2019-08-25

Description

【発明の名称】情報処理装置[Title of the Invention] Information processing device

【０００１】
【発明の属する技術分野】
本発明は、アプリケーションプログラムによる処理の一部分を、回路構成を再構成できるプログラマブル論理回路で処理することが可能である情報処理装置に関する。特に、回路の再構成と処理を連続的に実行する方法に関するものである。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an information processing apparatus capable of processing a part of processing by an application program by a programmable logic circuit whose circuit configuration can be reconfigured. In particular, the present invention relates to a method for continuously performing circuit reconfiguration and processing.

【００２５】
【発明が解決しようとする課題】
本発明は、上述した事情に鑑みてなされたもので、プログラマブル論理回路を再構成するためのメインプロセッサの負荷を大幅に軽減させることができ、これにより低消費電力化を図るとともに、メインプロセッサを有効に活用できるようにしてシステム全体のパフォーマンスを向上させた情報処理装置を提供することを目的とするものである。[0025]
[Problems to be solved by the invention]
The present invention has been made in view of the above circumstances, and can significantly reduce the load on a main processor for reconfiguring a programmable logic circuit. It is an object of the present invention to provide an information processing apparatus which can be effectively used to improve the performance of the entire system.

【００２７】
このようにして、プログラマブル論理回路では、予め設定されている順番で、処理回路の再構成と実行が自動的に行われる。そのため、ＣＰＵなどの制御手段では、最初に実行指示を行うだけで、以後順番に行われるプログラマブル論理回路の再構成や実行指示を行う必要がない。これによってＣＰＵなどの制御手段によるプログラマブル論理回路の制御を行うための処理ステップが大幅に削減され、高速化を図ることができるとともに、消費電力を大幅に低減することができる。これとともに、プログラマブル論理回路を含めた情報処理装置における全体のパフォーマンスを向上させることができる。[0027]
Thus, in the programmable logic circuit, the reconfiguration and execution of the processing circuit are automatically performed in a preset order. Therefore, the control means such as the CPU only issues the execution instruction first, and does not need to issue the reconfiguration or execution instruction of the programmable logic circuit which is performed sequentially thereafter. As a result, the number of processing steps for controlling the programmable logic circuit by a control unit such as a CPU can be greatly reduced, and the speed can be increased, and the power consumption can be significantly reduced. At the same time, the overall performance of the information processing device including the programmable logic circuit can be improved.

【００９７】
【発明の効果】
以上の説明から明らかなように、本発明によれば、あらかじめ使用する回路と順番を規定できる場合には、メインプロセッサによる最初のデータ処理開始の制御だけで、あとは処理データ（例えば処理データのヘッダ情報）を解釈するだけで、プログラマブル論理回路の複数の機能回路によるデータ処理を順次実行してゆくことができる。このため、メインプロセッサによる制御の処理ステップを削減して高速化を図ることができるとともに、消費電力も低減することができる。[0097]
【The invention's effect】
As is clear from the above description, according to the present invention, when the circuit to be used and the order can be specified in advance, only the control of the first data processing start by the main processor is performed, and the processing data (for example, the processing data Only by interpreting the (header information), data processing by a plurality of functional circuits of the programmable logic circuit can be sequentially executed. Therefore, the number of processing steps of control by the main processor can be reduced to increase the speed, and the power consumption can be reduced.

【００９８】
また、回路の再構成のための制御に対するメインプロセッサの負荷が軽減されることによって、その処理パワーを他の処理へ使用できるため、システム全体のパフォーマンスの向上を図ることができるという効果がある。[0098]
In addition, since the load on the main processor for control for reconfiguring the circuit is reduced, the processing power can be used for other processing, so that the performance of the entire system can be improved.

Claims

In an information processing apparatus having a programmable logic circuit whose function can be changed and reconfigured at any time by changing circuit information, circuit information holding means for holding circuit information to be used in advance and an order, and a given process The first circuit information used for reconfiguring the programmable logic circuit is specified from the data, and the programmable logic circuit is reconfigured by the circuit information in the order held in the circuit information holding means from the specified circuit information. An information processing apparatus, comprising: an interface unit that configures a processing circuit by using the processing circuit and performs the processing of the processing data.

In the header part of the processing data, the order of the processing steps defined in advance, the address information of the circuit information holding unit that stores the circuit information to be reconfigured corresponding to the order, and the processing performed by the circuit corresponding to the order 2. The information according to claim 1, wherein address information of a storage unit for storing data, and information of the number of circuits that can be simultaneously and continuously reconfigured in the programmable logic circuit corresponding to the order are added. Information processing device.

The interface means corresponds to the order of processing steps when, in the relationship between the maximum configurable circuit size of the programmable logic circuit and the circuit size to be reconfigured, if an area where continuous processing circuits cannot be reconfigured at the same time cannot be ensured. And control is performed so that processing is performed continuously while sequentially performing processing by the configured processing circuit and input / output of intermediate processing data processed by the processing circuit to / from the storage unit. The information processing apparatus according to claim 2, wherein

The interface means, after performing reconfiguration of a plurality of processing circuits in a relationship between a maximum configurable circuit size of the programmable logic circuit and a circuit size to be reconfigured, processing in the processing circuits is continuously executed. And storing the result of the last processing circuit in the storage means as intermediate processing data, and controlling the reconfiguration of the plurality of processing circuits and the processing in the plurality of processing circuits to be sequentially executed. Item 3. The information processing device according to item 2.

The interface means, in the relationship between the maximum configurable circuit scale of the programmable logic circuit and the circuit scale to be reconfigured, the reconfiguration of a plurality of processing circuits, while continuously performing as many as can be reconfigured simultaneously, the first When the reconfiguration of the processing circuit is completed, the first processing is executed, and the reconfiguration of the next circuit is performed in parallel with the execution of the processing, and the processing result is transferred to the next reconfigured processing circuit for continuous processing. 3. The information processing apparatus according to claim 2, wherein the control is performed such that the processing is performed.

The information processing apparatus according to claim 4, wherein a processing result in the processing circuit can be stored in the storage unit as intermediate processing data.

6. The information processing apparatus according to claim 4, wherein a processing result in the processing circuit can be stored in the storage unit as intermediate processing data every time the processing of a predetermined processing step is completed.