JP2000330798A - Interrupt controller and method for verifying interrupt control - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily verify interrupt control to an interrupt request signal from the outside by separating the hardware of an input-output device from software in a processor. SOLUTION: This controller is provided with a mask register Rm which masks respective interrupt request signals IRQ1 to IRQn while corresponded to the priorities of the signals IRQ1 to IRQn and a pseudo-interrupt generation register Rq which generates a signal being the origin of a pseudo-interrupt control signal simulating an encode signal 5 generated by the respective signals IRQ1 to IRQn while the entire interrupt request signals IRQ1 to IRQn are masked by the register Rm, a processor 1 performs interrupt processing by the pseudo-interrupt control signal generated on the basis of the signal of the register Rq, and the operation verification only of software is performed on the basis of this interrupt processing results.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system which generates an interrupt control signal with a priority set based on an interrupt request signal from an input / output device and notifies the processor of the interrupt control signal. The present invention also relates to an interrupt control device and an interrupt control verification method for causing the processor to execute an interrupt process.

[0002]

2. Description of the Related Art Conventionally, an interrupt process in a computer system is incorporated in an operating system or the like. During execution of the program, the execution of the program is temporarily interrupted for some reason, and the processing program is executed according to the factor. .

Generally, interrupt factors in a processor include:
External factors and internal factors can be classified, and the external factors include those for recognizing that the outside of the processor has entered a special state, and processing requests from an external peripheral device to the processor. As the internal factors, there are processing requests from the built-in peripheral functions to the microcomputer, such as the elapse of a set time by an internal timer and the end of serial data transfer. When there are a plurality of interrupts, it may be necessary to prohibit the interrupt in program processing due to the interrupt. In this case, the prohibition of the interrupt is called a mask.

FIG. 8 is a block diagram showing the configuration of a computer system including a conventional interrupt control device. In FIG. 8, a processor bus 23 includes a memory 21a, a processor 21, and a plurality of input / output devices (I / Os) 22-1 to 22-1.
22-n are connected. The interrupt control device 30 includes a plurality of I
/ O22-1 to 22-n and the processor 21.

[0005] External interrupt request signals IRQ11 to IRQ1n are input from a plurality of I / Os 22-1 to 22-n to an interrupt control device 30, and the interrupt control device 30 outputs the interrupt request signals IRQ11 to IRQ11 to IRQ1n. An encode signal 25 with a priority corresponding to IRQ1n is generated, and an interrupt is generated by notifying the encode signal 25 to the processor 21. The processor 21 has an interrupt handler (not shown), and activates an interrupt process for an externally generated interrupt request (encode signal).

Japanese Patent Application Laid-Open Nos. 60-22248 and 2-202634 disclose priority determination processing of a plurality of interrupt request signals, mask processing of interrupt request signals, and state of interrupt request signals. An interrupt control device capable of performing a monitoring process and the like is disclosed.

[0007]

However, in the above-described conventional interrupt control device, the hardware of the input / output device and the interrupt control device operates normally, and the software for the interrupt control device operates normally. Assuming that the initial settings for the interrupt control device are also set correctly, the encode signal from the interrupt control device is notified to the processor. If these hardware or software does not operate normally, the interrupt Processing is not performed normally.

If this interrupt processing is not performed normally, the interrupt handler inside the processor is verified. However, since it is assumed that the above-described hardware or software is operating normally, the interrupt control is performed. However, there is a problem that the verification process becomes complicated and takes time.

In particular, when the hardware does not operate normally, the software verification is based on the normal operation of the hardware. Therefore, it is not easy to separate the software from the hardware, and the verification process becomes complicated. There was such a problem.

Furthermore, when a new input / output device or interrupt control device is employed in a computer system, it is necessary to use hardware or software in consideration of compatibility with the computer system. Alternatively, if the development time of the interrupt control device is short, etc., it is not possible to take sufficient time to understand the technical contents of the computer system. In many cases, the verification processing of the conventional interrupt control device that does not take this point into account takes a considerable amount of time.

[0011] The present invention has been made in view of the above,
An object of the present invention is to provide an interrupt control device and an interrupt control verifying method capable of easily verifying interrupt control for an interrupt request signal from the outside by separating the hardware and software described above.

[0012]

In order to achieve the above object, an interrupt control device according to the present invention generates an interrupt control signal with a priority set based on an interrupt request signal from an input / output device. And a mask setting means for masking each interrupt request signal in accordance with the priority of the interrupt request signal, and a mask setting means for notifying all of the interrupt request signals to the processor. Pseudo signal generation means for generating a pseudo interrupt control signal that simulates an interrupt control signal generated by each interrupt request signal in a state in which the interrupt request signal is masked. The processor performs an interrupt process in response to the pseudo interrupt control signal.

According to this invention, the mask setting means masks each interrupt request signal in accordance with the priority of the interrupt request signal from the input / output device. A processor that generates a pseudo interrupt control signal that simulates an interrupt control signal generated by each interrupt request signal while masking all the interrupt request signals, and uses the pseudo interrupt control signal to perform an interrupt process. And causes the processor to execute the interrupt processing, and easily verifies only the software of the interrupt processing by the processor based on the result of the interrupt processing.

[0014] In the interrupt control device according to the next invention, in the above invention, the interrupt request signal storage means for temporarily storing the presence or absence of each of the interrupt request signals and the interrupt request signal storage means are stored in the interrupt request signal storage means. A first history holding unit for holding a history of the presence / absence of the interrupt request signal.

According to the present invention, the interrupt request signal storage means temporarily stores the presence or absence of each of the interrupt request signals, and the first history holding means stores the interrupt request signal stored in the interrupt request signal storage means. The history of the presence / absence of the write request signal is held.

The interrupt control apparatus according to the next invention is the above-mentioned invention, wherein the interrupt control signal storage means for temporarily storing the content of the interrupt control signal, and the interrupt control signal stored in the interrupt control signal storage means. Second that holds the history of the contents of the
And a history holding means.

According to this invention, the interrupt request signal storage means temporarily stores the content of the interrupt control signal, and the second history holding means stores the interrupt control signal stored in the interrupt control signal storage means. The history of the contents of the control signal is retained.

The interrupt control device according to the next invention is the above-mentioned invention, wherein, after the generation of the interrupt request signal, from the masking of the interrupt request signal by the mask setting means to the release of the mask of the interrupt request signal. If the interrupt request signal does not change during this period, the processor further includes a notifying unit that notifies the processor that an error has occurred in the interrupt control device.

According to the present invention, the notifying unit is configured to execute the interrupt from the generation of the interrupt request signal to the release of the interrupt request signal from the masking of the interrupt request signal by the mask setting unit. When the request signal does not change, the processor is notified of the occurrence of an abnormality in the interrupt control device.

An interrupt control verification method according to the next invention is as follows.
In an interrupt control verification method for generating a series of interrupt control signals in which priority is set based on an interrupt request signal from an input / output device and verifying a series of interrupt controls for performing an interrupt process by a processor, A pseudo signal generating step of generating a pseudo interrupt control signal that simulates an interrupt control signal generated by each interrupt request signal while masking the interrupt request signal of A software verifying step of causing the processor to perform an interrupt process using an interrupt control signal and verifying software of the processor.

According to the present invention, first, in the pseudo signal generation step, a pseudo interrupt control signal simulating the interrupt control signal generated by each interrupt request signal in a state where all the interrupt request signals are masked is generated. Then, in a software verification step, the processor is caused to perform an interrupt process using the pseudo interrupt control signal generated in the pseudo signal generation step, and the software of the processor is verified.

An interrupt control verification method according to the next invention is as follows.
An interrupt control verification method for generating a series of interrupt control signals based on an interrupt request signal from an input / output device and verifying a series of interrupt controls for performing an interrupt process by a processor, A mask setting step of masking each interrupt request signal in accordance with the priority of the interrupt request signal; and temporarily storing the presence / absence of each interrupt request signal and holding a history of the presence / absence of the interrupt request signal. And a hardware verification step of verifying hardware related to the input / output device based on an interrupt processing result of the processor and a history of the holding step.

According to the present invention, first, in the mask setting step, each interrupt request signal is masked in accordance with the priority of the interrupt request signal, and in the holding step, the presence / absence of each interrupt request signal is temporarily stored. Then, the history of the presence or absence of the interrupt request signal is held, and the hardware related to the input / output device is verified by the hardware verification step based on the result of the interrupt processing by the processor and the history of the holding step. ing.

The interrupt control verification method according to the next invention is as follows.
In the above invention, a history holding step of temporarily storing the content of the pseudo interrupt control signal or the interrupt control signal and holding a history of the content of the pseudo interrupt control signal or the interrupt control signal; A signal generation verifying step of verifying the generation of the pseudo interrupt control signal or the interrupt control signal based on the history held by the holding step.

According to this invention, first, in the history holding step, the pseudo interrupt control signal or the content of the interrupt control signal is temporarily stored, and the history of the pseudo interrupt control signal or the content of the interrupt control signal is stored. After that, in a signal generation verifying step, the generation of the pseudo interrupt control signal or the interrupt control signal is verified based on the history held in the history holding step.

The interrupt control verification method according to the next invention is as follows.
An interrupt control verification method for generating a series of interrupt control signals based on an interrupt request signal from an input / output device and verifying a series of interrupt controls for performing an interrupt process by a processor, A monitoring step of monitoring a change in the interrupt control signal during a period from generation of the interrupt request signal to mask release of the interrupt request signal by the mask setting unit after generation of the interrupt request signal; And notifying the processor that an abnormality has occurred when the interrupt request signal does not change.

According to the present invention, first, in the monitoring step, after the interrupt request signal is generated, the interrupt request signal is masked by the mask setting means until the mask of the interrupt request signal is released. A change in the interrupt control signal is monitored, and the notifying step notifies the processor that an abnormality has occurred when the interrupt request signal does not change in the monitoring step.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of an interrupt control device and an interrupt control verification method according to the present invention will be described below in detail with reference to the accompanying drawings.

Embodiment 1 First, a first embodiment of the present invention will be described. FIG. 1 is a block diagram showing a configuration of a computer system including an interrupt control device according to Embodiment 1 of the present invention. 1, a processor 1, a memory 1a, and a plurality of input / output devices (I / O) 2-1 to 1
2-n are connected to the processor bus 3, respectively. The interrupt control device 10 includes a processor 1 and a plurality of I / O2s.
-1 to 2-n.

The processor 1 performs an interrupt process based on the encode signal 5 input from the interrupt control device 10, and an interrupt handler 6 realized by software and a plurality of I / Os 2-1 to 2- n is described,
It has O software 7 and a debugger 8 that can perform a debug process and settings for the interrupt control device 10.

The interrupt control device 10 includes a plurality of I / Os 2-1.
, A pseudo interrupt generation register Rq for generating a pseudo interrupt request signal corresponding to .about.2-n, a mask register Rm for masking the interrupt request signal, interrupt request signals IRQ1 to IRQn, and a mask register Rm corresponding thereto. AND circuits 11-1 to 11-n which take the logical product of the outputs from the AND circuits 11-1 to 11-n, and the outputs of the AND circuits 11-1 to 11-n and the output of the pseudo interrupt generation register Rq are respectively associated with each other to form a logical sum. OR circuits 12-1 to 12-n and OR circuits 12-1 to 12-12
It has a priority encoder 13 that generates an encoded signal 5 assigned a priority based on the output of −n and outputs it to the processor 1.

The interrupt request signals IRQ1 to IRQn from the I / Os 2-1 to 2-n are transmitted to the respective I / Os in the interrupt control device 10.
AND circuits 11-1 to 11- corresponding to 2-1 to 2-n
n. On the other hand, AND circuits 11-1 to 11-n
Are connected to one of the input terminals of interrupt request signals IRQ1 to IRQn.
, The bit content R of the mask register Rm corresponding to
m1 to Rmn are input. The bit contents Rm1 to Rmn of the mask register Rm are set to mask or not to mask based on a preset priority.
That is, among the interrupt request signals IRQ1 to IRQn, the bit contents Rm1 to Rmn of the mask register Rm corresponding to the highest priority interrupt request signal are set to “1”, and the other bit contents Rm1 to Rmn are set to “1”. Set to "0".
When the bit contents Rm1 to Rmn of the mask register Rm are “0”, an interrupt request is not generated by logical AND regardless of the presence or absence of the interrupt request signal. That is,
The interrupt is masked.

The outputs of the AND circuits 11-1 to 11-n are
The outputs are input to one ends of the OR circuits 12-1 to 12-n, and the outputs of the AND circuits 11-1 to 11-n are set to "1" by a logical sum.
In this case, "1" is always output to the priority encoder 13. The other input terminals of the OR circuits 12-1 to 12-n have bit contents Rq1 to Rq1 of the pseudo interrupt generation register Rq corresponding to the interrupt request signals IRQ1 to IRQn, respectively.
The output of qn is input. The bit contents Rq1 to Rqn of the pseudo interrupt generation register Rq are set by the debugger 8, and pseudo interrupt request signals for simulating the interrupt request signals IRQ1 to IRQn are input to the other input terminals of the OR circuits 12-1 to 12-n. Is input to When the pseudo interrupt request signal is generated, the bit contents Rm1 to Rmn of the mask register Rm are set by the debugger 8 so as not to generate the encode signal 5 corresponding to the interrupt request signals IRQ1 to IRQn.
All are masked. That is, the bit contents Rm1 to Rm
All n are set to “0”.

Thereafter, the priority encoder 13
Generates an encoded signal 5 with a priority based on the output signals input from the OR circuits 12-1 to 12-n, outputs the encoded signal 5 to the processor 1, and a predetermined interrupt is generated by the interrupt handler 6. Will happen. By the way, in the above-described interrupt control, it is necessary to verify a defect beforehand or to verify a defect that has occurred afterward. The verification process in this case will be described with reference to a flowchart shown in FIG.

FIG. 2 is a flowchart showing a hardware / software verification processing procedure. The hardware refers to hardware of the plurality of I / Os 2-1 to 2-n and the interrupt control device 10, and the software refers to software in the processor 1.

In FIG. 2, first, a normal interrupt process is performed (step S11). That is, a plurality of I / O2-1 to I / O2-1
2-n, outputs an interrupt request signal to the interrupt controller 10;
The interrupt controller 10 outputs an encode signal 5 to the processor 1 based on the output interrupt request signal, and the interrupt handler 6 in the processor 1 executes an interrupt routine based on the encode signal 5. .

Thereafter, it is determined whether or not the interrupt processing has been performed normally (step S12). If the interrupt processing has been normally performed (step S12, YES), the present processing is terminated, and the processing has not been performed normally. In this case (step S12, NO), the software verification process is executed by setting the pseudo interrupt generation register Rq to the pseudo interrupt request signal (step S12).
13), it is determined whether the software is normal (step S14). Thereafter, if the software is normal (step S14, YES), it is determined that the hardware is abnormal (step S15), and if the software is not normal (step S14, NO),
It is determined that the software is abnormal (step S1
6), end this processing.

Next, the software verification processing procedure shown in FIG. 2 will be described in detail with reference to the flowchart in FIG. In FIG. 3, first, the debugger 8 checks all bit contents Rq1 to Rq of the pseudo interrupt generation register Rq.
n is set to “0” (step S21). Thereafter, the debugger 8 further sets all bit contents Rm1 to Rmn of the mask register Rm to “0” (step S2).
2). Thereby, the interrupt request signals IRQ1 to IRQn
Is not input to the priority encoder 13, and as a result, the encoded signal 5 is not generated.

Thereafter, the desired interrupt request signals IRQ1 to IRQ1 to IRQ1
Pseudo interrupt generation register R corresponding to one of RQn
The bit contents Rq1 to Rqn of q are set to “1” (step S23), and the process returns to step S13. Thereby, the pseudo interrupt request signal is input to the priority encoder 13 via the OR circuits 12-1 to 12-n, the generated encode signal 5 is input to the processor 1, and the interrupt process is executed.

According to the first embodiment, the pseudo interrupt generation register Rq is set by the debugger 8 which is software, and an interrupt request signal generated by hardware is intentionally generated as a pseudo interrupt request signal. Since the interrupt processing of the interrupt handler 6 of the processor 1 can be activated, it is possible to reliably separate the hardware from the hardware and easily verify the operation of only the software of the interrupt handler 6 in the processor 1. Can be.

In the first embodiment, the software verification processing (step S13) and the like are performed after the normal interruption processing (step S11). However, the software verification processing itself is performed independently. May be performed. By this independently performed software verification processing, the operation verification of only the interrupt handler 6 in the processor 1 can be easily performed.

Embodiment 2 Next, a second embodiment of the present invention will be described. In the first embodiment, the pseudo interrupt request signal is generated by setting the pseudo interrupt generation register Rq, and the interrupt handler 6 is activated by the encode signal based on the pseudo interrupt request signal, and the operation of the interrupt handler 6 is performed. Although the verification is performed, in the second embodiment, only the operation verification of the hardware of the I / Os 2-1 to 2-n and the interrupt control device 10 can be performed.

FIG. 4 is a block diagram showing a configuration of a computer system including an interrupt control device according to the second embodiment of the present invention. In FIG. 4, in addition to the configuration of interrupt control device 10 shown in FIG. 1, interrupt control device 10 generates status register Rs for temporarily storing the state of interrupt request signals IRQ1 to IRQn, and priority encoder 13 generates An encoding status register 14 for temporarily storing the information content of the encoding signal 5 to be encoded, and a status register Rs
And a history acquiring / holding unit 15 for sequentially acquiring and holding the contents temporarily stored in the encoding status register 14 as a history. The other configuration is the same as the configuration shown in FIG. Are denoted by the same reference numerals.

Here, the status register R
The hardware / software verification process using the s, the encode status register 14, and the history acquisition / hold unit 15 will be described with reference to the flowchart shown in FIG. In FIG. 5, first, a normal interrupt process is performed (step S31). That is, a plurality of I / O2-1 to I / O2-1
2-n, outputs an interrupt request signal to the interrupt controller 10;
The interrupt controller 10 outputs an encode signal 5 to the processor 1 based on the output interrupt request signal, and the interrupt handler 6 in the processor 1 executes an interrupt routine based on the encode signal 5. .

Thereafter, the history obtaining / holding unit 15 outputs the interrupt request signals IRQ1 to IRQ1 which change by the normal interrupt processing.
The history of RQn and the encoding signal 5 is acquired (step S32). That is, the bit contents of the interrupt request signals IRQ1 to IRQn sequentially stored in the status register Rs and the information contents of the encode signal 5 sequentially stored in the encode status register 14 are acquired as a pair and held as history information.

Thereafter, it is determined whether or not the interrupt has been normally performed (step S33). If the interrupt has been normally performed (step S33, YES), the present process is terminated, and the interrupt is terminated. If not performed normally (step S33, N
In O), it is further determined whether or not the history content of the status register Rq is normal (step S34). If the history content of the status register Rq is not operating normally (step S34, NO), the I / Os 2-1 to 2-
It is determined that n is abnormal (step S36), this processing ends, and if the history content of the status register Rq is normal (step S34, YES), the I / O 2-1
To 2-n are determined to be operating normally (step S3).
5).

If it is determined that the I / Os 2-1 to 2-n are operating normally (step S35), it is further determined whether or not the contents of the encode status register 14 are normal (step S37). If it is determined that the contents of the encode status register 14 are not operating normally (step S37, NO), the interrupt control device 10
Is determined to be abnormal (step S3).
9) If it is determined that the contents of the encode status register 14 are operating normally (step S37, YE)
In S), it is determined that the hardware of the interrupt control device is normal and the software in the processor 1 is abnormal (step S38), and the process ends.

In the above-described second embodiment, the normal interrupt processing (step S31) is performed. However, the present invention is not limited to this, and the interrupt processing performed by the pseudo interrupt request signal in the first embodiment is performed. There may be. In this case, the hardware of the interrupt control device 10, particularly the hardware of the priority encoder 13 and the like can be verified. Also, by using the pseudo interrupt request signal and the interrupt request signal,
It is possible to further specify a hardware failure location in the interrupt control device 10.

In the second embodiment, the status register Rs and the encode status register 14
Although the processing is performed in combination with the above, the present invention is not limited to this, and hardware verification may be performed using either one. Further, in the second embodiment, the history acquisition /
When the holding unit 15 retrieves the history information, an interface that directly retrieves the outputs of the status register Rs and the encode status register 14 may be provided.

According to the second embodiment, the status register Rs and the encode status register 1
4, only the I / Os 2-1 to 2-n and the hardware of the interrupt control device 10 can be easily verified. If the history is normal, the software can be verified at the same time.

Embodiment 3 FIG. Next, a third embodiment of the present invention will be described. In the third embodiment, the information content of the status register Rs provided in the second embodiment is monitored, and the state of the interrupt control is determined based on the monitoring result.

FIG. 6 is a block diagram showing a configuration of a computer system including an interrupt control device according to the third embodiment of the present invention. In FIG. 3, the interrupt control device 10 is different from the interrupt control device 10 shown in FIG.
The bit contents Rs1 to Rsn of s are monitored, and if an interrupt request signal that has issued an interrupt request within a series of interrupt control periods does not change even after a series of interrupt control periods, an abnormality in the processing of the mask register is determined. It has a monitoring unit 16 for notifying the processor 1, and the other configuration is the same as that of the second embodiment, and the same components are denoted by the same reference numerals.

Normally, when the interrupt is activated, the interrupt handler 6 sets the bit contents Rm1 to Rmn of the mask register Rm.
Is performed, and then I / O2-1 to I / O2-1 to I-2
A series of processes for canceling the interrupt factor of -n and canceling the mask are executed. During this series of interrupt processing periods, the monitoring unit 16 monitors the bit contents Rm1 to Rmn of the mask register Rm, and the interrupt request signal that issued the interrupt request until the mask is released does not change to “0”. In this case, the processor 1 is notified of an interrupt that cannot be masked or that the history is abnormal.

The dynamic verification process of the interrupt control in the monitoring unit 16 in the interrupt control device 10 will be described with reference to the flowchart of FIG. In FIG. 7, first, the monitoring unit 16 determines the bit contents Rs1 to Rs1 of the status register Rs.
Rsn is monitored (step S41). Thereafter, it is determined whether or not the above-described series of interrupt processing periods has elapsed (step S42). If the series of interrupt processing periods has not elapsed (step S42, NO), the process proceeds to step S41, and if the series of interrupt processing periods has elapsed (step S42).
(42, YES), it is determined whether the monitored interrupt request signal has changed from "1" to "0" (step S43).

When the interrupt request signal changes (step S
43, YES), it is determined that the interrupt processing is operating normally, and the flow shifts to the step S41 to repeat the above-described processing.
When the interrupt request signal does not change (step S43, N
In O), the processor 1 is notified that the interrupt processing is abnormal (step S44), and the processing ends.

According to the third embodiment, the second embodiment
The bit contents Rs1 to Rs1 of the status register Rs provided by
Since Rsn is monitored and an abnormality in the interrupt control is dynamically detected and notified to the processor 1, a failure due to the abnormality in the interrupt control can be immediately detected, and an abnormality in the interrupt control can be detected. To prevent the occurrence of unpredictable actions based on the information from spreading.

[0057]

As described above, according to the present invention, the mask setting means masks each interrupt request signal in accordance with the priority of the interrupt request signal from the input / output device. Means for generating a pseudo interrupt control signal simulating an interrupt control signal generated by each interrupt request signal in a state where all the interrupt request signals are masked by the mask setting means; Is notified to the processor that performs the interrupt processing, and the processor executes the interrupt processing. Based on the result of the interrupt processing, only the software of the interrupt processing by the processor is easily verified. A pseudo interrupt control signal corresponding to the control signal can be intentionally generated, and the input / output device and the verification of the hardware of the interrupt control device are separated from each other.
There is an effect that the verification processing of only the software can be easily performed.

According to the next invention, the interrupt request signal storage means temporarily stores the presence or absence of each of the interrupt request signals, and the first history holding means stores the interrupt request signal in the interrupt request signal storage means. Since the history of the presence / absence of the interrupt request signal is retained, it is possible to easily verify only the hardware of the input / output device based on the result of this history, and before the development of the software in the processor. This has the effect that the hardware of the input / output device can be verified.

According to the next invention, the interrupt request signal storage means temporarily stores the content of the interrupt control signal, and the second history holding means stores the interrupt control signal stored in the interrupt control signal storage means. Since the history of the contents of the interrupt control signal is held, the effect is obtained that the hardware of the input / output device and the hardware of the interrupt control device can be verified based on the history result. Further, since the interrupt request signal from the input / output device can be centrally managed, it is possible to simplify the configuration of the interrupt processing software and to reduce the number of bug generation factors. .

According to the next invention, after the interrupt request signal is generated, the notifying means performs the interrupt processing between the time when the mask setting means masks the interrupt request signal and the time when the interrupt request signal is unmasked. When the interrupt request signal does not change, the processor is notified of the occurrence of an abnormality in the interrupt control device. Therefore, the interrupt request signal storage means is effectively used to dynamically execute the interrupt processing. This makes it possible to perform an accurate verification process and prevent an unexpected operation from occurring due to the occurrence of an abnormality.

According to the next invention, first, in the pseudo signal generation step, a pseudo interrupt control signal simulating the interrupt control signal generated by each interrupt request signal while all the interrupt request signals are masked. Then, the software verification step causes the processor to perform an interrupt process using the pseudo interrupt control signal generated by the pseudo signal generation step, thereby verifying the software of the processor. , A pseudo interrupt control signal corresponding to the interrupt control signal can be intentionally generated, and verification of only software can be performed by separating the verification of the input / output device and the hardware of the interrupt control device. There is an effect that it can be easily performed.

According to the next invention, first, in the mask setting step, each interrupt request signal is masked in accordance with the priority of the interrupt request signal, and in the holding step, the presence / absence of each interrupt request signal is temporarily determined. Storing the history of the presence / absence of the interrupt request signal, and verifying the hardware related to the input / output device based on the result of the interrupt processing by the processor and the history of the holding step by a hardware verification step. Therefore, it is possible to easily verify only the hardware of the input / output device based on this history result, and to verify the hardware of the input / output device before developing the software in the processor. It has the effect of being able to.

According to the next invention, first, in the history holding step, the pseudo interrupt control signal or the content of the interrupt control signal is temporarily stored, and the pseudo interrupt control signal or the content of the interrupt control signal is stored. The history is held, and then, by the signal generation verification step, the pseudo interrupt control signal or the generation of the interrupt control signal is verified based on the history held by the history holding step. There is an effect that the hardware of the input / output device and the hardware of the interrupt control device can be verified based on the history result. Further, since the interrupt request signal from the input / output device can be centrally managed, it is possible to simplify the configuration of the interrupt processing software and to reduce the number of bug generation factors. .

According to the next invention, first, in the monitoring step, after the generation of the interrupt request signal, the mask setting unit sets the mask between the mask of the interrupt request signal and the release of the mask of the interrupt request signal. A change in the interrupt control signal is monitored, and the notifying step notifies the processor that an abnormality has occurred when the interrupt request signal does not change in the monitoring step. This makes it possible to perform an efficient verification process and to prevent the occurrence of an unexpected operation due to the occurrence of an abnormality.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a computer system including an interrupt control device according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing a hardware / software verification processing procedure using the interrupt control device shown in FIG. 1;

FIG. 3 is a flowchart showing a detailed processing procedure of the software verification processing shown in FIG. 2;

FIG. 4 is a block diagram showing a configuration of a computer system including an interrupt control device according to a second embodiment of the present invention.

FIG. 5 is a flowchart showing a hardware / software verification processing procedure using the interrupt control device shown in FIG. 4;

FIG. 6 is a block diagram showing a configuration of a computer system including an interrupt control device according to a third embodiment of the present invention.

7 is a flowchart showing a procedure of a verification process of interrupt control using the interrupt control device shown in FIG. 6;

FIG. 8 is a block diagram showing a configuration of a conventional computer system including an interrupt control device.

[Explanation of symbols]

Reference Signs List 1 processor, 1a memory, 2-1 to 2-n input / output device (I / O), 3 processor bus, 5 encode signal, 6 interrupt handler, 7 I / O software, 8
Debugger, 10 interrupt controller, 11-1 to 11-n
AND circuit, 12-1 to 12-n OR circuit, 13
Priority encoder, 14 encoding status register, 15 history acquisition / holding unit, 16 monitoring unit,
IRQ1 to IRQn interrupt request signal, Rq pseudo interrupt generation register, Rm mask register, Rs status register.

Claims (8)

[Claims] 1. An interrupt control device for generating an interrupt control signal of which priority is set based on an interrupt request signal from an input / output device and notifying the processor of the interrupt control signal, Mask setting means for masking each interrupt request signal in accordance with the priority of the request signal; and interrupt control generated by each interrupt request signal in a state where all the interrupt request signals are masked by the mask setting means. A pseudo-signal generating means for generating a pseudo-interrupt control signal that simulates a signal, wherein the processor performs an interrupt process based on the pseudo-interrupt control signal generated by the pseudo-signal generating means. Control device. 2. An interrupt request signal storage means for temporarily storing the presence / absence of each of said interrupt request signals, and a first memory for holding a history of the presence / absence of the interrupt request signal stored in said interrupt request signal storage means. The interrupt control device according to claim 1, further comprising: a history holding unit. 3. An interrupt control signal storing means for temporarily storing the content of the interrupt control signal, and a second history for storing a history of the content of the interrupt control signal stored in the interrupt control signal storing means. The interrupt control device according to claim 1, further comprising: a holding unit. 4. When the interrupt request signal does not change between generation of the interrupt request signal by the mask setting means and release of the interrupt request signal after generation of the interrupt request signal, The interrupt control device according to claim 2, further comprising a notification unit configured to notify the processor that an abnormality has occurred in the interrupt control device. 5. An interrupt control for generating an interrupt control signal of which priority is set based on an interrupt request signal from an input / output device and verifying a series of interrupt controls for performing an interrupt process by a processor. In the verification method, a pseudo signal generating step of generating a pseudo interrupt control signal that simulates an interrupt control signal generated by each interrupt request signal while masking all the interrupt request signals; A software verifying step of causing the processor to perform an interrupt process using the pseudo interrupt control signal generated by the processor and verifying software of the processor. 6. An interrupt control for generating an interrupt control signal of which priority is set based on an interrupt request signal from an input / output device and verifying a series of interrupt controls for causing a processor to execute an interrupt process. In the verification method, a mask setting step of masking each interrupt request signal in accordance with the priority of the interrupt request signal; and temporarily storing the presence / absence of each interrupt request signal; A holding step of holding a history, and a hardware verification step of verifying hardware related to the input / output device based on an interrupt processing result of the processor and a history of the holding step. Control verification method. 7. A history holding step of temporarily storing the pseudo interrupt control signal or the content of the interrupt control signal, and holding a history of the content of the pseudo interrupt control signal or the interrupt control signal; 7. A signal generation verifying step for verifying generation of the pseudo interrupt control signal or the interrupt control signal based on the history held by the holding step, and further comprising: Control verification method. 8. An interrupt control for generating an interrupt control signal with a priority set based on an interrupt request signal from an input / output device and verifying a series of interrupt controls for causing a processor to execute an interrupt process. In the verification method, after the interrupt request signal is generated, a monitoring step of monitoring a change in the interrupt control signal between a time when the interrupt request signal is masked by the mask setting means and a time when the interrupt request signal is unmasked. And a notifying step of notifying the processor that an abnormality has occurred when the interrupt request signal does not change in the monitoring step.