JP2000261416A - Duplex data transfer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the necessity of a buffer for storing all data and to reduce the scale and price of a circuit by providing a data selection circuit with a pair of shift buffers to which data are successively inputted and executing parity check in each data of fixed bytes and in each vertical parity byte. SOLUTION: The data selection circuit 24 is provided with shift buffers (memories) 30a, 30b of multi-stage constitution respectively connected to data inputs 1, 2 making a pair. The circuit 24 is also provided with a parity check circuit 34 for receiving outputs from respective stages of the buffers 30a, 30b as inputs and inputting a parity check timing signal 33 from a counter 32. Data to be checked as duplex data streams and vertical parities are stored in respective shift buffers 30a, 30b, and when the parity check timing signal 33 is validated, the vertical parities of both the data streams are checked by the circuit 34.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer circuit, and more particularly to a duplicated data transfer circuit having a data check function using vertical parity.

[0002]

2. Description of the Related Art Conventionally, this type of duplicated data transfer circuit can perform correct data transfer without system down or data retransmission even if one of the data or the data transfer path fails during the data transfer. It is used for the purpose of being

Such a conventional technique is disclosed in, for example,
-83603, "Data communication method and apparatus",
JP-A-6-95901 discloses a "method of detecting a transmission error in non-procedural communication" and JP-A-56-101700 discloses a "ROM failure diagnosis method".

[0004] However, in the "data communication method and apparatus" of Japanese Patent Application Laid-Open No. 9-83603, a plurality of pieces of transfer data which are divided into data and each of which is given a parity are transferred in parallel, and , Check that normal data is extracted, and then combine by parity. This prior art is not a duplex circuit because it divides data and transfers a plurality of data in parallel. Therefore, in this prior art, it is necessary to issue a retransmission request for data in which an error has occurred.

The other two prior arts are the same as the present invention in that data is divided into fixed bytes and a vertical parity is inserted. However, in these prior arts, although error detection can be performed by parity check, it is necessary to retransmit data in which an error has occurred. Therefore, these three prior arts differ from the present invention in processing after transferring data and detecting an error.

FIG. 5 shows a format of a data stream in the conventional duplex data transfer. Where S
(Start) indicates the beginning of the data stream. D
1 to Dn indicate data to be transferred. P indicates the vertical parity of the data. E (end) indicates the end of the data stream.

Next, a conventional data transfer and selection method will be described. As shown in FIG. 2, the data is generated from the data transmitting unit 21 and output to the data receiving unit 25. Here, the data stream is duplicated by the data duplication circuit 22 to ensure reliability. The duplicated data passes through two different transmission paths (circuits, cables, etc.) 23 and reaches the data selection circuit 24. The data that has reached the data selection circuit 24 is checked for the vertical parity for each data stream, and one of the data determined to be correct is replaced with the data selection circuit 24.
And the data is sent to the data receiving unit 25. At this time, the data selection circuit 24 requires a data holding buffer memory corresponding to the number of data of the data stream.

[0008]

The above-mentioned prior art has several problems. First, there is a problem that the circuit becomes large-scale. The reason is that a buffer memory for holding both data streams is required in order to check and select a duplicated data stream based on vertical parity. The capacity of this buffer memory increases in proportion to the data stream length.

Second, there is a problem that the delay time required for the data stream transmitted from the data transmitting section to reach the data receiving section increases. The reason is that the duplicated data stream is checked and selected based on the vertical parity transmitted last, so that it is necessary to stop the data without being transmitted until that time.

Third, the longer the data length, the lower the reliability. The reason is that the parity check checks whether the number of “1” in the data is an even number (even number parity) or an odd number (odd number parity). This is because detection becomes impossible. Therefore, the greater the number of data to be checked, the higher the probability of inversion of the even number of data and the lower the reliability.

Therefore, one of the objects of the present invention is to provide a duplicated data transfer circuit having a small circuit scale.

Another object of the present invention is to provide a duplicated data transfer circuit in which the delay time of a data stream when checking data by vertical parity is small.

Still another object of the present invention is to provide a duplicated data transfer circuit with high transfer data reliability.

[0014]

In order to solve the above-mentioned problems, a duplicated data transfer circuit according to the present invention employs the following characteristic configuration.

(1) A duplicated data transfer circuit for duplicating data to be transferred by a data duplication circuit, transferring the data through different transmission paths, selecting any correct data by a data selection circuit, and outputting the selected data to a data receiving unit. The data is in a data stream format in which a vertical parity byte is inserted for each fixed byte, and the data selection circuit has a pair of shift buffers to which the duplicated data is sequentially input, and the data of the fixed byte and Duplex data transfer circuit that performs parity check for each vertical parity byte.

(2) The data selection circuit receives, in addition to the pair of shift buffers, a counter for counting an operation clock of the shift buffer and a parity check timing signal from the counter, and stores the parity check timing signal in the shift buffer. The dual data transfer circuit according to the above (1), comprising: a parity check circuit for performing a parity check of the read data; and a select circuit for selecting a correct one of the pair of shift buffers according to a select signal from the parity check circuit.

(3) The duplex data transfer circuit according to (1), wherein 4 bytes are selected as the fixed bytes.

(4) The duplex data transfer circuit according to (2), wherein the counter is connected to an output side of a first stage of the pair of shift buffers, and is enabled when the head of the data stream is recognized.

(5) The dual data transfer circuit according to the above (2), wherein the counter repeatedly counts the total number of the fixed byte number and the vertical parity byte of the data stream.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure and operation of a preferred embodiment of a duplicated data transfer circuit according to the present invention will be described below in detail with reference to FIGS.

First, FIG. 1 shows a configuration example of a data stream in a duplicated data transfer circuit according to the present invention. In the present invention, one byte of vertical parity is inserted for a fixed number of bytes in the data stream, for example, one byte is inserted for four bytes of data in the example of FIG. FIG.
S is a signal representing the beginning of data, D1 to DN are data, P1 to Pn are parity, and E is a signal representing the end of data. These vertical parities P1 to Pn are vertical parities for the first 4 bytes of each vertical parity data. That is, P1 is a parity of D1 to D4, P2 is a parity of D5 to D8, and so on. These vertical parities make it possible to check data of 4 bytes each.

Therefore, 4 bytes of data and 1 vertical parity
Data can be checked every five bytes in total, and one of the duplicated data can be selected and output to the data receiving unit.

Next, a data transfer procedure of the data stream shown in FIG. 1 will be described with reference to FIG. A data stream having the format shown in FIG. 1 is transmitted from the data transmission unit 21 to the data reception unit 25. Data sending unit 2
The data stream transmitted from 1 is duplicated by the data duplication circuit 22. Data from the duplicated data duplication circuit 22 passes through two transmission paths 23 having the same configuration, and both data arrive at the data selection circuit 24. Both data from both transmission paths 23 are transmitted to data selection circuit 2
When the data arrives at 4, the data parity circuit 24 checks the vertical parity, and any one of the correctly transmitted data is selected and transferred to the data receiving unit 25.

FIG. 3 is a detailed block diagram of the data selection circuit 24. The data selection circuit 24 has multi-stage shift buffers (memory) 30a and 30b connected to a pair of data inputs 1 and 2, respectively. In this specific example, the shift buffers 30a and 30b have a five-stage configuration. The first stage of these two shift buffers 30a and 30b and 2
A counter 32 is connected between the stages. Further, it has a parity check circuit 34 which receives as input the output of each stage of both shift buffers 30a and 30b and receives a parity check timing signal 33 from the counter 32. Further, a select circuit 36 is connected to the output side of both shift buffers, and a shift signal 30a or 3 is supplied by a select signal 35 from a parity check circuit 34.
0b is selected and output to the data receiving unit 25 (see FIG. 2) as a data output.

Next, the operation of the duplicated data transfer circuit according to the present invention, in particular, the operation of the data selection circuit 24 will be described with reference to FIGS. The duplicated data duplicated by the data duplication circuit 22 and transmitted via the transmission paths 1 and 2 of the transmission path 23 are simultaneously input to the data inputs 1 and 2 of the pair of shift buffers 30a and 30b of the data selection circuit 24. . Upon recognizing that the head data of these data streams has arrived, the counter 32 starts operating. The counter 32 is used to detect the position of the vertical parity (timing for performing the parity check).

The data stream arriving at the data selection circuit 24 is shifted in sequence from the leading S to the shift buffers 30a,
0b. These shift buffers 30a, 30b
In each row, data to be checked (D1 to DN)
And the vertical parities (P1 to Pn) are stored. It is assumed that the shift buffers 30a and 30b have a buffer memory of the number of bytes required for the check (5 bytes for the data stream in FIG. 1).

When the data (eg, D1 to D4) to be checked and the vertical parity (eg, P1) of the duplicated data stream are stored in each of the shift buffers 30a and 30b, the counter 32 is a parity check timing. Then, the parity check timing signal 33 is validated. When the parity check timing signal 33 becomes valid, the parity check circuit 34 checks the vertical parity of both duplexed data streams.

The parity check circuit 34 checks the vertical parity of both data streams, determines which one is correct, sends a select signal 35 to the select circuit 36, and selects the correct data of the shift buffer 30a or 30b. Select a stream. The select signal 35 remains fixed until all the data to be checked is transferred to the data receiving unit 25.

The above-described series of operations is repeated as long as the transfer of all data in 5-byte units continues. As a result, even if a failure occurs in any one of the duplicated data or the transmission path 23, normal data is always transferred to the data receiving unit 25, and communication reliability is maintained. You. Here, each shift buffer 30a, 3
Note that the delay between the input data input to 0b and the data output from the select circuit 36 is minimized.

Next, FIG. 4 shows the data selection circuit 2 described above.
4 is an operation timing chart of FIG. In FIG. 4, (a) is a clock for sequentially shifting the shift buffers 30a and 30b. (B), (c), (d), (e), and (f) are 5 stages from the first stage of the shift buffer 30a.
This is the shift buffer output up to the stage. (G)-(k)
Are shift buffer outputs from the first stage to the fifth stage of the shift buffer 30b. (L) is a counter enable (count_en) signal 41 for enabling the counter 32. As described above, the counter enable signal 41 is enabled when the shift buffers 30a and 30b recognize the leading data S of the data stream, and starts the counting operation. Next, (m) shows the counter 3
A count value 42 of 2 is counted up from “0” to “4” at each clock, and the counting from “0” to “4” is repeated again.

As is apparent from FIG. 4, when the count value 42 of the counter 32 is "4", each shift buffer 30
Since four data (for example, D1 to D4) and a vertical parity (for example, P1) are stored in the fifth stage from the first stage of a and 30b, the parity check circuit 34 performs a parity check at this point, and FIG. A select signal 35 shown in (n) is output. The select signal 35 is sent from the select circuit 36 to the data receiving unit 25 by the shift buffer 30.
Determining which data stream to output, a or 30b, is as described above. Either correct data stream, that is, a data stream having a correct parity check result and no error is selected. If both data streams are correct, it does not matter which one is selected, but it is preferable to determine beforehand the data stream on the shift buffer 30a side (or 30b side).

When all data transfer is completed and E is recognized in the data stream, the counter enable (count) is enabled.
t_en) 41 becomes invalid, and the data transfer operation ends.

The configuration and operation of the preferred embodiment of the duplex data transfer circuit according to the present invention have been described in detail. But,
It can be understood that this is merely an example of the present invention, and various modifications can be made without departing from the gist of the present invention. For example, in the examples of FIGS. 1 and 3, one byte of vertical parity is inserted for every four bytes of data.
Thus, the shift buffer of the data selection circuit can be made relatively small. However, when the number of the vertical parities is increased, the data transfer efficiency is reduced. Therefore, the format of the optimum data stream should be determined in consideration of the data transfer efficiency, the data transfer reliability, and the scale of the data selection circuit, and it should be understood by those skilled in the art that the format should not be limited to the format of FIG. Easy to understand.

[0034]

As will be understood from the above description, according to the dual data transfer circuit of the present invention, the following various remarkable effects can be obtained.

First, data is checked without requiring a buffer for holding all data. For example, since only a 5-byte shift buffer is required, the circuit scale can be reduced, and the circuit can be reduced in size and inexpensive.

Second, there is no need to wait for all data to arrive for checking and selecting data for each block (for example, 5 bytes), and the delay from data input to output is minimized.

Third, by duplicating the data,
Even if a failure occurs in one of the transmission systems, there is no need to retransmit data, it is possible to continue transmitting correct data, and parity check is performed for each data block instead of checking all data. Since the probability of erroneous data is reduced, the reliability of transferred data is high.

[Brief description of the drawings]

FIG. 1 is a format example of a data stream in a redundant data transfer circuit according to the present invention.

FIG. 2 is a schematic block diagram of a duplicated data transfer circuit that transfers data of the data format shown in FIG.

FIG. 3 is a detailed block diagram of a data selection circuit used in the duplicated data transfer circuit shown in FIG.

FIG. 4 is an operation timing chart of the data selection circuit shown in FIG. 3;

FIG. 5 is a format example of a data stream in a conventional duplex data transfer method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 21 Data transmission part 22 Data duplication circuit 23 Transmission path 24 Data selection circuit 25 Data reception part 30a, 30b Shift buffer 32 Counter 34 Parity check circuit 36 Select circuit

Claims (5)

[Claims] 1. A duplicated data transfer circuit for duplicating data to be transferred by a data duplication circuit, transferring the data through different transmission paths, selecting one of correct data by a data selection circuit, and outputting the selected data to a data receiving unit. Data is,
The data selection circuit has a pair of shift buffers into which the duplicated data is sequentially input, and has a data stream format in which vertical parity bytes are inserted every fixed bytes. A redundant data transfer circuit for performing a parity check. 2. The data selection circuit receives a counter for counting an operation clock of the shift buffer in addition to the pair of shift buffers and a parity check timing signal from the counter, and stores the parity check timing signal in the shift buffer. 2. A parity check circuit according to claim 1, further comprising: a parity check circuit that performs a parity check of data; and a select circuit that selects a correct one of the pair of shift buffers according to a select signal from the parity check circuit. Redundant data transfer circuit. 3. The duplex data transfer circuit according to claim 1, wherein 4 bytes are selected as said fixed bytes. 4. The duplex data transfer circuit according to claim 2, wherein said counter is connected to an output side of a first stage of said pair of shift buffers, and is enabled when a head of said data stream is recognized. . 5. The duplex data transfer circuit according to claim 2, wherein said counter repeatedly counts said fixed number of bytes of said data stream and a total count of said vertical parity bytes.