JP2000101421A - Programmable device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a self-reconfiguration function to the programmable device. SOLUTION: This programmable device is provided with a programmable logic section 20, a trigger condition discriminating section 31, that counts number of times of basic triggers having a prescribed value of signals from the programmable logic section 20 synchronously with a clock and generates a final trigger signal when the counted number of times reaches a setting value, a circuit information selecting section 32 that decides revision of the circuit configuration, based on the current circuit configuration of the programmable logic section 20 and on the generation of the final trigger signal or its sequence, and a configuration control section 33 that reads configuration information, based on the decision so as to revise the circuit configuration of the programmable logic section 20. The state of the programmable logic section 20 is stored in a variable storage section before the revision of the circuit configuration of the programmable logic section 20 and the initial state of the programmable logic section 20 after the revision of the circuit configuration of the programmable logic section 20 is set, based on the stored value.

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FPGA (Field
Programmable Gate Array (PLD) and Programmable Logi (PLD)
c)), and a programmable device having a programmable hardware configuration.

2. Description of the Related Art Since a programmable device of this kind can realize different functions according to a program like a computer, it is versatile and its design can be easily changed. Unlike a computer program, a program of a programmable device is for configuring hardware by changing the connection of elements, so that a circuit configured with a programmable device can perform high-speed processing. . For example, an FPGA device is connected to a microprocessor without a multiplication circuit, the number of multiplications executed by software is counted during execution of the program, and when the counted value exceeds a set value, the program is loaded into the FPGA device and a hardware multiplication circuit is executed. Then, an apparatus has been proposed which executes multiplication at high speed by switching multiplication by software to multiplication by an FPGA device and performs the same for other operations (Japanese Patent Laid-Open No. 8-46509). ). Thus, by dynamically configuring a programmable device such as an FPGA device, it becomes possible to execute many functions at high speed with one programmable device.

However, it is not possible to judge reconfiguration or execute reconfiguration by the programmable device itself.
If this becomes possible, the programmable device itself becomes multifunctional, the system including the programmable device can be simplified, the cost can be reduced, and the use of the programmable device is expanded. An object of the present invention is to provide a programmable device having a self-reconfiguration function in view of such a problem.

According to a first aspect of the present invention, there is provided a programmable device comprising: a programmable logic unit; and a signal necessary for determining a change in the circuit configuration of the programmable logic unit is supplied from the programmable logic unit. The circuit includes a circuit configuration change determination unit that determines a circuit configuration change based on a signal, and a configuration control unit that reads configuration information based on the determination and changes the circuit configuration of the programmable logic unit. According to this programmable device, the reconfiguration judgment and reconfiguration are performed by the programmable device itself, so that the system using the programmable device is simplified and the cost is reduced, and the use of the programmable device is expanded. The contribution is great. In the programmable device according to the second aspect, in the first aspect, the circuit configuration change determination unit counts the number of basic triggers in which the signal is a predetermined value in synchronization with a clock, and the counted number becomes a set value. A trigger condition judging unit for generating a final trigger signal at the time of occurrence, and a circuit information selecting unit for deciding the circuit configuration change based on the generation of the final trigger signal. Claim 3
In claim 2, the clock is an operation clock or a timer clock of the programmable logic unit. According to a fourth aspect, in the second or third aspect, the circuit information selection unit determines which circuit configuration should be changed based on the current circuit configuration of the programmable logic unit and the generation of the final trigger signal. . According to this programmable device,
Further multifunctionalization is achieved. According to a fifth aspect of the present invention, in the second or third aspect, the circuit information selecting unit is configured to select a circuit configuration to be changed based on a current circuit configuration of the programmable logic unit and a generation order of the plurality of final trigger signals. To determine. According to a sixth aspect of the present invention, there is provided the programmable device according to any one of the first to fifth aspects, wherein a state of the programmable logic unit is stored before the circuit configuration of the programmable logic unit is changed, and a stored value of the state of the circuit is stored. There is further provided a variable storage unit for setting an initial state of the circuit after the change. According to this programmable device, the circuit operation can be appropriately changed according to the initial state setting, so that more detailed processing can be performed. According to a seventh aspect of the present invention, in the programmable device according to any one of the first to sixth aspects, the configuration control unit reads predetermined configuration information in response to an external signal to change a circuit configuration of the programmable logic unit. A predetermined circuit configuration is forcibly set. According to this programmable device, the function of the programmable device can be changed more flexibly. In the programmable device according to claim 8, in claim 7, the external signal is:
Generated in response to power up. In the programmable device according to the ninth aspect, in the third aspect, the trigger condition determination unit determines whether or not the value of the signal matches a set value and outputs a match signal. A counter that counts the clock when it indicates a match and outputs the final trigger signal when the count reaches a predetermined value. 11. The programmable device according to claim 10, wherein the counter has a cycle counter for counting the operation clock and a timer counter for counting the timer clock, and outputs the coincidence signal to the cycle counter and the timer. A first switch for selectively supplying one of the counters and an output of the cycle counter and an output of the timer counter in conjunction with the first switch to output the final trigger signal. 2 changeover switch.

Embodiments of the present invention will be described below with reference to the drawings. First Embodiment FIG. 1 shows an FPGA device 10 having a self-reconfiguration function and a configuration memory 40 storing a program (configuration information) for achieving each function of the FPGA device 10. It is a functional block diagram shown. This FP
The GA device 10 is used for data processing or control, for example, and is incorporated in a computer system. FP
The GA device 10 includes a programmable logic unit 20 whose function is variable by a program and a fixed circuit unit 30 whose function is fixed. Fixed circuit section 30
May or may not be programmable like the programmable logic unit 20. Signals SI1 to SIp are externally supplied to the programmable logic unit 20, and a signal SO
1 to SOq are output. Programmable logic unit 2
Among the signals in 0, a signal at M points necessary for determining the circuit configuration change is extracted, and the trigger condition determination unit 3 of the fixed circuit unit 30
1 is supplied. The trigger condition determination unit 31 is, for example, as shown in FIG.
As shown in (1), when the input signal A is at a low level (L), it is determined to be the basic trigger 1, and when this is repeated 100 times, a signal of the final trigger 1 is generated and supplied to the circuit information selection unit 32. The trigger condition determination unit 31 also determines that the input signal B is the basic trigger 2 when the input signal B is at a high level (H).
When the total time becomes 250 μS, a signal of the final trigger 2 is generated and supplied to the circuit information selection unit 32. The trigger condition determination unit 31 further determines that the value on the bus C is 3Fh (h is 1
When it is a hexadecimal number), it is determined to be the basic trigger 3, and when this is repeated 50 times, a signal of the final trigger 3 is generated and supplied to the circuit information selection unit 32. FIG. 2 shows the same contents for the basic triggers 4 and 5. The trigger condition determination unit 31 includes a trigger condition determination unit 31U as shown in FIG. 4 for each input signal. The basic trigger set value 311 is, for example, an L level ('0') which is a condition of the basic trigger 1 in FIG.
This set value is the content of the flip-flop or the potential of the ground wiring. The comparator 312 has the basic trigger set value 3
11 is compared with the signal from the programmable logic unit 20, and when they match, a matching signal whose output is set to a high level is output as a basic trigger. FIG.
When the last trigger condition of the is the number of cycles, the changeover switches 313A and 313B
And the cycle counter 314 is used. When the final trigger condition is the total time, the changeover switches 313A and 313B are switched to the timer counter 315 side, and the timer counter 315 is used.
When the final trigger condition is the number of cycles, the cycle number setting value 316 is used, and when the final trigger condition is the total time, the timer setting value 317 is used. Outputs of AND gates 318 and 319 are supplied to a clock input terminal CK of the cycle counter 314 and the timer counter 315, respectively. An operation clock (or system clock) of the programmable logic unit 20 is supplied to one input terminal of the AND gate 318, and a timer clock is supplied to one input terminal of the AND gate 319. The output of the comparator 312 is supplied via a changeover switch 313A to the other input terminal of the AND gate 318 when the cycle counter 314 is used, and to the other input terminal of the AND gate 319 when the timer counter 315 is used. It is supplied to the input end. When the configuration of the programmable logic unit 20 is completed, when the cycle counter 314 is used, the cycle number setting value 3
16 is loaded into the cycle counter 314 as an initial value, and when the timer counter 315 is used, the timer set value 317 is loaded into the timer counter 315 as an initial value. Both the cycle counter 314 and the timer counter 315 are down counters. If the cycle counter 314 is used and the output of the comparator 312 indicates a match, the operation clock is
The clock signal is supplied to the clock input terminal CK of the cycle counter 314 via 18 and its count value is decremented. When the count value of the cycle counter 314 becomes 0 and then becomes -1, an overflow signal is taken out as a final trigger signal via the changeover switch 313B. Similarly, when the timer counter 315 is used, if the output of the comparator 312 indicates a match, the timer clock is supplied to the clock input terminal CK of the timer counter 315 via the AND gate 319, and the count value is output. Is decremented. When the count value of the timer counter 315 becomes 0 and then becomes -1, the overflow signal is taken out as the final trigger signal via the changeover switch 313B. Returning to FIG. 1, the circuit information selection unit 32 determines whether the currently functioning circuit configuration of the programmable logic unit 20 is any of the circuits 1 to N, the condition of generation of the final trigger or the sequence thereof. Based on the programmable logic unit 2
It is determined which circuit configuration should be changed to 0. For example, as shown in FIG. 2, when the programmable logic unit 20 is the current circuit 1 and the last trigger 2 or 3 occurs, and then the last trigger 1 occurs, the circuit information selecting unit 32 changes to the circuit 5. Decide what to do. When the programmable logic unit 20 is the current circuit 1 and the final trigger 4 or 5 is generated, the circuit information selecting unit 32 determines that the circuit 3 should be changed. FIG. 2 also shows other circuit configuration changes. FIG. 3 is a state transition diagram between circuit configurations related to FIG. FIG. 3 shows a case where the FPGA device 10 is used for data processing. The circuit 1 performs a file search process, the circuit 2 performs a transfer process of the searched file, the circuit 3 performs an error process, and Reference numeral 5 is for performing a search result display process. When determining that the circuit i should be changed to the circuit i (i is any one of 1 to N), the circuit information selection unit 32 activates a circuit i determination signal and supplies it to the configuration control unit 33. When it is determined that the circuit i should be changed to the circuit i, the configuration control unit 33 reads the circuit information #i from the configuration memory 40 and loads the circuit information #i into the programmable logic unit 20 to reload the programmable logic unit 20. Configure. When the fixed circuit unit 30 is programmable, the configuration information is loaded into the programmable logic unit 20 so as not to affect the configuration of the fixed circuit unit 30. According to the above-described FPGA device, the reconfiguration determination and the reconfiguration are performed by the FPGA device itself, so that the system using the FPGA device is simplified and the cost is reduced, and the FPGA device is used. It greatly contributes to expanding applications. During the configuration, input / output processing cannot be performed, so the configuration control unit 33 supplies a busy signal BUSY to a main CPU (not shown) to temporarily suspend the processing. When it is necessary to set the initial state after the configuration of the programmable logic unit 20, the state of the programmable logic unit 20 is stored in the variable storage unit 34 immediately before the configuration, and the information is stored in the programmable storage immediately after the configuration. The logic unit 20 is loaded into the programmable logic unit 2
Initialize 0. With this configuration, the circuit operation can be appropriately changed according to the initial state setting, so that more detailed processing can be performed. When the load signal LOAD is supplied to the configuration control unit 33 upon power-on or in response to a request from the main CPU, predetermined circuit information is stored in the programmable logic unit 2.
0 to force the configuration. At this time, a circuit j determination signal (j is any one of 1 to N)
To the configuration control unit 33 at the same time
The configuration of the circuit j may be supplied from U. In this way, F
The function of the PGA device can be changed. The configuration memory 40 is a ROM or a RAM. In the case of the RAM, for example, the work RAM of the CPU may be shared. In the configuration memory 40, for example, as shown in FIG. 5, circuit information is stored in each divided storage area. The chip select signal CS, the output enable signal OE, and the address ADR are supplied from the FPGA device 10 to the configuration memory 40.
The device 10 is supplied with data DATA. The chip select signal CS is activated, the configuration memory 40 is selected, and the data read operation is started by the supply of the address ADR. When the output enable signal OE is activated, the parallel data DATA is supplied to the FPGA device 10. Parallel data DATA is FPGA
The signal is converted into a serial signal by the parallel / serial conversion circuit 101 in the device 10 and supplied to the program storage unit for the programmable logic unit 20. FIG. 6 shows a modification of FIG. The configuration memory 40A includes configuration ROMs 40A1 to 40AN for each circuit configuration to be configured. For each of i = 1 to N, the chip select signal CSi is supplied from the FPGA device 10 to the configuration ROM 40Ai. An output enable signal OE and a clock CLK are supplied from the FPGA device 10 to the configuration ROMs 40A1 to 40AN via the bus, and a clock CLK is supplied from the selected one of the configuration ROMs 40A1 to 40AN to the FPGA device 10 via the bus. Synchronized data DATA is supplied. The present invention also includes various modified examples. For example, in FIG. 4, only one pair of a counter and an AND gate may be used, and one of the timer clock and the operating clock may be selectively supplied to the AND gate without using the changeover switches 313A and 313B. Further, an asynchronous counting method may be used in which the output of the comparator 312 is supplied to the clock input terminal CK of the counter 314 via the changeover switch 313A without using the AND gate 318. Further, instead of the FPGA device, the function described above may be achieved by using another programmable device whose hardware configuration is programmable. Further, since the fixed circuit unit 30 does not have to be programmed with a programmable circuit, a part or all of the
A configuration in which the device is provided outside the programmable device and connected to the programmable device (a programmable device as a whole connected configuration) may be used. In this case, although the number of components increases, the same function can be achieved.

[Brief description of the drawings]

FIG. 1 shows an F with a self-reconfiguration function
FIG. 2 is a functional block diagram illustrating a PGA device and a configuration memory.

FIG. 2 is a table showing functions of a trigger condition determination unit and a circuit information selection unit in FIG.

FIG. 3 is a state transition diagram between circuit configurations related to FIG. 2;

FIG. 4 is a circuit diagram illustrating a configuration example of a trigger condition determination unit.

FIG. 5 is a connection diagram between an FPGA device and a configuration memory.

FIG. 6 is a diagram showing a modification of FIG. 5;

[Explanation of symbols]

 Reference Signs List 10 FPGA device 20 Programmable logic unit 30 Fixed circuit unit 31 Trigger condition determination unit 32 Circuit information selection unit 33 Configuration control unit 34 Variable storage unit 40, 40A Configuration memory 40A1, 40Ai Configuration ROM 31U Trigger condition determination unit 311 Basic trigger Set value 312 Comparator 313A, 313B Changeover switch 314 Cycle counter 315 Timer counter 316 Number of cycles set value 317 Timer set value 318, 319 AND gate ADR Address DATA data CS, CS1 Chip select signal OE Output enable signal 101 Parallel / direct conversion circuit CK clock input terminal

Claims (10)

[Claims] 1. A programmable logic unit, and a signal required for determining a change in circuit configuration of the programmable logic unit is supplied from the programmable logic unit.
A circuit configuration change determination unit that determines a circuit configuration change based on the signal; and a configuration control unit that reads configuration information based on the determination and changes the circuit configuration of the programmable logic unit. Programmable device. 2. The circuit configuration change determining section counts the number of basic triggers whose signal is a predetermined value in synchronization with a clock, and generates a final trigger signal when the counted number reaches a set value. The programmable device according to claim 1, further comprising: a trigger condition determination unit; and a circuit information selection unit that determines the change of the circuit configuration based on the generation of the final trigger signal. 3. The programmable device according to claim 2, wherein the clock is an operation clock or a timer clock of the programmable logic unit. 4. The circuit information selector according to claim 1, wherein a circuit configuration to be changed is determined based on a current circuit configuration of the programmable logic unit and generation of the final trigger signal. 4. The programmable device according to 2 or 3. 5. The circuit information selecting section determines which circuit configuration should be changed based on the current circuit configuration of the programmable logic section and the generation order of the plurality of final trigger signals. The programmable device according to claim 2 or 3, wherein: 6. A variable storage unit for storing a state of the circuit before changing the circuit configuration of the programmable logic unit, and setting an initial state of the circuit after changing the circuit configuration of the programmable logic unit using the stored value. The programmable device according to any one of claims 1 to 5, further comprising: 7. The configuration control section reads predetermined configuration information in response to an external signal and forcibly changes the circuit configuration of the programmable logic section to a predetermined circuit configuration. Item 7. The programmable device according to any one of Items 1 to 6. 8. The programmable device according to claim 7, wherein said external signal is generated in response to power-on. 9. The trigger condition determination section determines whether or not the value of the signal matches a set value and outputs a match signal. If the match signal indicates a match, 4. The programmable device according to claim 3, further comprising: a counter that counts a clock and outputs the final trigger signal when the count value reaches a predetermined value. 10. The counter has a cycle counter that counts the operation clock and a timer counter that counts the timer clock, and selectively outputs the coincidence signal to one of the cycle counter and the timer counter. A first changeover switch to be supplied, and a second changeover switch that selects one of the output of the cycle counter and the output of the timer counter in conjunction with the first changeover switch and outputs the selected output as the final trigger signal. The programmable device according to claim 9, wherein: