JP2000091435A - Electronic data processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic data processing system that enables efficient processing by keeping track of the state of logical cells which is used on a programmable logic circuit. SOLUTION: This electronic data processing system executes a series of processings described by a program, at least part of which can be processed by programmable logic circuits, and has a plurality of logic cells as programmable logic circuits. By configuring circuit information in logic cells in the specified area from among plurality of cells, new logic circuits are provided in the specified area. There is provided a logic cell state memory 30, That stores information reflecting each state of a plurality of logic cells in the programmable logic circuit. From among the information stored in the logic cell state memory 30, information STD which reflects the state of the logic cells configured is updated, each time new circuit information is configured.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing system capable of processing at least a part of a processing by a programmable logic circuit whose circuit configuration can be partially reconfigured, and more particularly to a programmable logic circuit. About the effective use of

[0002]

2. Description of the Related Art In the field of digital logic circuit products, especially application-specific integrated circuits (ASICs), in order to shorten the development period of the products, they are composed of a field programmable gate array (FPGA) or a programmable logic device (PLD). Programmable logic circuits are widely used.

[0003] These programmable logic circuits can freely configure internal logic circuits and connections between the logic circuits by reading circuit information describing the logic circuits. For this reason, the use of the programmable logic circuit has an advantage that the time required to manufacture an integrated circuit, which conventionally required several weeks to several months after the completion of circuit design, is not required.

In particular, a programmable logic circuit which can be electrically reconfigured by using an SRAM or the like as an input of a switch for determining the function of a logic cell as in the invention of US Pat. No. 4,700,187 is a circuit once manufactured. The advantage is that programmable logic circuits can be freely changed as many times as necessary, and programmable logic circuits are becoming more and more widely used.

[0005] Recently, logic circuits have increased in complexity, and the circuit scale has increased to a scale that cannot be realized by a single programmable logic circuit. One method for solving this problem is to connect and use a plurality of programmable logic circuits.

However, since the number of input / output connections of the programmable logic circuit is limited, it is difficult to realize all the logic circuits by this method. Further, even if it can be realized, a new disadvantage that power consumption increases with the increase in the number of programmable logic circuits to be used is caused.

As another solution, it has been proposed to reconfigure a programmable logic circuit in the middle of processing in order to realize different logic circuits at different times. This method has an advantage that various processes can be performed at a relatively high speed even when the size of a built-in circuit is limited because the device is small like a portable information terminal.

However, in this case, there is a disadvantage that extra time is required for rereading the circuit information when reconfiguring the circuit in the programmable logic circuit. Furthermore, reconfiguring in the middle of the process means that the process is temporarily suspended, the data at that time is stored in a storage device outside the programmable logic circuit, new circuit information is read and reconfigured, and the data before the reconfiguration is performed. And extra processing of inputting new data accompanying the reconstruction is required.

In order to solve this problem, a programmable logic circuit described in a data book named "CONFIGURABLE LOGIC" by Atmel, USA, has a data storage device (SRAM) for storing data when performing reconfiguration. During the operation of the circuit, a part of the circuit information is read from the external storage device and partially reconfigured to minimize the time required for the reconfiguration.

[0010]

However, when a plurality of different logic circuits are formed on the programmable logic circuit at different times by using such a partially reconfigurable programmable logic circuit, a conventional technique has been proposed. In the application software using the programmable logic circuit, the position of the logic cell used as a circuit on the programmable logic circuit was unknown, so the circuit to be reconfigured, for example, It is necessary to configure as a reference, and a plurality of circuits are configured to be overlapped on the same part on the programmable logic circuit.

For example, as shown in FIG. 14, a case is considered in which two circuits A and B are configured on a programmable logic circuit in the order of circuit A → circuit B → circuit A to perform processing. In this case, the circuit A includes, as shown in FIG.
An area based on, for example, the lower left corner of the circuit configuration area FL of the programmable logic circuit is configured on the programmable logic circuit. Then, when the processing in the circuit A is completed, the circuit B then performs, as shown in FIG.
Similarly, it is configured on the programmable logic circuit as an area based on the lower left corner of the circuit configuration area FL. Finally, as shown in FIG. 14C, the circuit A is again configured on the programmable logic circuit as an area based on the lower left corner of the circuit configuration area FL.

The size of a circuit to be reconfigured into a programmable logic circuit is large or small, and the size of the circuit to be reconfigured is relatively small, so that a plurality of circuits can be simultaneously formed on the programmable logic circuit. There is also. For example, in the case of the above example, the circuit A and FIG.
As shown in FIG. 4 (d), they can be simultaneously configured on the circuit configuration area FL of the programmable logic circuit.

In this case, a plurality of circuits can be simultaneously formed on a programmable logic circuit, and a circuit used once, such as the circuit A in the above-described example, is
FIG. 14 (a) shows a case of using again later.
As shown in FIG. 14D, after the circuit A is configured on the programmable logic circuit, if the circuit B can be reconfigured in an empty area of the circuit configuration area 10 as shown in FIG. Since it remains on the programmable logic circuit as it is, after the processing in the circuit B, the processing using the circuit A can be executed without reconfiguring the circuit A again.

In this manner, the time required for reconfiguring the circuit A after the circuit B can be saved, so that the overall processing time can be shortened and the processing can be performed efficiently.

However, in the conventional information processing system, as described above, the position of a logic cell used as a circuit on the programmable logic circuit is unknown on the application software side that executes processing using the programmable logic circuit. Therefore, the reconstruction as shown in FIG. 14D could not be performed.

SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide an information processing system capable of ascertaining the use state of a logic cell on a programmable logic circuit and enabling efficient processing. .

[0017]

According to a first aspect of the present invention, there is provided an information processing system for executing a series of processes in which a program is described, and at least a part of the series of processes. However, in an information processing system which can be processed by a programmable logic circuit, the programmable logic circuit has a plurality of logic cells, and among the plurality of logic cells, a logic cell in a designated area is provided with circuit information. Is configured to implement a new logic circuit in the designated area, and stores information reflecting the state of each of the plurality of logic cells of the programmable logic circuit. A state memory, wherein each time new circuit information is configured, the logic cell state Of the stored information in the memory, and updates the information reflecting the state of the configuration logical cell.

According to a second aspect of the present invention, in the first aspect, the information reflecting the state of the logic cell in the logic cell state memory is such that the circuit state of the logic cell is constituted by any number of configurations. It is characterized by including the maximum number of configuration times.

According to a third aspect of the present invention, in the information processing system according to the first or second aspect, the information reflecting the state of the logic cell in the logic cell state memory includes a circuit including the logic cell, It is characterized by including information indicating whether it is operable on the programmable logic circuit.

[0020]

According to the first aspect of the present invention, there is provided a logic cell state memory for storing information reflecting respective states of a plurality of logic cells of a programmable logic circuit. , An empty area on the programmable logic circuit can be easily grasped. Therefore, when the vacant area is larger than the circuit to be reconfigured, a new circuit can be reconfigured in the vacant area, and the efficiency of effectively utilizing the circuit resources previously configured in the programmable logic circuit can be improved. Processing can be expected.

Further, when the number of times of configuration is stored as information reflecting the state of the logic cell stored in the logic cell state memory as in the second aspect of the present invention, the configuration has been performed before as much as possible. In order to use the circuit, it is possible to set an area configuring a circuit for performing a new configuration.

In the invention according to claim 3, the information reflecting the state of the logic cell includes information indicating whether a circuit including the logic cell is operable on the programmable logic circuit. Therefore, it is possible to easily detect a previously configured circuit that is available.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an information processing system according to the present invention will be described below with reference to the drawings.

First, FIG. 2 shows a main conceptual configuration of an embodiment of an information processing system to which the present invention is applied, in which at least a part of the processing is processed by a programmable logic circuit whose circuit configuration can be reconfigured.

In the information processing system of this embodiment, a target application program (sometimes simply a program) 100 separates a series of processes to be executed by the program into a plurality of processes. Each process is configured as a module. This module is referred to as a processing module in this specification.

In this embodiment, each processing module constituting the program 100 is constituted by a software program whose processing is described in a programming language so that the CPU 500 executes the processing. This software program is called a software module SM. Therefore, in the case of this embodiment,
The application program 100 includes a set of a plurality of software modules SM.

In this embodiment, the storage device 20
0, a module HM in which the same processing as the processing performed by each of the software modules SM is described by circuit information for reconfiguring into a programmable logic circuit (this module is referred to as a hardware module in this specification) is stored and prepared. I do. The storage device 200 may be provided in the information processing system, or may be a storage device on a network.

In the case of this example, the program 100 corresponds to FIG.
As shown in (1), it is composed of a header part HED and a main part PRG, and the main part PRG is composed of a set of a plurality of software modules SM as described above. And
In the header HED, the identification code ID of the corresponding hardware module HM, which is described by circuit information for reconfiguring the same processing as each software module SM into a programmable logic circuit, is described.

In this case, the identification code ID is described in the program 100 so that the software module SM and the hardware module HM that perform the same processing are associated with each other. For example, in this example, each software module SM is arranged in the order according to the processing execution order on the program of the plurality of software modules SM of the main body PRG.
Code ID of hardware module HM corresponding to
Is described in the header section HED.

Hardware module acquisition means 300
Is the identification code ID described in the program 100
By using the hardware module HM that executes the same processing as that executed by the software module SM,
It is obtained from the storage device 200 in the system or from the storage device 200 on the network. Then, the hardware module acquisition unit 300 reconfigures the circuit based on the acquired hardware module HM on the programmable logic circuit 400.

The hardware module HM stored in the storage device 200 includes the circuit information of the programmable logic circuit 400. FIG. 4 shows the structure of this circuit information.

That is, as shown in FIG. 4, the circuit information 201 includes a header section 202 as an additional information section and a code section 203 as a circuit data section. The header section 202 includes circuit name information 204, input / output port information 205,
Area information 206 is described.

In this example, the circuit name information 204 describes, as an identifier ID of its own circuit information, a circuit name (hereinafter referred to as its own circuit name) that the circuit information 201 configures in the programmable logic circuit 400. I have. The own circuit name as the identifier ID of the own circuit information is also the name given to the circuit information 201. In this example, as will be described later, the application program 100 uses its own circuit name as an identifier ID of the circuit information as specification information of a circuit included in the programmable logic circuit 400.

The circuit name information 204 includes an identification part for distinguishing between the hardware module HM and the software module SM. In this embodiment, except for the identification part, the application program 10
The software module SM of 0 and the hardware module HM have the same identifier.

Input / output port information 205 of header section 202
Is an input (I) depending on the direction of signal flow to the circuit.
N), port type 207 selected from output (OUT) or bidirectional (IN / OUT), port position coordinates (X, Y) 2 in units of logic cells (described later) 2
08 and the data width (number of bits) 209 of the port.

The area information 206 indicates the size of a circuit formed on the programmable logic circuit 400 by the circuit information 201. For example, when the circuit configuration area is rectangular, the area information 206 is required in the vertical and horizontal directions. It is described as a combination (Nx, Ny) of the numbers Nx and Ny of the logic cells.

The code section (circuit data section) 203 is constituted by a set of pairs of an address ADR and data DT. The address ADR is an address of a configuration memory (described later) that determines the state of a logic cell or wiring configuring the programmable logic circuit 400. The data DT determines the state of a logic cell or a wiring corresponding to the written address of the configuration memory.

The software processing by the software module SM of the program 100 is executed by the CPU 500.

Actual application program 100
Is executed by the execution module determining means 600 for each processing module, selecting which of the software module SM and the hardware module HM is to be executed. In this embodiment, the execution module determining unit determines which module executes the processing module based on the execution module selection condition set in the selection condition setting unit 700.

In the selection condition setting means 700, various selection condition items such as processing time by software or hardware, memory consumption, and reconfiguration time of a programmable logic circuit are assumed in advance. Alternatively, an execution module selection condition can be set by combining a plurality of condition items. The execution module determining unit 600 selects a processing module that matches the set selection condition among the hardware module HM and the software module SM as an execution module. The information on the selection condition items for each processing module is stored in the memory of the execution module determining unit 600 in advance.

The selection condition setting means 700 is provided so that the execution module selection condition can be changed by the user. When a user decides on a certain process,
It is also possible to set which of the hardware module HM and the software module SM is used.

[Example of Hardware Configuration of Embodiment] FIG.
Is a block diagram illustrating an example of a hardware configuration of the information processing system 10 according to the present embodiment. In the information processing system 10 of this embodiment, a main memory 13 composed of, for example, a DRAM is connected to a host bus 11B of a CPU 11 via a memory controller (not shown) included in a chipset 12.

The host bus 11B is connected to a PCI bus 14 via a host-PCI bus bridge (not shown) included in the chipset 12. The PCI bus 14 is connected to a programmable logic circuit 400 via a programmable logic circuit interface 15, a hard disk drive 18 via a hard disk interface 17, and a communication interface 19.

The communication interface 19 is connected via a network 20 such as a LAN or the Internet to a storage device 21 in which circuit information reconfigured in the programmable logic circuit 400 is stored.

An application program is stored in a hard disk read / written by the hard disk drive 18. The application program may be stored in a storage device (server) on the network 20 in some cases.

The hard disk of the hard disk drive 18 may store circuit information reconfigured in the programmable logic circuit 400. In the case of this example, the hard disk read / written by the hard disk drive 18 forms a storage device in the information processing system 10.

In this embodiment, the hardware acquisition means 300 and the execution module determination means 600 are implemented as software as one function of the OS of the information processing system 10 shown in FIG.

Next, the structure of the programmable logic circuit 400 is shown in FIG. The programmable logic circuit 400 includes a logic cell 401, a wiring region 402, and an input / output terminal 403.
And Although not shown, the programmable logic circuit includes a configuration memory for storing circuit information. The configuration memory stores the EE in the logic cell 401 and the wiring area 402.
It is composed of rewritable memory elements such as PROM and SRAM.

When an address ADR is given to the configuration memory and data of new circuit information (see FIG. 4) is stored, the circuit configuration in the logic cell 401, the logic cell 401 and the input / output The connection state of the wiring region 402 that connects the terminals 403 to each other is reconfigured. This series of operations is called a configuration. By rewriting a part of the configuration memory, the circuit can be partially reconfigured even when the programmable logic circuit is operating.

Data to be processed is input to the circuit element reconfigured in the programmable logic circuit 400 via the input / output terminal 403, and the processing result is output. The application program specifies the logic cell 401 of the data input destination and the logic cell 401 of the data output source by a control code indicating the cell coordinates corresponding to the position of the logic cell.

Next, the logic cell state memory of the main part of the present invention will be described with reference to FIG. In this embodiment, as a part of the memory area of the main memory 13, as shown in FIG.
Logic cell state memory 30 including a memory area (logic cell state storage unit) 31 corresponding to each of the logic cells
Is provided.

Each of the logic cell state storage units 31 has
Logic cell state data STD as information reflecting the state of the corresponding logic cell of the programmable logic circuit is stored. In this case, the application program 100
Manages the state of each logic cell on the programmable logic circuit 400 by associating, for example, 1-byte logic cell state data STD with one logic cell. FIG. 1 is a conceptual diagram of a memory space of a logic cell state memory 30 configured in the main memory 13.

In the case of this example, an active flag AF indicating whether a circuit including a logic cell corresponding to the logic cell state data STD is operable is assigned to the first bit of the 1-byte logic cell state data STD. The remaining 7 bits include a configuration number C indicating the number of configurations of the logic cell.
No is written.

For simplicity, for example, as shown in FIG. 7, a programmable logic circuit in which 4 × 4 logic cells are two-dimensionally arranged is assumed as the programmable logic circuit 400. When a functional circuit is configured in an area surrounded by a dotted line in FIG. 7A from the initial state of the programmable logic circuit, the logic cell state of each logic cell state storage unit 31 of the logic cell state memory 30 is set. The data STD is as shown in FIG.

That is, the logic cell state data S of the logic cell in the area where the functional circuit is configured
The TD active flag AF becomes “1” indicating an active state (a state in which a circuit can be used on the programmable logic circuit 400), and the configuration number CNo represents a first configuration [ 0000001]. On the other hand, the active flag AF of the logic cell state data STD of the logic cell in the area where the functional circuit has not been configured becomes “0” indicating an inactive state, and
The configuration number CNo indicates that no configuration has been performed yet [000000].
0].

The provision of the logic cell state memory 30 allows the application program 100 to obtain basic data for determining where to configure a circuit on the programmable logic circuit 400 next. Further, in this embodiment, the configuration number CNo of the value of the data STD of each logic cell state storage unit of the logic cell state memory 30, the active flag AF, and the name of the configured circuit are associated with each other. The information is stored in the main memory 13. It can be seen that a circuit in which the active flag AF is active “1” is available on the programmable logic circuit 400.

The memory capacity required for the logic cell state memory 30 is 64 if the logic cell state data STD is 1 byte for one logic cell as in the above example.
4k for a programmable logic circuit of about 64 cells
Even a programmable logic circuit of about 128 bytes × 128 cells is about 16 kbytes, which requires relatively small memory consumption.

Next, an example of application processing in the information processing system according to this embodiment will be described with reference to FIGS.

As shown in FIG. 8, when the application program is started, a list of necessary hardware modules written at the beginning of the program and setting of variables are performed as preprocessing. (Step S101).

Next, the main processing is performed, and each processing routine is executed by using either the hardware module or the software module. That is, before execution of each processing routine, it is determined whether the routine is to be subjected to software processing by the CPU 500 or dedicated hardware is mounted on the programmable logic circuit 400 and hardware processing is performed there (step S10).
2).

As described above, this determination is made by the execution module determining means 600, but may be specified by the application program 100, or the software is already executed by another CPU at the time of execution. However, the software processing may be switched to the hardware processing on the assumption that it will take a long time.

If software processing is selected in step S102, the CPU 500 performs software processing (step S103). If hardware processing is selected, the application program 5
00 implements dedicated hardware on the programmable logic circuit 400, passes necessary parameters such as data to be processed and control variables to the programmable logic circuit 400, and performs hardware processing. Received from programmable logic circuit 400 (step S
104).

When the processing in one processing routine is completed, the process proceeds to the next processing routine, or when there is no next processing routine, this application program is terminated (step S105).

Next, the hardware processing executed in step S103 will be described. FIG. 10 and a continuation of FIG. 11 show a detailed flowchart of this hardware processing.

When the hardware processing is started, it is checked whether or not a required circuit is on the programmable logic circuit 400 by using the reference information of the main memory 13 (step S111). Whether the required circuit is on the programmable logic circuit 400 is determined by the main memory 13 and the state data ST of the logic cell state memory 30 as described above.
Since the configuration number CNo, which is D, and the active flag AF are stored in association with each other, it is easy to determine. That is, specifically, the main memory 13 searches the main memory 13 for the circuit name of the circuit in which the active flag AF of the state data STD of the logic cell state memory 30 is in the active state. Is determined based on whether or not it matches the circuit name of the above.

As a result of the determination in step S111, when it is determined that a necessary circuit exists on the programmable logic circuit 400, the processing is performed by the circuit without performing the configuration (step S123). If the necessary circuit does not exist on the programmable logic circuit 400, the circuit is changed to the programmable logic circuit 40.
In order to configure on 0, proceed to the next step S112,
The circuit information is obtained from the storage device 21 via the hard disk drive 18 or the network 20.

Next, this configuration is
A variable d for confirming the number of the configuration is initialized (step S113). Next, the logic cell state data S of the logic cell state memory 30 of the main memory 13
Referring to the TD, a configurable free area on the programmable logic circuit 400 is confirmed.

Specifically, the configuration number CNo written in the memory space corresponding to each logic cell
Confirms the area occupied by the logic cell equal to or less than the variable d (step S114). At first, since the variable d = 0, the area occupied by the logic cell of the configuration number CNo = 0 is grasped. And the size of this grasped area,
This is compared with the area occupied by the circuit, which is obtained from the area information of the circuit to be configured (step S115). As a result of this comparison, if it is determined that the area where the circuit can be configured is not empty, the value of the variable d is increased (step S116), and the process returns to step S114. If it is determined that the area where the circuit can be configured is empty, the process proceeds to the next step S117, where the circuit is rearranged.

In the process of relocating circuits in step S117, a place where a circuit in a free area of the programmable logic circuit 400 can be configured is specified, and the circuit information stored in a storage device such as the hard disk drive 18 is identified. The bit data therein is rewritten to circuit data which constitutes a specified area on the programmable logic circuit 400. Alternatively, the bit data is generated by changing the layout data in the design tool in the circuit information.

Next, the rearranged bit data is loaded from a storage device such as the hard disk drive 18 into the configuration memory of the programmable logic circuit 400 (step S118).

During the loading, the maximum value CNomax of the current configuration number CNo is set to 1 in the logical cell state storage section 31 of the logical cell state memory 30 corresponding to the logical cell to be configured.
Is written (step S119). And
The maximum value CNomax of the configuration number is updated (step S120).

Then, the active flag AF of the state data STD of the logic cell whose configuration number CNo of the logic cell state data STD stored in the logic cell state memory 30 is equal to or smaller than the variable d is reset to "0" (step S <b> 121), the circuits of these configuration numbers are disabled as circuits on the programmable logic circuit 400. Also, the active flag AF of the logic cell state data STD corresponding to the logic cell configuring the configured circuit is set to “1” (step S122), and the circuit is available on the programmable logic circuit 400. As shown.

When the configuration of the programmable logic circuit 400 is completed, processing is performed in the circuit configured in the programmable logic circuit 400 (step S123), and the processing result is returned to the application program. The hardware processing is executed as described above.

FIG. 11 is a schematic diagram showing the number of times of configuration and the update state of the data STD of each logical cell state storage unit 31 in the area of the logical cell state memory 30 of the main memory 13. In FIG. 11, for simplicity of description, the number of logic cells of the programmable logic circuit 400 is 4 ×
4 = 16, and the numerical value indicates the configuration number. A hatched square indicating the logical cell state storage unit 31 indicates an active flag AF = 1 (active state), and an unhatched square indicates an active flag AF = 0. (Inactive state).

In the example described below, the circuit is arranged, if there is a vacant area, in the vacant area with the left bottom justified. If there is no vacant area, the circuit is laid out in the lower left of the entire programmable logic circuit in principle. And

FIG. 11A shows an initial state such as after a system reset. In the logical cell state memory 30, the configuration number CNo of the state data STD of each logical cell state storage unit 31 is CNo = It is 0, and the active flag AF is also AF = 0, so that the circuit can be configured anywhere on the programmable logic circuit 400.

FIG. 11B shows an example of a state after the first configuration is performed. In this example,
This is a case where the circuit a is configured in a logical cell region of 2 × 4 in length × width = corresponding to the region 32 surrounded by a broken line. The data STD of the logic cell state storage unit 31 corresponding to the configured logic cell has a configuration number CNo of CNo = 1 and an active flag A
F is updated to AF = 1.

At this point, the programmable logic circuit 4
Since the empty area above the area No. 00 is a logical cell area of (vertical × horizontal) = 2 × 4, if the circuit to be configured next is smaller than the 2 × 4 area, the configuration number CNo is CNo = 0. If the circuit is configured in a certain logic cell area and the circuit is larger than this area, the area of the circuit a is also a reconstruction area. In other words, the areas where the configuration numbers CNo are CNo = 0 and CNo = 1 are the reconfiguration target areas.

In this state, when the circuit b occupying the logical cell area of (vertical × horizontal = 2 × 2) is to be configured, this second configuration circuit b is shown in FIG. 11 (B). Considering that the configuration is smaller than the logic cell area with the configuration number CNo = 0, the circuit is generally arranged at the lower left in the empty area, and the circuit b is, as shown in FIG.
Is arranged in a dashed area 33 above the area 32.

The configuration number CNo = 2 and the active flag AF = 1 are written as the state data STD of the logical cell state storage section 31 in this area 33. At this point, the programmable logic circuit 400
Above, both the circuit a and the circuit b can operate.

At this point, if the circuit to be configured next is a circuit smaller than the 2 × 2 area, it is configured in the area of the logic cell where the configuration number CNo is CNo = 0. When the circuit is a large circuit, the regions of the circuits a and b are also the reconstruction regions. That is, the configuration number CNo is CNo =
The areas of 0, CNo = 1, and CNo = 2 are the reconstruction target areas.

Also, if the second configuration circuit is a circuit c occupying a logical cell area of (vertical × horizontal = 4 × 2), and the logic of configuration number CNo = 0 shown in FIG. If it is larger than the cell area, the reconstruction area is determined as follows.

That is, the configuration number C
A combination of a logic cell region of No = 0 and a logic cell region of configuration number CNo = 1, and a circuit c
Compare with the size. Then, since the circuit c is smaller than the combined area, the bottom left is basically a rule. Therefore, the circuit c is arranged in the area 34 surrounded by a broken line in FIG. At this point, the circuit a becomes inoperable, and only the circuit c is operable.

Next, after the state shown in FIG. 6C, as a third configuration, the height × width =
Consider a case where a circuit d occupying a 2 × 3 logic cell area is configured. In this case, since the circuit d is larger than the logic cell area of the configuration number CNo = 0 shown in FIG. 11C, the logic cell areas of the configuration numbers CNo = 0 and CNo = 1 are next combined. The size of the circuit d is compared with the size of the circuit d. Then, the circuit d becomes
Since the area is smaller than the combined area, as shown in FIG. 11 (E), the bottom left is the principle, and the circuit a is arranged in the broken line area 35 which is a part of the area where the circuit a was originally arranged. To be.

Then, the configuration number CNo = 3 and the active flag AF = 1 are written as the logic cell state data STD of the logic cells in the area 35. Further, in the logic cell state data STD of the logic cell in which the circuit is not formed in the logic cell having the configuration number CNo = 1, the active flag AF of the logic cell is rewritten to AF = 0. Therefore, the circuits operable at this time on the programmable logic circuit 400 are changed to the circuit b and the circuit c.

Further, as a third configuration after the state shown in FIG. 11C, when a circuit e occupying a logical cell area of (vertical × horizontal = 2 × 2) is formed, the size of the circuit e is large. 11C, the circuit e is arranged in an area 36 indicated by a broken line corresponding to the empty area, as shown in FIG. 11F. You. In the case of this example, on the programmable logic circuit 400, at this time, all of the circuit a, the circuit b, and the circuit c can operate.

Further, after the state shown in FIG.
As the second configuration, vertical x horizontal = 3 x 3
Of a circuit f occupying the logic cell region of FIG. In this case, the size of the circuit f is as shown in FIG.
It is larger than the free area of the configuration number CNo = 0 shown in FIG. 4C, and larger than the combined area of the logic cell area of the configuration number CNo = 0 and the logic cell area of CNo = 1. Therefore, the size of the circuit f is compared with an area obtained by combining the logic cell area of the configuration number CNo = 0, the logic cell area of the CNo = 1, and the logic cell area of the CNo = 2. Then, since the circuit f is smaller than the area obtained by combining these three areas, the circuit f is arranged at the lower left of this area as shown in FIG. At this point, only the circuit c can operate on the programmable logic circuit 400.

As described above, the state data STD of each logic cell state storage unit 31 of the logic cell state memory 30 of the main memory 13 is updated every time the configuration is performed.

Then, as described above, by referring to the active flag AF of the state data STD of each logical cell state storage unit 31 of the logical cell state memory 30,
On the programmable logic circuit 400, a circuit operable at that time can be grasped.

Further, by referring to the configuration number of the status data STD of each logic cell status storage unit 31 of the logic cell status memory 30, it is possible to easily confirm an empty area and to configure a new circuit. In addition, the configuration area of the new circuit can be efficiently determined.

In this embodiment, since the configuration number CNo is 7 bits, 0 to 12
You can only number up to seven. Therefore, in this embodiment, the configuration number CNo is 127
At this point, a configuration number conversion routine in a memory full state as shown in FIG. 12 is executed.

That is, as shown in FIG. 12, first, the state data S stored in the first logical cell state storage section 31 of the logical cell state memory area 30 of the main memory 13 is read.
The TD is checked (step S131), and it is checked whether or not the active flag AF is 0 (step S131).
132).

If the active flag AF = 0, the value of the configuration number CNo of the logic cell state data STD is set to 0 (step S133). Also,
If the active flag AF = 1, classification is performed sequentially from n = 1 according to the value of the configuration number CNo of the logic cell state data STD (step S1).
34). The above processing is performed on all the logic cells (steps S135 and S136).

The processing up to this point will be described with reference to FIG. 13 which is a schematic diagram of the logic cell state memory area 30. That is, in FIG. 13A, the configuration number CNo of the data STD corresponding to the logic cell having the configuration number CNo = 121 where the active flag AF = 0 and the logic cell having the configuration number CNo = 123 is shown in FIG. As shown in FIG. 13 (B), CNo = 0 is converted.

The logic cell of the configuration number CNo = 126 with the active flag AF = 1 is classified into n = N1, and similarly, the configuration number CNo = 1 with the active flag AF = 1.
The 27 logic cells are associated with n = N2 as a classification.

Next, the classified sets {N1, N2,.
With respect to Nn 小 さ い, according to the value of the configuration number CNo at the time of classification,
Sorting is performed (step S137). In the example of FIG. 13, for the set {N1, N2}, N1 is CNo = 12.
6, since N2 is CNo = 127, it remains {N1, N2}.

Next, with respect to the set of sorted results, the smallest number is CNo = 1, the next is CNo = 2, and so on.
The value of No is rewritten (step S138). In the example of FIG. 13, the configuration number CNo of the state data STD of the logic cell corresponding to N1 is CNo = 1, N2
Is rewritten as CNo = 2 in the configuration number CNo of the state data STD of the logic cell corresponding to.

Finally, the maximum value of the rewritten configuration number is set as the maximum value of the configuration number CNomax (step S13).
9), this configuration number conversion routine ends.

The configuration number CNo
Becomes 127, and when the hardware processing is completed, resetting the configuration memory of the programmable logic circuit 400 simplifies the application program.

The configuration number CNo
Becomes a certain number, the programmable logic circuit 4
By resetting the 00 configuration memory, it is possible to eliminate the influence on the operation circuit due to the circuit fragments left by the configuration many times.

Further, depending on the application, the amount of memory for one logic cell in the logic cell state memory space for storing the state of the logic cell on the programmable logic circuit can be increased or decreased. For example, in an application in which the number of times of configuration on the programmable logic circuit is small, the number of bits assigned to the state data STD may be small, and in an application in which the number of times of configuration is large, the number of bits of state data may be increased.

For example, in an application in which the number of times of configuration on a programmable logic circuit is small, the state data STD for one logic cell includes
For example, when 4 bits are allocated, only the configuration number from 0 to 7 can be used, but there is an advantage that a programmable logic circuit of 128 cells × 128 cells requires a small memory consumption of about 8 kbytes.

[0103]

As described above, according to the present invention, in an information processing system using a programmable logic circuit device capable of partially reconfiguring a circuit configuration during operation, a plurality of circuits are spatially divided. In the case where the logic cell state memory is used, information that reflects the state of each logic cell on the programmable logic circuit is stored in the logic cell state memory so that resources on the programmable logic circuit can be efficiently used. Configuration that can be used for

[0104] Circuits that have been configured and executed, and that are still left on the programmable logic circuit, can be used without configuration if necessary, eliminating the time required for configuration. , Leading to a reduction in processing time.

Also, by counting the number of times of configuration in the programmable logic circuit and resetting the configuration memory at a certain number of times, the operation of the operation circuit due to fragments of the circuit that are left by many times of configuration is performed. It is possible to eliminate the effect.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a logic cell state memory according to an embodiment of an information processing system according to the present invention;

FIG. 2 is a functional block diagram for describing an outline of a configuration of an information processing system according to an embodiment of the present invention;

FIG. 3 is a diagram used to explain an outline of an embodiment of an information processing system according to the present invention;

FIG. 4 is a diagram showing an example of circuit information configured in a programmable logic circuit in the embodiment of the information processing system according to the present invention;

FIG. 5 is a block diagram illustrating a hardware configuration example of an embodiment of an information processing system according to the present invention.

FIG. 6 is a diagram showing an example of a programmable logic circuit used in an embodiment of the information processing system according to the present invention.

FIG. 7 is a diagram for explaining a correspondence between states of logic cells on a programmable logic circuit and contents of a logic cell state memory in the embodiment of the information processing system according to the present invention;

FIG. 8 is a flowchart for explaining an outline of processing in an embodiment of the information processing system according to the present invention.

FIG. 9 is a diagram showing a part of a flowchart for explaining a main part of a process in the embodiment of the information processing system according to the present invention;

FIG. 10 is a diagram showing a continuation of the flowchart for explaining the main part of the processing in the embodiment of the information processing system according to the present invention;

FIG. 11 is a diagram for explaining data updating of a logic cell state memory when configuration is performed a plurality of times in the embodiment of the information processing system according to the present invention;

FIG. 12 is a flowchart for explaining a configuration number conversion process of a logical cell state memory in the embodiment of the information processing system according to the present invention;

FIG. 13 is a diagram for explaining a configuration number conversion process of the logic cell state memory of FIG. 12;

FIG. 14 is a diagram illustrating a conventional method for configuring a programmable logic circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Information processing system 11 CPU 13 Main memory 18 Hard disk drive 20 Network 30 Logic cell state memory 31 Logic cell state storage part 400 Programmable logic circuit 401 Logic cell 402 Wiring area STD Logic cell state data CNo Configuration number AF Active flag

Claims (6)

[Claims] 1. An information processing system for executing a series of processes in which a process is described by a program, wherein at least a part of the series of processes can be processed by a programmable logic circuit. A plurality of logic cells, and of the plurality of logic cells, circuit information is configured in a logic cell in a designated area, thereby mounting a new logic circuit in the designated area And a logic cell state memory for storing information reflecting a state of each of the plurality of logic cells of the programmable logic circuit, wherein each time new circuit information is configured, the logic cell state memory is provided. Reflects the state of the configured logic cell in the stored information of The information processing system characterized by updating that information. 2. The information processing system according to claim 1, wherein the information reflecting the state of the logic cell in the logic cell state memory includes information indicating the number of configurations of the circuit state of the logic cell. An information processing system including a configuration count. 3. The information processing system according to claim 1, wherein the information that reflects the state of the logic cell in the logic cell state memory is such that a circuit including the logic cell is provided on the programmable logic circuit. An information processing system characterized by including information indicating whether or not it is operable on a computer. 4. The information processing system according to claim 1, wherein the configuration of the next new functional circuit is changed by referring to information reflecting the state of each logic cell in the logic cell state memory. An information processing system, wherein a possible area on the programmable logic circuit is determined. 5. The information processing system according to claim 1, wherein said programmable logic logic is referred to by referring to information reflecting a state of each logic cell in said logic cell state memory. An information processing system, wherein a circuit operable on a circuit is detected and used. 6. The information processing system according to claim 1, wherein when the information reflecting the state of the logic cell in the logic cell state memory becomes equal to a preset one, the programmable logic circuit is controlled by the logic cell state memory. An information processing system for resetting a configuration memory of a circuit.