JP2000050496A - Charge control device for electric double-layer capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a charge control device for an electric double-layer capacitor that has less heat generation in a switching element for controlling current, and superior practicality. SOLUTION: A device is provide with a switching element Trp fro charging that is connected in series with a capacitor block CB where a plurality of electric double-layer capacitors Ci are connected in series, a charging part that drives and controls the element Trp and controls a charging current to the capacitor block CB from a power supply for charging, a switching element Tri limiting charging that is connected to each capacitor Ci in parallel, and a charging limitation part that drives and controls the switching element for limiting charging to prevent overcharging in each capacitor an bypasses the discharging and charging current of the electric double-layer capacitor. The charging part has a means for judging full charging and a means for generating a drive signal for charging, and the charging limitat part has a means for specifying a target to be controlled, a means for judging inner short-circuiting, a means for judging charging limitat, and a means for generating a drive signal for charging limitat.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a large-capacity capacitor bank (electric double-layer capacitor for power) containing a capacitor block formed by connecting a plurality of electric double-layer capacitors in series in a rectangular outer case, The present invention relates to a charge control device for an electric double layer capacitor which is provided in a rectangular outer case of the capacitor bank and is used for charging the capacitor block.

[0002]

2. Description of the Related Art An electric double layer capacitor utilizes electric energy by electric charges accumulated in an electric double layer formed at an interface between a polarizable electrode and an electrolytic solution. It is noted that this electric double layer capacitor is capable of rapid charge / discharge and stable against repeated charge / discharge.
The development of large-capacity capacitors of several thousand F is in progress.

The withstand voltage of an electric double layer capacitor is governed by the decomposition voltage of an electrolytic solution and is as low as about 0.8 to 3 V. For this reason, the rectangular exterior is used for high-voltage and large-capacity applications such as motor drive power supplies, power supplies that respond to instantaneous voltage drops in various information devices such as computers, power supplies for signs on remote islands and mountains, and power supplies for outdoor lights. A large-capacity capacitor bank (electric double layer capacitor for power) containing a capacitor block in which a plurality of electric double layer capacitors (unit cells) are connected in series in a case is used. As an example, ten laminated electric double-layer capacitors (unit cells) having a rated voltage of 3 V and a capacitance of 1600 F are connected in series and housed in a rectangular outer case.
Capacitance 160F, width 100 x height 120 x length 25
There is a capacitor bank having a size of about 0 mm.

When charging a capacitor block in which a plurality of such electric double layer capacitors are connected in series,
Due to variations in the basic performance (capacitance, internal resistance, etc.) of individual electric double-layer capacitors and slight differences in the degree of performance degradation, some electric double-layer capacitors are not fully charged, Will be overcharged. When the capacitor voltage becomes excessive with respect to the withstand voltage due to overcharging, performance degradation such as a decrease in capacitance and an increase in leakage current is caused.

Therefore, conventionally, a charge limiting circuit has been proposed which controls the charge state of each of the electric double layer capacitors C connected in series and limits the charge so that each capacitor C does not exceed the withstand voltage. As shown in FIGS. 8 and 9, a charge limiting circuit A indicated by reference symbol A is connected in parallel to a plurality of electric double layer capacitors C constituting a capacitor block, and the terminal voltage of the capacitor C is reduced. When the voltage reaches a preset voltage Vr (<withstand voltage) of a predetermined value, the comparator CO turns on the switching element (eg, transistor) S. When the switching element S is turned on,
The charging current flowing to the capacitor C is bypassed via the switching element S and flows to the capacitor connected to the subsequent stage or the charge limiting circuit A thereof, and at the same time, the capacitor C is discharged via the switching element S. Then, the terminal voltage decreases. In this way, when each capacitor reaches the set voltage Vr, all electric double layer capacitors C are fully charged while discharging the charge current to another capacitor simultaneously with discharging.

[0006]

However, in the above-described conventional charge limiting circuit A, when the terminal voltage of the electric double layer capacitor C reaches a set voltage Vr set in advance as a final target value, the capacitor C is not charged. Since the bypass of the charging current flowing in is started, the energization of the switching element S is concentrated and frequently repeated at the end of charging the capacitor block, so that the heat generated by the semiconductor switching element S such as a transistor considerably increases. It was big.

For this reason, each switching element S
It is necessary to attach a printed circuit board on which the charge limiting circuit A is mounted in the outer case of the capacitor bank. In order to ensure heat dissipation of the switching element S, a charge limiting circuit including a switching element with a heat sink is required. A whole could not be molded with an insulating material such as epoxy resin. For this reason, a capacitor bank equipped with a conventional charge limiting circuit A in an outer case is inferior in terms of water resistance and reliability. For example, when used as a power source for an outside light, the capacitor bank may be installed underground or on a wall of a building. It could not be embedded and installed, and there was a problem in terms of practicality.

Accordingly, an object of the present invention is to provide a capacitor bank containing a capacitor block in which a plurality of electric double-layer capacitors are connected in series in an outer case, and the capacitor mounted in the outer case of the capacitor bank. In the charge control device for electric double layer capacitors used for charging the blocks, the heat generated by the switching element for current control is small, eliminating the need to provide a heat sink or the like.
An object of the present invention is to provide a charge control device for an electric double layer capacitor that can realize a capacitor bank having excellent practicality.

[0009]

In order to achieve the above object, a charge control device for an electric double layer capacitor according to the present invention is connected in series to a capacitor block formed by connecting a plurality of electric double layer capacitors in series. A charging switching element, a charging unit that drives and controls the charging switching element to control a charging current from a charging power supply to the capacitor block, and is connected in parallel to each of the electric double-layer capacitors. A charge limiting switching element, and a charge limiter that drives and controls the charge limiting switching element so as not to overcharge each of the electric double layer capacitors, thereby discharging the electric double layer capacitor and bypassing a charging current. And a charging control device for an electric double layer capacitor comprising:
Full charge determination means for determining whether the capacitor block terminal voltage detection value has reached a predetermined full charge set voltage at predetermined time intervals, excluding a plurality of electric double layer capacitors excluding those having an internal short circuit. A charging drive signal generating means for outputting a drive signal to the charging switching element when the capacitor block terminal voltage detection value does not reach the full charge set voltage as a result of the determination by the full charge determination means; Wherein the charge limiting unit comprises: a control target designating unit for sequentially designating the plurality of electric double layer capacitors one by one in a predetermined order when the driving signal is output to the charging switching element. For the electric double layer capacitor designated by the control target designation means, based on the terminal voltage detection value and the capacitor block terminal voltage detection value. An internal short-circuit determining means for determining whether or not the electric double-layer capacitor has an internal short-circuit by comparing with the calculated internal short-circuit determination level; When there is no short circuit, based on the capacitor block terminal voltage detection value, a charge limit determination level exceeding a predetermined amount of the average terminal voltage of each electric double layer capacitor during charging is calculated, and the terminal voltage detection value of the electric double layer capacitor is calculated. Charge limit determining means for determining whether or not is greater than the charge limit determination level, and as a result of the determination by the charge limit determination means, when the detected terminal voltage of the electric double layer capacitor is greater than the charge limit determination level, A drive signal is supplied to the charge limiting switching element of the electric double layer capacitor so that the terminal voltage falls below the charge limit determination level. And it is characterized in that it has a charge limiting drive signal generating means for outputting. Further, the charging unit and the charging limiting unit are realized by a microcomputer.

In the charging control device according to the present invention, when charging a capacitor block formed by connecting a plurality of electric double layer capacitors in series, the internal short circuit judging means at each predetermined time interval at the time of charging makes the internal of each electric double layer capacitor. Determines the presence or absence of a short circuit, and if it detects the presence of an electric double layer capacitor in which an internal short circuit has occurred partially due to deterioration, etc.
By determining whether or not V0 has reached the set full charge set voltage Vf by subtracting the set voltage of the electric double layer capacitor with an internal short circuit, the continuation / end of charging to the capacitor block is determined. ing.

[0011] With this configuration, when there is an internal short circuit in any of the electric double layer capacitors, the charging of the capacitor block can be terminated when all the electric double layer capacitors without the internal short circuit reach their set voltage. As a result, unlike the related art, all the capacitors having no internal short circuit reach the set voltage and charge to the capacitor block despite the discharge and the bypass of the charge current by the respective charge limiting switching elements Tri. Is not continued without terminating, and therefore, it is possible to prevent a large amount of heat from being generated in the charge limiting switching element Tri.

In the charge control device according to the present invention, the control for limiting the charging current is performed by the charge limit determining means for each electric double layer capacitor determined to have no internal short circuit by the internal short circuit determining means. At every predetermined time interval, based on the detected capacitor bank terminal voltage value V0 at that time, a charge limit determination level VL of a value exceeding a predetermined amount of the average terminal voltage Vave of each electric double layer capacitor rising with the progress of charging is calculated, It is determined whether or not the detected terminal voltage value Vi of the electric double layer capacitor to be controlled is greater than the determination level VL. As a result of the determination, when the terminal voltage detection value Vi of the electric double layer capacitor is equal to or higher than the charge limit determination level VL, the charge restricting drive signal generating means causes the switching element Tri connected to the electric double layer capacitor to be connected in parallel. A drive signal is output, the electric double layer capacitor is discharged, the capacitor terminal voltage Vi falls below the determination level VL, and the capacitor average terminal voltage Va
The value is close to ve.

As described above, small discharge is performed intermittently by the charge limiting switching element Tri from the stage where the capacitor terminal voltage Vi is low, and the terminal voltages of these electric double layer capacitors are reduced in the charging process until the set voltage is reached. Since it is made uniform so as to be almost the same, unlike the conventional case, the discharge of the large current by the switching element Tri is not frequently repeated at short time intervals at the end of charging. Large heat generation in the switching element Tri can be prevented.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing an example of an electric circuit configuration of a capacitor bank including a charge control device for an electric double layer capacitor according to the present invention.

As shown in FIG. 1, the capacitor bank comprises:
A plurality, in this example, five electric double layer capacitors C1 to C5
Are connected in series, and a charge control device for an electric double layer capacitor used for charging the block CB. The positive terminal 1 'of the capacitor block CB is connected to the positive external terminal 1 of the capacitor bank via a diode Da whose anode is connected to the terminal 1'.
The negative terminal 2 'of CB is connected to the negative external terminal 2 of the capacitor bank. A positive terminal of a charging power supply (not shown) is connected to the external terminal 1, and a negative terminal of the power supply is connected to the external terminal 2. The voltage and capacity of each of the electric double layer capacitors C1 to C5 constituting the capacitor block CB are a rated voltage of 3 V and a capacitance of 1600F in this example.

The charge control device for an electric double layer capacitor is as follows:
Each of a charging switching element Trp and a diode Db forming a charging current path from the positive external terminal 1 to the positive terminal 1 'of the capacitor block CB, and electric double layer capacitors C1 to C5 constituting the capacitor block CB. The switching elements Tr1 to Tr5 and the diodes D1 to D5 connected between the terminals, respectively, and the diode Da inserted and connected between the positive terminal 1 'of the capacitor block CB and the positive external terminal 1 of the capacitor bank CB. And a programmed one-chip microcomputer (hereinafter simply referred to as a microcomputer) 3. The diodes D1 to D5 are for protecting the capacitor against reverse charging. The switching elements Trp, Tr1 to
Tr5 uses a transistor, in this example, an EFT (field effect transistor). However, in FIG. 1, not a symbol of the EFT but a symbol of an ordinary bipolar transistor is used.

The microcomputer 3 includes a CPU, ROM, RA
A charging unit that includes an M / I / O interface, an A / D converter, a pulse generator, and the like, controls a charging switching element Trp to control a charging current from a charging power supply to the capacitor block CB, and a capacitor block CB And a charge limiter that drives and controls the charge-limiting switching element Tri so as to prevent overcharging of each of the electric double-layer capacitors C1 to C5, thereby discharging the electric double-layer capacitor Ci and bypassing the charge current. Make up.

In this microcomputer 3, a capacitor block
The terminal voltage V0 of CB is the plus terminal 1 '(microcomputer 3
Of the input terminal A / Din (5) of the microcomputer 3) and the voltage of the negative terminal 2 '(connected to the terminal GND of the microcomputer 3), and detect as a voltage difference. I have. Also, an i-th electric double layer capacitor
The terminal voltage Vi of Ci is obtained by reading the voltage of the positive terminal and the voltage of the negative terminal of the capacitor Ci and detecting the difference between the voltages.

Next, an example of control by the microcomputer 3 will be described with reference to flowcharts shown in FIGS.

In this case, the control data previously input to the RAM of the microcomputer 3 is N: the number of electric double layer capacitors Ci connected in series, Ivt: control cycle time (ms), and sf: Internal short-circuit deemed coefficient (%), k, kk: Coefficient for calculating allowable value of capacitor Ci terminal voltage variation, T
o: Time ratio (%) of control cycle time Ivt, TP: Pulse cycle (μs) of drive pulse train PP of charging switching element Trp, TPB: Charge limiting switching element Tri
Pulse period (μs) of the driving pulse train PB, PBcount:
Number of pulses in drive pulse train PB, dVc: drive pulse train PP
Is a constant (mV) for calculating the pulse duty ratio.

First, in step 101, as an initial setting, the number of capacitors scn regarded as having an internal short circuit is set to zero, and the number of pulses PPcount of the driving pulse train PP for driving the charging switching element Trp is set.
With the previously input control data Ivt
, To and TP are calculated by the following equation (1). In the equation (1), for example, the control cycle time Ivt: 1
00 ms, time ratio To: 40 in control cycle time Ivt
%, The pulse period TP of the driving pulse train PP of the charging switching element Trp: 1000 μs, the number of pulses PPco
unt is 40.

[0022]

(Equation 1)

After the initial setting, the timer is started (step 102), and it is checked whether or not the control cycle time Ivt has elapsed as the time measured after the timer is started (step 103). If the control cycle time Ivt has elapsed (YE in step 103)
S), the timer is reset and restarted in step 104, and the process proceeds to step 105. In step 105, the terminal voltage V0 of the capacitor block CB is detected. Also, the full charge set voltage Vf of the capacitor block CB is Vf = 3000
X (N-scn). In the case of this example, the set voltage of each electric double layer capacitor Ci is 3000 mV, the number N of capacitors connected in series N = 5, and at this time, the scn = 0.
And the full charge set voltage Vf is 15000 mV (15 V)
It is. When the full-charge set voltage Vf is determined by an internal short-circuit determining means described later to indicate that an electric double-layer capacitor having an internal short-circuit exists, an internal short-circuit is generated from the electric double-layer capacitors C1 to C5 constituting the capacitor block CB. Is excluded.

Next, in step 106, it is determined whether or not the capacitor block terminal voltage detection value V0 is equal to or higher than the full charge set voltage Vf. If the voltage is equal to or higher than the full charge set voltage Vf (YES in step 106), the output of the drive signal to the charging switching element Trp is stopped in step 107, the charging is terminated, and a transition is made to a standby mode for the next charging. If smaller than the full charge set voltage Vf (N in step 106)
In O), the process proceeds to step 108. As described above, the means for executing the procedure of steps 105 and 106 constitutes a full charge determination means.

In step 108, the output voltage P of the charging power source is read through the input terminal A / Din (P).
Then, in step 109, the charging state of the charging power supply is checked, and in step 110, the output characteristics of the charging power supply are checked. That is, in Step 109, Step 108
It is determined whether or not the charging power supply output voltage P detected at step 105 is equal to or higher than the capacitor block terminal voltage detection value V0 detected at step 105. The charging power supply output voltage P is the terminal voltage detection value V0
If it is smaller (YES in step 109), for example, in the case of a charging power supply composed of a solar cell, it is considered that the voltage is low and the charging system is not ready, so the process shifts to the standby mode.

If the output voltage P of the charging power supply is higher than the terminal voltage detection value V0 of the capacitor block CB to be charged (NO in step 109), the characteristics of the charging power supply are confirmed in step 110. If the characteristic of the charging power supply is a constant current characteristic (NO in step 110), even if a large charging current is supplied to the capacitor block CB, the charging power supply is not likely to be in an overload state. Output terminal
A driving signal for turning on the element Trp continuously is output to the charging switching element Trp via Dout (P) to the charging switching element Trp (step 111). On the other hand, in the case of a charging power supply having a constant voltage characteristic instead of a constant current (YES in step 110), in order to prevent the charging power supply from being overloaded, the capacitor block terminal voltage detection value V0 is determined in step 112. [(Power output voltage for charging P) x 0.9
5] is determined. If it is large (YES in step 112), that is, in the last stage of charging, there is no possibility of overload, so step 111
And outputs a continuous drive signal. On the other hand, if it is not the end of charging (NO in step 112), the process proceeds to step 113 to generate a driving pulse train signal PP to be output to the charging switching element Trp.

FIG. 2 is an explanatory diagram of the driving pulse train signal PP applied to the charging switching element Trp. Step 11
3, in the pulse train signal PP, TP: pulse period,
Assuming that τ is a pulse width, a pulse duty ratio PPduty (%) represented by τ / TP is calculated and determined according to equation (2).

[0028]

(Equation 2)

That is, the driving pulse train signal PP applied to the switching element Trp has a pulse duty ratio PPduty, a pulse number PPcount, and a pulse period TP. In the case of a charging power supply having a constant voltage characteristic, the pulse period TP and the pulse number PP
By keeping the count constant and changing the pulse duty ratio PPduty so that the voltage rise dVc per unit time of the capacitor block CB due to charging becomes almost constant,
The charging power supply is prevented from being overloaded. As can be seen from equation (2), the pulse duty ratio PPduty
Is inversely proportional to the difference voltage (P-V0) between the power supply output voltage P for charging and the capacitor bank terminal voltage V0 during charging. In order to suppress the charging current when the difference voltage (P-V0) is large at the beginning of charging. It is set to be small, and is set to increase as charging progresses. The pulse duty ratio PPduty is a control cycle time Ivt (for example, 100 ms) which is pre-input control data, a voltage rise dVc (for example, 500 mV) of the capacitor block CB per the time Ivt, and a pulse train signal occupying the time Ivt. It is calculated from the PP time ratio To (for example, 40%) and the detected value (P−V0) according to the equation (2).

Next, the routine proceeds to step 114, where the output terminal Dout
Through (P), the charging switching element Trp is supplied to the driving device having the pulse duty ratio PPduty calculated in step 113, the pulse number PPcount calculated in step 101, and the pulse period TP (for example, 1000 μs) input in advance. The pulse train signal PP is output to charge the capacitor block CB. As described above, the charging drive signal generating means is constituted by the means for executing the procedure of steps 108 to 114.

Next, as an initial process for detecting the presence / absence of an internal short circuit in each of the electric double layer capacitors C1 to C5 and performing the charge limiting process, the number of capacitors scn determined to have an internal short circuit in step 115 is set to zero. Then, after setting the capacitor number i to 1 in step 116, the process proceeds to step 117.

In step 117, the terminal voltage V1 of the i-th electric double layer capacitor Ci, here the first electric double layer capacitor C1 specified in step 116, is detected, and the terminal voltage V0 of the capacitor block CB is detected. To detect. Also, the capacitor block terminal voltage detection value
Based on V0, the internal short-circuit judgment level VS is calculated as VS = (V0 / N)
X (Sf / 100). Here, in this case,
N = 5, and the internal short-circuit deemed coefficient sf, which is the control data input in advance, is, for example, 70%, which is an appropriate value obtained through experience.

The detected terminal voltage V1 of the electric double layer capacitor C1 is equal to the calculated internal short circuit determination level VS.
It is determined whether or not the capacitor C1 is larger than the capacitor C1 (Step 118).
Since there is no internal short circuit, it is considered normal, and the process proceeds to step 120 in order to perform a charge limiting process described later.
On the other hand, if the capacitor terminal voltage detection value V1 is equal to or lower than the internal short circuit determination level VS (NO in step 118), it is considered that the electric double layer capacitor C1 has an internal short circuit. The process proceeds to step 119 without performing the process. After the number of capacitors scn regarded as having an internal short circuit is incremented by 1, the process proceeds to step 127 to designate the next second electric double layer capacitor C2. . Thus, step 1
The means for executing the procedures of steps 17 and 118 constitutes an internal short circuit judging means.

At step 120, step 117 is executed.
Based on the capacitor block terminal voltage V0 detected in
The average terminal voltage Vave of the electric double layer capacitors excluding those connected in series and having an internal short circuit, Vave =
It is calculated as V0 / (N-scn). Next, step 121
Then, the variation allowable voltage Vda (mV) is calculated by equation (3). In the equation (3), the coefficients k 1 and kk are control data input in advance. For example, the coefficient k is set to 120 and the coefficient kk is set to 400.

[0035]

(Equation 3)

As shown in FIG. 4, the variation allowable voltage Vda has a relationship inversely proportional to the terminal voltage value V0 of the charged capacitor block CB, and when the capacitor block terminal voltage V0 is low ( When the capacitor average terminal voltage Vave is low), the voltage is large to positively charge the capacitor, and the capacitor block terminal voltage V0 is equal to the full charge setting voltage.
In this example, when Vf reaches Vf (when the capacitor average terminal voltage Vave reaches the set voltage of 3000 mV), it is set to zero. And the average terminal voltage
Based on Vave and the variation allowable voltage Vda, a charge limit determination level VL is calculated as VL = Vave + Vda. As shown in FIG. 4, the charge limit determination level VL is a value that exceeds the capacitor average terminal voltage Vave by a predetermined amount. The difference voltage is set so that the difference voltage from the average terminal voltage Vave becomes zero when the difference voltage gradually decreases and the capacitor block terminal voltage V0 reaches the full charge set voltage Vf. The charge limit determination level VL is set such that the terminal voltages Vi of the electric double layer capacitors Ci are almost the same in the charging process until the set voltage is reached for the electric double layer capacitors except those connected in series and having an internal short circuit. It is provided in order to make it.

Next, at step 122, it is determined whether or not the detected terminal voltage Vi of the i-th electric double layer capacitor Ci is equal to or higher than the charge limit determination level VL. Here, it is determined whether the terminal voltage detection value V1 of the first capacitor C1 is equal to or higher than the charge limit determination level VL. If it is equal to or higher than the charge limit determination level VL (NO in step 122), the process proceeds to step 123 to perform the charge limit process. On the other hand, when the terminal voltage detection value V1 is smaller than the charge limit determination level VL (step 122).
YES), the next second operation is performed without performing the charging restriction process.
The process proceeds to step 127 to designate the second electric double layer capacitor C2. As described above, the means for executing the procedure from step 120 to step 122 constitutes the charge restriction determining means.

FIG. 3 is an explanatory diagram of the driving pulse train signal PB applied to the charging limiting switching element Tri. In step 123, assuming that TPB is a pulse period and τ is a pulse width in the pulse train signal PB, a pulse duty ratio PBduty (%) represented by τ / TPB is calculated and determined according to equation (4).

[0039]

(Equation 4)

That is, the driving pulse train signal PB applied to the charging limiting switching element Tri connected in parallel to the i-th capacitor Ci has a pulse duty ratio PBduty, a pulse number PBcount, and a pulse period TPB.
TPB and the number of pulses PBcount are fixed, and the pulse duty ratio PBduty decreases as the terminal voltage Vi increases with respect to the terminal voltage Vi of the capacitor Ci.
When the switch is turned on, an excessive discharge current is prevented from flowing. In this example, Vi is the set voltage of 3000 mV
, PBduty = 20%. Here, the first electric double-layer capacitor C1 specified in step 116
The pulse duty ratio PBduty of the driving pulse train signal PB to be given to the charging limiting switching element Tr1 is calculated according to the equation (4).

Then, the process proceeds to a step 124, wherein the charging limiting switching element Tr1 is output through the output terminal Dout (1).
The pulse duty ratio PBduty calculated in step 123 and the pulse number PBcount previously input (for example, 1
0), and a previously input pulse period TPB (for example, 50
0 Ps) is output. After outputting the pulse train signal PB, step 1 is performed to check the result of discharging the capacitor C1 by the switching element Tr1.
At step 25, the terminal voltage V1 of the first capacitor C1 is detected. Next, at step 126, it is determined whether or not the terminal voltage detection value V1 of the capacitor C1 is equal to or higher than the charge limit determination level VL. When the charge limit determination level is VL or higher (step 1
(NO at 26) In step 123, the electric double layer capacitor C1 is discharged again so that its terminal voltage Vi falls below the charge limit determination level VL and becomes close to the capacitor average terminal voltage Vave. Return. When terminal voltage detection value V1 is smaller than charge limit determination level VL as a result of discharging by switching element Tr1 (YES in step 126)
Goes to step 127 to designate the next second electric double layer capacitor C2. As described above, the means for executing the procedure from step 123 to step 126 constitutes a charge limiting drive signal generating means.

Then, in step 127, the capacitor number i is incremented by one, and the next second
Designate the 2nd electric double layer capacitor C2. Next, at step 128, after confirming that the incremented capacitor number is equal to or less than the last number (i ≦ 5 in this example) (YES at step 128), the next electric double layer capacitor C2 is checked whether there is an internal short circuit. The process returns to step 117 to perform the detection and the charging restriction process when the internal short circuit is not detected. Thus, step 11
6, means for executing the procedures of steps 127 and 128 constitute a control target specifying means.

In this way, for all the electric double layer capacitors C1 to C5 from i = 1 to i = 5 constituting the capacitor block CB, detection of the presence or absence of an internal short circuit, and
A charge restriction process is performed when no internal short circuit is detected, and thereafter, the process returns to step 103. Then, in step 103, it is determined whether or not the control cycle time Ivt has elapsed since the timer was restarted in the previous step 104.
The series of processes described above is performed in the next control cycle starting from.

As a result, in the charging control device according to the present invention, when charging the capacitor block CB formed by connecting a plurality of electric double layer capacitors C1 to C5 in series, one of these electric double layer capacitors C1 to C5 is charged. , The charging of the capacitor block CB can be terminated when all the other electric double layer capacitors having no internal short circuit reach the set voltage. Therefore, unlike the conventional case, all the capacitors having no internal short circuit reach the set voltage, and their respective charge-limiting switching elements Tri
The charging of the capacitor block CB is not continued without ending even though the discharging and the charging current are bypassed by the above, so that there is no large heat generation in the charging limiting switching element Tri. can do. In addition, for each electric double-layer capacitor except those having internal short-circuits, small discharge is performed intermittently by the charge-limiting switching element Tri from the stage where the capacitor terminal voltage Vi is low, and during the charging process until the set voltage is reached. Since the terminal voltages Vi of these electric double layer capacitors are made uniform so as to be substantially the same, unlike the conventional case, the discharge of a large current by the charge limiting switching element Tri is performed at short intervals at the end of charging. The switching element Tri for limiting charging does not repeat frequently.
Large heat generation can be prevented.

[0045]

As described above, the electric double layer capacitor charging control device according to the present invention is provided in a capacitor bank containing a capacitor block in which a plurality of electric double layer capacitors are connected in series in an outer case. In the electric double layer capacitor charge control device provided in the outer case of the capacitor bank and used for charging the capacitor block, heat generated by the current control switching element is small, and a heat radiating plate or the like is not required. The entire control device can be molded with epoxy resin or the like. Therefore, the capacitor bank equipped with the charge control device of the present invention has excellent water resistance and reliability,
For example, when used as an external light power source or the like, it can be installed underground or embedded in a wall of a building. That is, according to the charge control device for an electric double layer capacitor of the present invention, it is possible to realize a capacitor bank which is much more practical than conventional ones.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of an electric circuit configuration of a capacitor bank including a charge control device for an electric double layer capacitor according to the present invention.

FIG. 2 is an explanatory diagram of a driving pulse train signal PP given to a charging switching element Trp shown in FIG.

FIG. 3 is an explanatory diagram of a driving pulse train signal PB given to a charging limiting switching element Tri shown in FIG. 1;

FIG. 4 is a graph showing a capacitor average terminal voltage Vave, a variation allowable voltage Vda, and a charge limit determination level VL, with the horizontal axis representing the capacitor block terminal voltage V0 and the vertical axis representing the voltage value.

FIG. 5 is a flowchart illustrating an example of a control procedure by a microcomputer.

FIG. 6 is a flowchart illustrating an example of a control procedure by a microcomputer.

FIG. 7 is a flowchart illustrating an example of a control procedure by the microcomputer.

FIG. 8 is a diagram illustrating an example of an electric circuit configuration of a capacitor bank including a conventional charge limiting circuit.

FIG. 9 is a diagram showing a charge limiting circuit of FIG. 8;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... The positive external terminal of a capacitor bank 2 ... The negative external terminal of a capacitor bank 1 '... The positive terminal of a capacitor block 2' ... The negative terminal of a capacitor block 3 ... One-chip microcomputer
CB: Capacitor block C1-C5: Electric double layer capacitor Trp: Charging switching element Tr1-Tr5: Charging limiting switching element Da, Db, D1
~ D5… Diode

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5G065 AA00 DA04 EA01 HA17 JA07 LA01 MA07 MA09 MA10 NA01 5H730 AA00 AS17 BB11 BB57 DD04 FD01 FF09 FG05

Claims (2)

[Claims] 1. A charging switching element connected in series to a capacitor block formed by connecting a plurality of electric double layer capacitors in series, and a driving control of the charging switching element to control a charging power supply from a charging power supply to the capacitor block. A charging unit that controls a charging current; a charging limiting switching element that is connected in parallel to each of the electric double layer capacitors; and a charge limiting unit that prevents the electric double layer capacitors from being overcharged. A charge control unit for an electric double layer capacitor, comprising: a charge limiting unit that drives and controls a switching element for performing bypass of discharging and charging current of the electric double layer capacitor. Capacitor block terminal voltage detection value is determined when there is an internal short circuit from the plurality of electric double layer capacitors. Full charge determination means for determining whether or not the full charge set voltage that has been removed has been reached; and, as a result of the determination by the full charge determination means, when the capacitor block terminal voltage detection value has not reached the full charge set voltage. And a charging drive signal generating means for outputting a drive signal to the charging switching element, wherein the charge limiting unit is configured to output the driving signal to the charging switching element when the driving signal is output to the charging switching element. A control target specifying means for sequentially specifying one by one in a predetermined order for the electric double layer capacitor, and a terminal voltage detection value and a capacitor block terminal voltage detection value for the electric double layer capacitor specified by the control target specifying means. An internal short-circuit judgment is performed by comparing with the internal short-circuit judgment level calculated based on Disconnection means, as a result of the determination by the internal short-circuit determination means, when there is no internal short-circuit in the electric double-layer capacitor, based on the capacitor block terminal voltage detection value, the average terminal voltage of each electric double-layer capacitor during charging is A charge limit determination level for calculating a charge limit determination level exceeding a predetermined amount, and determining whether a terminal voltage detection value of the electric double layer capacitor is greater than the charge limit determination level; and a result of the determination by the charge limit determination means. When the detected terminal voltage of the electric double layer capacitor is higher than the charge limit determination level, the drive signal is supplied to the charge limit switching element of the electric double layer capacitor so that the terminal voltage falls below the charge limit determination level. A charge control device for an electric double layer capacitor, comprising: a drive signal generating means for outputting a charge limiting signal. 2. The charging control device for an electric double layer capacitor according to claim 1, wherein said charging unit and said charging limiting unit are realized by a microcomputer.