GB2575810A - Power semiconductor device - Google Patents

Power semiconductor device Download PDF

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Publication number
GB2575810A
GB2575810A GB1811990.9A GB201811990A GB2575810A GB 2575810 A GB2575810 A GB 2575810A GB 201811990 A GB201811990 A GB 201811990A GB 2575810 A GB2575810 A GB 2575810A
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United Kingdom
Prior art keywords
region
semiconductor device
power semiconductor
conduction path
switch
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GB1811990.9A
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GB201811990D0 (en
Inventor
Huang Eddie
Koper Nicolaus
Rozman Matijaz
D Wood Stephen
Zhang Jianfeng
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Ween Semiconductors Tech Co Ltd
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Ween Semiconductors Tech Co Ltd
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Priority to GB1811990.9A priority Critical patent/GB2575810A/en
Publication of GB201811990D0 publication Critical patent/GB201811990D0/en
Priority to CN201910666410.2A priority patent/CN110767651A/en
Publication of GB2575810A publication Critical patent/GB2575810A/en
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Electronic Switches (AREA)
  • Thyristors (AREA)

Abstract

Power semiconductor device 100 and method of operation. Device 100 comprises a semiconductor substrate. Device 100 comprises unipolar conducting structure which comprises first, second and third regions 1, 2, 3 of first conductive type. Region 2 has less doping than regions 1, 3. Device 100 comprises bipolar conducting structure which comprises regions 4 and 5 of a second conductive type. Device 100 comprises first and second terminals 10, 20 coupled to regions 1 and 3, 5 respectively. First conduction path P1 between terminals 10, 20 uses regions 1, 2 and 3. Second conduction path P2 between terminals 10, 20 uses regions 2, 4 and 5. Path P1 switched ON and OFF at first frequency using control signal during ON state of device 100. Path P2 operates in high conductivity mode during off-phase (T1, figure 2) of path P1 and in low conductivity mode during on-phase T2 of path P1.

Description

Power Semiconductor Device
Technical Field
The present disclosure relates to a power semiconductor device. More particularly, but not exclusively, the present disclosure relates to a power switch for use in power electronics applications.
Background
A power semiconductor device is a semiconductor device used in power electronics applications. Such a device is also called a power device. In general, a power device has a rated voltage (i.e. the potential difference that the device has to withstand in an OFF state between its main terminals) of over 20V and conducts more than 100mA during its ON state. More commonly the ratings of a power device are above 60V and above 1A. These values make the power devices very different from low voltage devices, which operate with voltages typical below 5V and conduct currents typically under 1 mA and more commonly in the range of pAs or sub pAs. Another differentiation between power devices and other types of devices (such as low voltage or radio frequency (RF) devices) is that power devices mainly operate with large signals and behave like switches. An exception to that is found in high voltage or power amplifiers, which include specialised power transistors mainly used in linear operation. It is not uncommon for a power semiconductor device to carry an electric current of the order of around 10A to 3000A in its ON state and to block a voltage of the order of around 100V to 10000V in its OFF state. Commonly used power semiconductor devices include power diodes, thyristors, bipolar junction transistors (BJTs), power metal-oxidesemiconductor field-effect transistors (MOSFET), and Insulated-gate bipolar transistors (IGBT).
Power semiconductor devices are commonly used as switches or rectifiers in power electronics applications. A switch is an electronic device that can make or break an electrical circuit. A switch has an ON state during which an electric current can flow through the switch and an OFF state during which a current cannot flow through the switch. A switch is typically used to conduct current and block voltage in the same direction. In other words, the switch operates such that during the ON state a current flows from a first terminal to a second terminal of the switch, and the potential at the first terminal higher than the potential at the second terminal, and during the OFF state, the switch is able to withstand a voltage applied across the switch with the potential at the first terminal higher than the potential at the second terminal without conducting any significant current therebetween. A switch generally has a third terminal which functions as a control terminal for setting and switching the ON/OFF state of the switch. The voltage drop across the switch during the ON state is referred to as the “on-state voltage” of the switch. The on-state voltage is determined by the configuration and the material of the switch. Preferably, the on-state voltage should be as low as possible in order to reduce power loss and to improve the efficiency of the switch. The current flowing through a switch during its ON state shall be lower than the current rating of the switch, and the voltage applied across the switch during its OFF state shall be lower than the voltage rating of the switch. Otherwise, the switch will risk breaking down.
Currently for switching loads at DC voltages exceeding 400V the choice is between MOSFETs (in particular super-junction MOSFETs), insulated-gate bipolar transistors (IGBT), bipolar junction transistors (BJTs) and high voltage thyristors, plus the new technology options such as silicon carbide (SiC) FETs and Gallium nitride (GaN) FETs on the horizon. Each of these existing power switches has advantages and disadvantages and therefore is targeted to different types of applications.
BJT is a very mature technology and is relatively cheap to manufacture. Further, BJTs can switch high current loads at high voltages while achieving very low on-state voltages. However, to carry high current, BJTs must have relatively large base current, which requires separate base drive circuitry and supply. Further, a BJT used in power electronics applications generally has a large amount of charge stored in the base when the BJT is driven into saturation. The stored charge limits turn-off time of the BJT and therefore limits its frequency of operation in switching applications.
By contrast, MOSFETs are voltage-driven and can be controlled directly from ICs. Being majority carrier devices MOSFETs can switch loads at a very high frequency. Super-junction technology can achieve a very low on-state voltage. However, superjunction MOSFETs are still relatively expensive to manufacture, and in practice are limited to a voltage rating of lower than 1000V. The older technology of planar MOSFETs are much cheaper to manufacture and can be used to achieve a voltage rating of higher than 1000V. However, a planar MOSFET typically has a high on resistance (Rds(oh)) due to the series resistance ot the lowly doped region required for supporting high voltages. The high on-resistance means that the planar MOSFET can only be used at relatively low current densities and generally cannot achieve a high current rating.
IGBTs combine the easy-to-drive advantages of MOSFETs with a bipolar action to achieve a reasonably low on-state voltage at moderate to high current densities. The presence of stored charge from bipolar operation towers the effective series resistance of the lowly doped region. IGBTs are cheaper than super-junction MOSFETs to manufacture (though still significantly more expensive than high voltage BJTs), and can be used to achieve a voltage rating of more than 1000V. As with BJTs, the presence of stored charge within IGBTs limits the frequency of operation, though recent advances have made such devices suitable for operation up to 30-50 kHz. The on-state characteristic of an IGBT has a knee voltage which cannot be eliminated. Because of this knee voltage, the on-state voltage of an IGBT can never be lower than 0.7V, and in practice are mostly higher than 1V. In contrast, MOSFETs and even BJTs can achieve on-state voltages lower than 0.5V at suitable current densities. The degree of bipolar action in an IGBT is also typically limited by design, to ensure that it can be turned off via the gate of the IGBT. Hence, IGBTs are not suitable for operation at very high current densities.
High voltage thyristors, including Silicon-controlled rectifiers (SCRs) and gate turn-off thyristors (GTOs), are popular for industrial motor control applications. They benefit from a very strong bipolar action and can be used at very high current densities, achieving a low on-state voltage even where the voltage rating is very high (e.g., higher than 2000V). The on-state voltage, however, still has a “knee” as in IGBTs, and the strong bipolar action leads to very high stored charge, limiting the operation frequency of high voltage thyristors to around 1 kHz. SCRs also have the disadvantage of not being possible to turn off via the gate alone. Although GTOs can be turned off via the gate, they typically require high power gate drive circuits to facilitate this turn-off.
Compound semiconductor switches such as GaN and SiC FETs have many advantages and overcome a lot of the drawbacks of the various device types above, but at the moment their high cost still limits their use to specialist applications.
Thus there is a need for a cost effective power semiconductor device which can be used as a switch in power electronics applications and also provides low on-state voltage and high efficiency.
It is an object of the present disclosure, among others, to provide such a cost effective power semiconductor device.
Summary
According to a first aspect of the present disclosure there is provided a power semiconductor device, comprising: a semiconductor substrate comprising: a unipolar conducting structure comprising a first region of a first conductive type, a second region of the first conductive type, and a third region of the first conductive type, wherein the second region has a lower doping concentration than the first region and the third region; and a bipolar conducting structure comprising a fourth region of a second conductive type opposite to the first conductive type, the second region, a fifth region of the second conductive type; a first terminal operatively coupled to the first region; and a second terminal operatively coupled to the third region and the fifth region. The unipolar conducting structure is operable to provide a first conduction path between the first terminal and the second terminal using at least the first, second and third regions. The bipolar conducting structure is operable to provide a second conduction path between the first terminal and the second terminal using at least the fourth region, the second region and the fifth region. The first conduction path is configured to be switched on and off at a first frequency under application of a control signal during an ON state of the power semiconductor device, and the second conduction path is configured to operate in a high conductivity mode during an off-phase of the first conduction path and to operate in a low conductivity mode during an on-phase of the first conduction path.
By providing a bipolar conducting structure and a unipolar conducting structure on the same semiconductor substrate which share a common lowly doped second region designed to achieve a high-voltage rating, and by alternating conduction through a first conduction path provided by the unipolar conducting structure and a second conduction path provided by the bipolar conducting structure at a first frequency, the conduction of the bipolar conducting structure during an off-phase of the first conduction path allows the on-state voltage of the unipolar conducting structure to be reduced during the on-phase of the first conduction path. Accordingly, advantageously, the device can achieve an average on-state voltage which is lower than each of the onstate voltage of the bipolar conducting structure and the original on-state voltage of the unipolar conducting structure. Therefore, the device can achieve high efficiency and low power loss.
The term “terminal” may be used interchangeably with “electrode”.
It will be understood that the unipolar conducting structure refers to a semiconductor structure which uses only one type of charge carriers during electrical conduction. For example, a MOSFET and a Schottky diode are unipolar conducting structures. Because the charge carriers involved are the majority carriers, the unipolar conducting structure may also be referred to as a majority carrier conducting structure.
The first conduction path may be an electrically resistive conduction path.
The bipolar conducting structure refers to a semiconductor structure which uses both types of charge carriers (i.e., electrons and holes) during electrical conduction. For example, a bipolar junction transistor (BJT), a thyristor, an IGBT and a PN junction diode are bipolar conducting structures. Because both majority and minority carriers are involved during the conduction of the bipolar conducting structure, the bipolar conducting structure may also be referred to as a minority carrier conducting structure.
The terms “high conductivity mode” and “low conductivity mode” may also be referred to as “a first conductivity mode” and “a second conductivity mode”, respectively, with the first conductivity mode providing a higher conductivity level than the second conductivity mode. In general, the current flowing through the bipolar conducting structure during the low conductivity mode is at a level much lower than the current level flowing through the bipolar conducting structure during the high conductivity mode. The current flowing through the bipolar conducting structure during the low conductivity mode is also much lower than the current flowing through the first conduction path during the on-phase of the first conduction path. Therefore, the second conduction path and the bipolar conducting structure may also be considered as being “turned off” during the low conductivity mode.
The second region may be configured to receive conductivity modulation due to at least minority carriers injected from the fifth region into the second region when the second conduction path operates in the high conductivity mode.
The first conduction path may be in parallel to the second conduction path.
This parallel arrangement allows the unipolar conducting structure to enjoy the benefit of conductivity modulation due to the conduction of the bipolar conducting structure, yet without introducing a knee voltage of the bipolar conducting structure into the conduction characteristics of the entire ON state of the device.
The power semiconductor device may be operable to have an ON state during which an electric current flows between the first and second terminals using at least one of the first and second conduction paths, and an OFF state during which an electric current does not flow between the first and second terminals.
The power semiconductor device is a power switch. The power switch may be a bidirectional switch.
The bipolar conducting structure may comprise a gate terminal operatively coupled to the fourth region. The gate terminal may be operable to receive a gate signal for activating a current flow through the bipolar conducting structure. The power semiconductor device may be configured to enter the ON state from an OFF state upon application of the gate signal and the control signal.
The semiconductor substrate may be a monolithic silicon substrate. The first to fifth regions may be regions of the silicon substrate doped with different types and/or different levels of impurities.
The third region may have a first surface and a second surface opposite to the first surface. The second terminal may be electrically coupled to the second surface of the third region. The second region may be disposed on the first surface of the third region.
The second region may have a first surface and a second surface which is opposite to the first surface and faces the third region.
The fourth region may be disposed within the second region adjacent to the first surface of the second region.
The first region may be disposed adjacent to the first surface of the second region.
The fifth region may have a first surface and a second surface opposite to the first surface. The second terminal may be electrically coupled to the second surface of the fifth region.
The second region may be disposed on the first surface of the fifth region.
A time duration of the on-phase of the first conduction path may be configured to be longer than a time duration of the off-phase of the first conduction path during the ON state of the power semiconductor device.
A time duration of the on-phase of the first conduction path within at least one cycle of the control signal may be shorter than a time duration during which a fraction of the injected carriers disappear through recombination with majority carriers of the second region.
The fraction of the injected carriers may be a substantial fraction of the injected carriers. Optionally, the fraction may be of a value between 50% to 95%.
The first frequency may be between 10KHz to 10MHz.
The fifth region and the third region may be embedded within the substrate below the second region.
The unipolar conducting structure may comprise a metal-oxide-semiconductor (MOS) gate structure. The MOS gate structure may comprise a channel region of the second conductive type disposed between the first region and the second region, and a gate electrode for generating an electric field in the channel region to invert the conductivity type of the channel region so as to form a conducting channel between the first and second regions.
The gate electrode may be configured to receive the control signal to switch on and off the conducting channel of the MOS gate structure so as to switch on and off the first conduction path.
The first region may be disposed within the fourth region, and the bipolar conducting structure may comprise the first region.
The power semiconductor device may further comprise a switch connectable between the first terminal and the first region, and the switch is configured to receive the control signal to switch on and off the first conduction path.
The first region may be disposed within the fourth region. The bipolar conducting structure may comprise a sixth region of the first conductive type, and the sixth region may be disposed within the fourth region and may be spaced apart from the first region.
The first region may be in direct contact with the second region. The power semiconductor device may further comprise a switch connectable between the first terminal and the first region, and the switch may be configured to receive the control signal to switch on and off the first conduction path. The bipolar conducting structure may comprise a sixth region of the first conductive type, and the sixth region is disposed within the fourth region.
The power semiconductor device may comprise a first electrode portion electrically connected to the sixth region and a second electrode portion electrically connected to the first region. The term “electrode portion” may be used interchangeably with the term “metallisation contact”. The first electrode portion may be spaced apart from the second electrode portion. The switch may be electrically connected between the first terminal and the second electrode portion. The first electrode portion may be electrically connected to the first terminal.
The switch described above may be a low-voltage switch. It will be understood that the term “low-voltage switch” means that the switch has a voltage rating which is lower than a voltage rating of the power semiconductor device.
The switch described above may be formed on a further semiconductor substrate separate from the semiconductor substrate. The semiconductor substrate and the further semiconductor substrate may be enclosed in a single package.
The bipolar conducting structure may comprise a plurality of conducting cell connected in parallel between the first and second terminals. The sixth region may include a plurality of sixth sub-regions spaced apart from one another. The fourth region may include a plurality of fourth sub-regions spaced apart from one another. At least one of the sixth sub-regions may be disposed within one of the fourth sub-regions, forming one of the conducting cells with the second region and the fifth region. At least one of the sixth sub-regions may be operatively connected to the first terminal.
The fourth sub-regions may be spaced apart from one another at a distance which is configured such that during the OFF state of the device, depletion regions within the second region which are associated with adjacent fourth sub-regions collectively pinch off the first conduction path before the switch connectable between the first region and the first terminal breaks down.
The fifth region may include a plurality of fifth sub-regions spaced apart from one another. At least one of the fifth sub-regions may be disposed below one of the fourth sub-regions.
The first region may comprise at least one first sub-region spaced apart from one another, and the at least one first sub-region is disposed between adjacent ones of the fourth sub-regions.
Alternatively, the first region may comprise at least one first sub-region spaced apart from one another. The at least one first sub-region may be disposed within one of the fourth sub-regions and may have a boundary substantially aligned with a boundary of the one of the fourth sub-region such that the at least one first sub-region is in direct contact with the second region.
The doping concentration and a thickness of the second region may be configured such that the power semiconductor device is able to support a voltage with an amplitude of, but not limited to, 600V to 800V between the first and second terminals during the OFF state.
According to a second aspect of the present disclosure there is provided a method of operating a power semiconductor device, the power semiconductor device comprising: a semiconductor substrate comprising: a unipolar conducting structure comprising a first region of a first conductive type, a second region of the first conductive type, and a third region of the first conductive type, wherein the second region has a lower doping concentration than the first region and the third region; and a bipolar conducting structure comprising a fourth region of a second conductive type opposite to the first conductive type, the second region, a fifth region of the second conductive type; a first terminal operatively coupled to the first region; and a second terminal operatively coupled to the third region and the fifth region, the method comprising: providing a first conduction path between the first terminal and the second terminal using the first, second and third regions; applying a control signal to switch on and off the first conduction path at a first frequency during the ON state of the power semiconductor device; providing a second conduction path between the first terminal and the second terminal using the fourth region, the second region and the fifth region; and controlling the second conduction path to operate in a high conductivity mode during an off-phase of the first conduction path, wherein the second conduction path operates in a low conductivity mode during an on-phase of the first conduction path.
Where appropriate any of the optional features described above in relation to one of the aspects of the present disclosure may be applied to another one of the aspects of the disclosure.
It will be appreciated that the power semiconductor device of the present disclosure is applicable in various power electronics applications, not limited to the use as a power switch.
Brief Description of the Drawings
In order that the disclosure may be more fully understood, a number of embodiments of the disclosure will now be described, by way of example, with reference to the accompanying drawings, in which:
Fig. 1 is a schematic representation of a cross-section of a power semiconductor device according to a first embodiment of the present disclosure;
Fig. 2 is a schematic representation of input and output waveforms during the ON state of the power semiconductor device of Fig. 1;
Fig. 3 is a schematic representation of a cross-section of a power semiconductor device according to a second embodiment of the present disclosure;
Fig. 4 is a schematic representation of a cross-section of a power semiconductor device according to a third embodiment of the present disclosure;
Fig. 5 is a schematic representation of a cross-section of a power semiconductor device according to a fourth embodiment of the present disclosure;
In the drawings, like parts are denoted by like reference numerals. Further, in each drawing, a part denoted by a reference numeral in the format of N-i has equivalent characteristics to another part denoted by a reference numeral N.
It will be appreciated that the drawings are for illustration purposes only and are not drawn to scale.
Detailed Description of the Preferred Embodiments
Fig. 1 schematically illustrates a cross-section of a power semiconductor device 100 according to a first embodiment of the present disclosure. The device 100 is formed on an N+ silicon substrate 3. Parts of the substrate 3 are reversely doped to form a P+ region 5 and a P+ region 5-2. The P+ regions 5, 5-2 are formed on a bottom surface of the silicon substrate. An electrode 20 is electrically coupled to the bottom surfaces of the P+ regions 5, 5-2 and the N+ substrate 3. Although Fig. 1 shows that the N+ substrate 3 has the same thickness as the P+ regions 5, 5-2, it will be appreciated that the N+ substrate 3 may extend further towards a top surface of the device 100 and therefore may be thicker than the P+ regions 5, 5-2.
A lowly doped N- drift region 2 having a thickness t2 is disposed on the top surfaces of the N+ substrate 3 and the P+ regions 5, 5-2. The N- drift region 2 may have a doping concentration of, but not limited to, about 1013 cm-3 to 1015 cm'3. The thickness t2 may, for example, be of the order of tens of micrometres (pm). It will be appreciated that the particular value of the thickness t2 depends upon the voltage rating of the device 100. The N- drift region 2 may be an epitaxial layer. A P+ well 4 is provided in the N- drift region 2 adjacent to a top surface of the N- drift region 2. A N+ region 1 is provided in the P+ well 4 and is also adjacent to the top surface of the N- drift region 2. The “top surface” and the “bottom surface” used above may also be referred to as “a first surface” and “a second surface” which is opposite to the first surface, respectively. The P+ well 4 and the N+ region 1 may be formed by double diffusion processes. The Ndrift region 2 has a lower doping concentration than the substrate 3 and the N+ region 1.
A metal contact 8 is provided in direct contact with the P+ well 4 and is further connected to a gate terminal 40. A metal contact 9 is provided in direct contact with the N+ region 1 and is further connected to an electrode 10. The contacts 8, 9 are metallisation contacts directly in contact with semiconductor. For example, the contacts 8, 9 may be made of a material selected from, but not limited to, the group of aluminium, copper, gold, titanium or their alloys. The contacts 8, 9 may also be referred to as “electrodes”.
The N+ region 1, the N- drift region 2, the N+ substrate 3, the P+ well 4 and the P+ region 5 may also be referred to as the “first region”, the “second region”, the “third region”, the “fourth region” and the “fifth region” of the device 100, respectively. These regions are formed by doping respective impurities into silicon. The electrodes 10 and 20 may be referred to as the “first electrode” and the “second electrode” of the device 100, respectively, or the “first terminal” and the “second terminal” of the device 100, respectively.
The device 100 further includes a MOS gate structure, which includes an insulated gate 16, a channel region 15 along a top surface of the P+ well 4 between the N+ region 1 and the N- drift region 2 and a gate oxide layer 17 between the gate 16 and the channel region 15. A gate electrode 30 is electrically coupled to the gate 16. When a positive voltage is applied between the gate electrode 30 and the first electrode 10 (i.e., the potential at the gate electrode 30 being higher than the potential at the first electrode 10), the electric field generated by the voltage penetrates through the oxide layer 17 and inverts the conductivity type of the channel region 15 so as to create an Ntype inversion layer (i.e., an N channel) at the interface between the P+ well 4 and the oxide layer 17. The inversion layer provides a conductive channel through which a current can flow between the N+ region 1 and the N- drift region 2.
Therefore, when a positive voltage is applied between the gate electrode 30 and the first electrode 10, there is provided a first conduction path P1 between the first electrode 10 and the second electrode 20, via the N+ region 1, the inverted channel region 15, the N- drift region 2 and the N+ substrate 3.
Similar to a typical MOSFET, the first conduction path P1 uses only one type of charge carriers, i.e., electrons, for the electrical conduction. Electrons are the majority carriers of the N+ region 1, the inverted channel region 15, the N- drift region 2 and the N+ substrate 3. Therefore, the first conduction path P1 may also be referred to as a unipolar conduction path or a majority carrier conduction path. Accordingly, the N+ region 1, the N- drift region 2, the N+ substrate 3, the channel region 15, and the MOS gate structure collectively form a unipolar conducting structure.
As the first conduction path P1 is resistive, the on-state characteristic of the unipolar conducting structure has no knee voltage. The on-resistance (RDs(on)) of the unipolar conducting structure includes the resistance of the N+ region 1, the resistance of the inverted channel region 15, the resistance of the N- drift region 2, and the resistance of the N+ substrate 3, which are connected in series with each other.
A relatively thick and lowly doped N- drift region 2 is necessary for the unipolar conducting structure to block a high voltage applied between the first and second electrodes 10, 20. Such a lowly doped region therefore has high resistivity. The series resistance in the N- drift region 2 increases with the voltage rating of the device 100 and typically represents the biggest contribution to the total on-resistance of the first conduction path P1. Meanwhile, the presence of the lowly doped N- drift region 2 is necessary in order for the device 100 to achieve a high voltage rating, and it is not feasible to embed (e.g., by a diffusion process) more impurities (e.g., Phosphorus) into the drift region 2 to increase its doping concentration. Therefore, the lowly doped N drift region 2 poses as a challenge for reducing the voltage drop across the unipolar conducting structure during the conduction of the path P1.
The P+ region 5, the N- drift region 2, the P+ well 4, the N+ region 1 and the gate terminal 40 form a PNPN thyristor-like structure, in particular, a SCR-type thyristor. This thyristor structure provides a second conduction path P2 between the first electrode 10 and the second electrode 20 via the P+ region 5, the N- drift region 2, the P+ well 4 and the N+ region 1. The first conduction path P1 and the second conduction path P2 are connected in parallel between the electrodes 10 and 20.
The second conduction path P2 can be turned on by applying a positive voltage between the second electrode 20 and the first electrode 10 (i.e., the potential at the second electrode 20 being higher than the potential at the first electrode 10) and at the same time supplying a current to the gate terminal 40 with the current flowing into the P+ well 4. The second conduction path P2 conducts in only one direction, i.e., from the second electrode 20 to the first electrode 10. It will be appreciated that applying the positive voltage alone without supplying the current is not sufficient to turn on the second conduction path P2 since the reverse-biased PN junction formed between the P+ well 4 and the N- drift region 2 blocks a current flow through the path P2. The current flowing into the P+ well 4 is essential to trigger the conduction of the path P2. In more detail, the thyristor structure operates like two BJT connected together. The N+ region 1, the P+ well 4 and the N- drift region 2 form the first BJT, while the P+ well 4, the N- drift region 2 and the P+ region 5 form the second BJT. When a positive voltage is applied between the second electrode 20 and the first electrode 10, the current flowing into the P+ well 4 effectively flows into the base of the first BJT, thereby turning on the first BJT. Once the first BJT is switched on, current flows through the P+ well 4 and the N- region 2, thereby activating the base (i.e., the N- drift region 2) of the second BJT and turning on the second BJT. Once both of the first and second BJTs are turned on, current is able to flow from the second electrode 20 to the first electrode 10 along the path P2 via the P+ region 5, the N- drift region 2, the P+ well 4, the N+ region 1 sequentially.
When the path P2 is fully conducting, the N- drift region 2 is filled within minority carriers (i.e., holes in this case) injected from the P+ region 5. Further, the N- drift region 2 may further be filled with electrons drifted from the N+ region 1 across the P+ well 4, provided that the part of the P+ well 4 disposed between the N+ region 1 and the N- drift region 2 is not too thick and not too highly doped. In a non-limiting example, the thickness of the P+ well between the N+ region 1 and the N- drift region 2 may be between 1pm to 5pm. These carriers temporarily enhance the conductivity and reduce the effective resistance of the N- drift region 2, which, depending on the required maximum reverse voltage, may have a thickness in the order of several tens of micrometres (pm). This effect is referred to as conductivity modulation of the N- drift region 2. It will be appreciated that the minority carriers injected from the P+ region 5 may play a significant role in the conductivity modulation of the N- drift region 2.
it will be appreciated that once the path P2 is switched on, it cannot be turned off simply by removing the current supplied to the gate terminal 40. The path P2 remains highly conductive until the current flowing through the path P2 drops below a threshold value called “holding current”. The current supplied to the gate terminal 40 for triggering the conduction of the path P2 can be very low (e.g., of the order of several mAs), and can be supplied directly from an IC, without requiring a separate base-drive supply as for a typical BJT.
The conduction of the path P2 requires diffusion of both electrons and holes. Therefore the second conduction path P2 may be referred to as a bipolar conduction path or a minority carrier conduction path. Accordingly, P+ region 5, the N- drift region 2, the P+ well 4, the N+ region 1 collectively form a bipolar conducting structure. Due to the existence of three PN junctions formed within the bipolar conducting structure, there exists a knee voltage of around 1V in the conduction l-V characteristics of the bipolar conducting structure. The knee voltage is determined by the nature of the bipolar conducting structure and cannot be eliminated.
The device 100 may be used as a power switch. As described above, a switch is typically used to conduct current and block voltage in the same direction. The device can operate as a switch having an ON state and an OFF state when the potential at the second electrode 20 is higher than the potential at the first electrode 10.
In order to achieve the OFF state, both the paths P1 and P2 must be kept off. The path P1 can be kept off by applying a low voltage (including 0V) to the gate electrode 30 such that the voltage difference between the gate electrode 30 and the first electrode become lower than the threshold voltage for making the N channel within the channel region 15 (which means the path P1 cannot be established in the OFF state). The path P2 can be kept off by not supplying any current to the gate terminal 40, thereby not triggering the path P2. Accordingly, current cannot flow from the second electrode 20 to the first electrode 10 and the device operates in the OFF state.
In order to achieve the ON state, at least one of the paths P1 and P2 is generally turned on. The path P1 can be turned on by applying a relatively high voltage to the gate electrode 30 such that the voltage difference between the gate electrode 30 and the first electrode 10 become higher than the threshold voltage for making the N channel. The path P2 can be turned on by supplying a current to the gate terminal 40. The current flows into the P+ well 4 to trigger the conduction of the path P2. In this way, a current can flow from the second electrode 20 to the first electrode 10 via one or both of the paths P1 and P2, and the device 100 operates in the ON state.
As described above, the voltage drop along the path P1 may be substantial due to the highly resistive N- drift region 2, and the path P2 suffers from a knee voltage of around 1V which cannot be eliminated. In order to reduce the on-state voltage of the device 100 (i.e., the voltage drop between the second electrode 20 and the first electrode 10 during the ON state), the device 100 is controlled to dynamically increase the charge carrier concentration of the N- drift region 2, thereby decreasing the resistance of the N- drift region 2 (without actually embedding more impurities into the region 2) during the ON state of the device 100. This is described in more detail below.
Fig. 2 illustrates waveforms of a current lG supplied to the gate terminal 40 of the bipolar conducting structure, a voltage VGS applied between the gate electrode 30 and the first electrode 10, and the resulting on-state voltage V0N between the second electrode 20 and the first electrode 10, during the ON state of the device 100. For illustration purposes only, the time duration of the ON state is shown as t0N.
As shown in Fig. 2, instead of having the gate 16 biased positive constantly to induce the presence of the N channel during the whole period t0N of the ON state, a fast switching on-off pulse VGS is applied to the gate electrode 30 to periodically switch on and off the N channel within the channel region 15, thereby periodically switching on and off the first conduction path P1. The frequency of VGS may be, for example, between 10 kHz and 10 MHz. The on/off switching frequency of the N channel and the first conduction path P1 is substantially the same as the frequency of VGS.
The period of VGS is T, which includes an off-phase T1 during which the N channel is switched off and an on-phase T2 during which the N channel is switched on.
During the off-phase T1, the first conduction path P1 is switched off. However, a current pulse lG with a time duration of T3 is supplied to the gate terminal 40 to activate the second conduction path P2 at the beginning of the off-phase T1. In this way, the second path P2 is turned on at the start of the first off-phase T1 of the ON period tGN· For the second and subsequent off-phases T1, the rising edge of the current pulse lG may be aligned with the falling edge of VGS, such that the second path P2 is switched on for the entire time duration of each off-phase T1. Once the path P2 is activated, current will flow from the second electrode 20 to the first electrode 10 through the bipolar conducting structure, regardless of whether or not a current pulse lG is being supplied to the gate terminal 40.
During the conduction of the path P2, the on-state voltage V0N during the off-phase T1 is around 1V (i.e., the knee voltage of the on-state characteristics of the bipolar conducting structure). As described above, the N- drift region 2 receives conductivity modulation during the conduction of the path P2, which is mainly due to minority carriers (i.e., holes in the device 100) injected from the P+ region 5 into the N- drift region 2. Due to the quasi-charge neutrality constraint, the injected minority carriers will also lead to an increase in majority carriers (i.e., electrons) in the N- drift region 2 during the subsequent on-phase T2 as described below. The presence of excess carriers within the N- drift region 2 temporarily enhance the conductivity and reduce the resistivity of the N- drift region 2.
When the N channel is turned on during the on-phase T2, both the first conduction path P1 and the second conduction path P2 are conducting at the beginning of the on-phase T2. It will be appreciated that current will tend to flow through a path having a lower resistance. Due to conductivity modulation received by the N- drift region 2 during the off-phase T1, the instantaneous on-resistance of the first conduction path P1 has been greatly reduced from its normal level, since the biggest contributor to this resistance the N- drift region 2 - has its effective resistance reduced by the presence of injected minority carriers. Therefore, current tends to flow through the first conduction path P1 and the instantaneous on-state voltage of the path P1 drops to a level which is much lower than the knee voltage of the path P2. The level of V0N is illustrated as being about 0.1V in Fig. 2 as an example, but may vary depending on the configuration of the unipolar conducting structure and the current density flowing through the path P1.
Because majority (if not all) of the current is directed to the path P1, the current flowing through the path P2 drops below the holding current of the bipolar conducting structure. Accordingly the path P2 is automatically turned off or enters a very low conductivity mode. Therefore, the time duration T3 of the current pulse Ig may optionally be shorter than, equal to or larger than the duration of the off-phase T1. It will be appreciated that although Fig. 2 shows that a current pulse lG is applied to the gate terminal 40 at the beginning of each off-phase T1, the current applied to the gate terminal 40 may alternatively remain on during the entire period of the ON state. It will be appreciated that when the current flowing through the path P2 drops below the holding current, the path P2 is automatically turned off if the current pulse lG is not being supplied to the gate terminal 40. However, if the current pulse lG continues to be supplied to the gate terminal 40 during the on-phase T2, the bipolar conducting structure still conducts a very low level of current through the path P2 and therefore operates in a low conductivity mode. The low level of current through the path P2 in the low conductivity mode is almost negligible as compared to the current level flowing through the path P1 during the on-phase T2. The constant presence of a current applied to the gate terminal 40 during the ON state ensures that when the first conduction path P1 is turned off, the second conduction path P2 is automatically turned on. Further, when the path P1 is turned on, conduction of the path P1 will cause the path P2 to enter the low conductivity mode and a majority of the current flowing between the electrodes 10, 20 flows through the path P1.
With the on-phase T2 continuing, the minority carriers injected into the N- drift region 2 begin to disappear through recombination with the majority carriers within the N- drift region 2. Therefore, the effective resistance of the N- drift region 2 increases during the on-phase T2 as shown in Fig. 2, causing the on-state voltage of the device 100 to gradually increase over time.
Typically, the minority carrier lifetime in the N- drift region 2 is such that the recombination process occurs over several microseconds. In an example, the recombination process may take at least around 10 microseconds. It will be appreciated that preferably the time duration of the on-phase T2 is shorter than the lifetime of the injected minority carriers. In a further example, the time duration of the on-phase T2 may be shorter than a time duration for a fraction of the injected carriers to disappear through recombination. The fraction may be a substantial fraction and may have a value between, for example, 50% to 95%.
By repeating the off-phase T1 and the on-phase T2 of VGS and supplying the current pulse lG at the beginning of each off-phase T1, during the entire time period t0N of the ON state of the device, current flowing from the second electrode 20 to the first electrode 10 alternates between the path P2 and the path P1 at a frequency equal to 1/T. By making the frequency 1/T suitably high (i.e., by reducing the time duration of one or both of the off-phase T1 and the on-phase T2), the minority carriers injected into the N- drift region 2 during the off-phase T1 may be mostly present for the whole of the on-phase T2, thereby causing the on-state voltage of the path P1 to stay low throughout the entire on-phase T2. As shown in Fig. 2, the on-state voltage gradually rises as the injected carriers recombine during the on-phase T2, but before the on-state voltage has significantly increased the N channel is turned off again and a current pulse lG is applied to the gate terminal 40, causing the second conduction path P2 to turn on, thereby “replenishing” the injected carriers of the N- drift region 2. Further, the conduction path during on-phase T2 (i.e., the first conduction path P1) is purely resistive, and does not have any PN junction and therefore has no knee voltage.
Fig. 2 shows that the on-phase T2 has a longer time duration than the off-phase T1. The exact ratio of the off-phase T1 and the on-phase T2 can be optimised to obtain the maximum benefit. In general, optimum performance may be obtained by having the offphase T1 as short as possible but long enough to have established a high level of conductivity modulation in the N- drift region 2, and by having the on-phase T2 as long as possible without letting the on-state voltage rise too much from its initial low value. In this way, the average on-state voltage of the device 100 is much lower than the knee voltage of the bipolar conducting structure. The device 100 therefore can achieve a performance comparable with the performance achieved by super-junction structures or compound semiconductors, but can be manufactured in a more cost-effective manner than super-junction structures or compound semiconductors.
It will be appreciated that the N- drift region 2 is preferably made of a semiconductor material with a relatively high minority carrier lifetime. This allows the time duration of the on-phase T2 to be extended with respect to the time duration of the off-phase T1. Accordingly, the average on-state voltage of the device 100 can be further reduced to a lower level, due to the very low on-state voltage provided by the path P1 during the onphase T2.
High minority carrier lifetime within the N- drift region 2 may be achieved by using a low defect-density silicon structure as the material of the N- drift region 2. In an example, a back-diffused homogeneous wafer is used as the starting material for making the device 100, in which the N- drift region 2 is already provided by the wafer and would not be an epitaxial layer made by an epitaxial process on the substrate 3. The N- drift region 2 made in this way has a low defect density, and thus the minority carrier lifetime in the N- drift region 2 is relatively high. In a further example, the N- drift region 2 is an epitaxial layer made by an epitaxial process, and an annealing process is performed on the epitaxial layer to reduce the structural defects therein.
For example, the time duration of the off-phase T1 may be from several nanoseconds to several microseconds. It has been found that there exists a minimum time duration of the off-phase T1 in order to allow the bipolar conducting structure to conduct so as to fully modulate the conductivity of the N- drift region 2. Further, it has been found that prolonging the minimum time duration may not necessarily further enhance the conductivity of the N- drift region 2. The minimum time duration varies with the particular doping and thickness configurations of the device 100, the current density flowing through the device 100, the operating temperature, and other external conditions, and may typically be within the range of 0.5 to 2 microseconds. The time duration of the on-phase T2 may preferably be around 5 to 15 microseconds. The duty cycle of the signal VGS which produces low VON is generally in the range of 80% to 95%. It will be appreciated that the particular values of the time periods and the duty cycle described above are examples only, and the practical operation of the device 100 is in no way limited to those figures.
Fig. 2 shows that the time duration t0N of the ON state of the device 100 is equal to three times the period T of VGS. It will be appreciated that this is merely for illustration, and that the time duration t0N may be equal to i*T, with i being an integer equal to or larger than one. Further, the ON state of the device 100 must end within an on-phase T2 and cannot end within an off-phase T1. If the ON state ends within an off-phase T1, the second conduction path P2 remains on due to the latching effect of the thyristor-like bipolar conducting structure even if the current pulse lG is removed, and it will not be possible to switch off the current flow from the second electrode 20 to the first electrode 10. It will be appreciated that any control logic responsible for generating the signals VGS and lG can be easily programmed by the skilled person to ensure that the real switching between the ON state and the OFF state of the device 100 happens within an on-phase T2.
Conductivity modulation is also used in bipolar power devices such as IGBTs. However, the device 100 provides advantages over those bipolar power devices. In particular, the on-state characteristic of an IGBT has a knee voltage (at least 0.7V, generally larger than 1V in practice) which cannot be eliminated. The knee voltage is due to the presence of a PN junction connected in series in the current conduction path of an IGBT, and cannot be eliminated. In contrast, the device 100 is able to achieve an on-state voltage lower than the knee voltage of a typical bipolar conducting structure, by providing a unipolar conducting structure and a bipolar conducting structure connected in parallel to each other and alternating current between the two structures at a suitably high frequency. Further, although a typical IGBT includes a thyristor-like parasitic bipolar conducting structure, no thyristor action is desired to occur under any operating condition of the IGBT because the latch-up effect of the thyristor causes the fatal device failure. In contrast, the thyristor-like bipolar conducting structure of the device 100 is desired to be turned on in order to perform conductivity modulation to the N- drift region 2.
The device 100 may include a plurality of cells connected in parallel between the electrodes 10 and 20. The regions 1 to 5, the channel region 15, the metal contacts 8, 9, the gate 16 and the oxide layer 17 may form one cell of the device 100. Fig. 1 illustrates a second cell which includes an N+ region 1-2 electrically connected (not shown) to the first electrode 10 via a metal contact 9-2, a P+ well 4-2 electrically connected (not shown) to the gate terminal 40 via a metal contact 8-2, and a P+ region
5-2 electrically connected to the second electrode 20 . It will be appreciated that the N+ region 1-2, the P+ well 4-2 and the P+ region 5-2 work with the N- drift region 2, the N+ substrate 3, the gate 16 and the oxide layer 17 to provide a further unipolar conducting structure and a further bipolar conducting structure and function in the same way as described above. The device 100 may include thousands of cells in order to achieve a desired current rating. The cells share the N- drift region 2 and the N+ substrate 3. All of the first conduction paths of the cells may be collectively referred to as the “first conduction path” provided by the “unipolar conducting structure” of the device. All of the second conduction paths of the cells may be collectively referred to as the “second conduction path” provided by the “bipolar conducting structure” of the device.
Fig. 3 schematically illustrates a cross-section of a power semiconductor device 200 according to a second embodiment of the present disclosure.
In the device 100, the first conduction path P1 provided by the unipolar conducting structure is switched on and off by applying a drive pulse VGS to the gate electrode 30. The gate drive power consumption increases linearly with the frequency of the drive pulse VGS. Further, if the device 100 has a high voltage rating (e.g., 600V to 800V), the gate electrode 30 may have a large capacitance. It may therefore be difficult to drive the gate electrode 30 at a high frequency due to the large gate capacitance. Further, a large current may be required to drive the gate electrode 30 and therefore the power consumption for driving the gate electrode 30 may be substantial.
The device 200 solves this problem by providing a low voltage switch 12 connected in series between the first electrode 10 and the electrode 9, and by adding a further N+ region 6 within the P+ well 4. The N+ region 6 is spaced apart from the N+ region 1 and has a metal contact 18 which is electrically connected to the first electrode 10. The N+ region 6 may be referred to as the “sixth region” of the device 200. The low voltage switch 12 means a switch having a low voltage rating which is at least lower than the voltage rating of the device 200. Other elements of the device 200 are equivalent to the corresponding elements of the device 100 which are labelled using the same reference numerals. The switch 12 can be switched on and off under control of a control signal (not shown).
The N+ region 6, the P+ well 4, the N- drift region 2 and the P+ region 5 collectively form a thyristor-like bipolar conducting structure, which is operable to provide a second conduction path P2 between the first electrode 10 and the second electrode 20. The second conduction path P2 extends sequentially from the P+ region 5, the N- drift region 2, the P+ well 4 to the N+ region 6.
Same as the device 100, the N+ region 1, the N- drift region 2, the N+ substrate 3, the channel region 15, and the MOS gate structure collectively form a unipolar conducting structure. The unipolar conducting structure is operable to provide a first conduction path P1 between the first electrode 10 and the second electrode 20. The first conduction path P1 extends sequentially from the N+ substrate 3, the N- drift region 2, the channel region 15 to the N+ region 1.
Similar to the device 100, the device 200 can operate as a switch having an ON state and an OFF state when the potential at the second electrode 20 is higher than the potential at the first electrode 10.
During the ON state of the device 200, the gate electrode 30 is biased positive throughout the period of the ON state. That is, a high voltage (i.e., logic T voltage, general equal to the voltage level of a power supply) is constantly applied to the gate electrode 30. Therefore, an N channel is present within the channel region 5 throughout the period of the ON state. The on and off switching of the path P1 between the electrodes 10 and 20 during the ON state is accomplished by turning on and off the switch 12.
In particular, when the switch 12 is turned off, the electrode 9 is disconnected from the first electrode 10. Therefore, although the N channel is present in the channel region 5, no current can flow between the electrodes 10 and 20 via the path P1 and the path P1 is thus turned off by the switch 12. In the meantime, a current pulse Ig is supplied to the gate terminal 40 to activate the second conduction path P2. The conduction of the path P2 injects minority carriers from the P+ region 5 into the N- drift region 2.
When the switch 12 is turned on, the electrode 9 is electrically connected to the first electrode 10 and accordingly the first conduction path P1 conducts current between the electrodes 10 and 20. The conductivity of the first conduction path P1 is temporarily enhanced by the injected minority carriers. In the meantime, the second conduction path P2 is automatically switched off or enters a very low conductivity mode (depending upon the absence/presence of the current pulse lG as described above) once the current flowing through the path P2 drops below the holding current of the bipolar conducting structure.
By providing the N+ region 6 and connecting the metal contact 18 of the N+ region 6 directly to the first electrode 10, the second conduction path P2 bypasses the switch 12, thereby allowing current to flow through the second conduction path P2 during the off-phase of the first conduction path P1.
During the OFF state of the device 200, the path P1 is turned off by turning off the switch 12 as described above. Similar to the device 100, the path P2 is kept off by not supplying any current to the gate terminal 40, thereby not triggering the path P2. Accordingly, current cannot flow from the second electrode 20 to the first electrode 10. Similar to the device 100, switching between the ON state and the OFF state of the device 200 shall happen within an on-phase of the path P1 as described above.
The low voltage switch 12 may be a low voltage CMOS switch. The control signal for turning on and off the switch 12 may be applied to a gate of the switch 12. Such a low voltage CMOS switch has very low gate capacitance and can be turned on and off at a high frequency using a logic signal. There is no need to provide a large current for driving the switch 12. The power consumption for driving the switch 12 may be significantly lower than the power consumption for driving the gate electrode 30 of the device 100.
The switch 12 may be made on the same silicon substrate as the regions 1 to 6 of the device 200. Alternatively, the switch may be made on a separate silicon substrate, which may be further enclosed in a single package together with other parts of the device 200.
Fig. 3 illustrates a second cell of the device 200 which includes an N+ region 1-2 electrically connected (not shown) to the bottom node of the switch 12 via a metal contact 9-2, such that the switch 12 can switch on and off the first conduction path of the second cell. The second cell further includes an N+ region 6-2 electrically connected (not shown) to the first electrode 10 via a metal contact 18-2, a P+ well 4-2 electrically connected (not shown) to the gate terminal 40 via a metal contact 8-2, and a P+ region 5-2 electrically connected to the second electrode 20. The structure of the second cell is symmetric to that of the first cell. Therefore, it will be appreciated that the N+ region 1-2, the N+ region 6-2, the P+ well 4-2 and the P+ region 5-2 work with the N- drift region 2, the N+ substrate 3, the gate 16 and the oxide layer 17 to provide a further unipolar conducting structure and a further bipolar conducting structure which operate in the same way as described above.
Each of the devices 100 and 200 uses a gate-driven MOS structure (which includes the gate 16, the oxide layer 17 and the channel region 15) as part of the unipolar conducting structure. It will be appreciated that other types of unipolar conducting structure may be used, as shown in Fig. 4 and Fig. 5.
Fig. 4 schematically illustrates a cross-section of a power semiconductor device 300 according to a third embodiment of the present disclosure.
The device 300 differs from the devices 100, 200 in that the N+ region 1 of the device 300 is disposed outside of the P+ well 4, and the N+ region 1 is in direct contact with the N- drift region 2. Therefore, unless modulated otherwise (as described below), the N+ region 1 is always in electrical connection with the N+ substrate 3 via the N- drift region 2. Because the only charge carriers involved in this electrical connection are the majority carriers (i.e., electrons) of the regions 1 to 3, the N+ region 1, the N- drift region 2, and the N+ substrate 3 form a unipolar conducting structure which provides a first conduction path P1. The device 300 does not have a gate-driven MOS structure.
Similar to the device 200, the P+ well 4 is in contact with the metal contact 8, which is directly connected to the gate terminal 40, and the N+ region 6 which is disposed within the P+ well 4 is directly connected to the first electrode via the metal contact 18. The N+ region 1 is connected to the first electrode 10 via the series-connected low voltage switch 12. The P+ region 5 is electrically connected to the second electrode 20.
The N+ region 6, the P+ well 4, the N- drift region 2 and the P+ region 5 collectively form a thyristor-like bipolar conducting structure, which is operable to provide a second conduction path P2 between the first electrode 10 and the second electrode 20. The second conduction path P2 extends sequentially from the P+ region 5, the N- drift region 2, the P+ well 4 to the N+ region 6.
As shown in Fig. 4, the device 300 includes a plurality of cells. Each cell includes a N+ region 1-i which is connected to a bottom end of the switch 12, a P+ well 4-i, a N+ region 6-i which is disposed within the P+ well 4-i and electrically connected to the first electrode 10 via a metal contact 18-i, and a P+ region 5-i below the N- drift region 2. The numeral i varies from 2 to N, with N being the total number of the cells. N is equal to 5 in Figure 4 for illustration purposes only. The P+ wells 4, 4-2...4-N are spaced apart from each other with a spacing L. Each of the N+ regions 1, 1-2...1-N is disposed between adjacent P+ wells. The P+ regions 5-I are “scattered” within the N+ substrate 3. Each of the P+ regions 5-i is generally located below the respectively P+ well 4-i, in order to shorten the length of the N- drift region 2 between each pair of the P+ region 5-i and the P+ well 4-i. All of the cells share the switch 12, the N- drift region 2 and the N+ substrate 3 and operate in the same manner.
Similar to the devices 100 and 200, the device 300 can operate as a switch having an ON state and an OFF state when the potential at the second electrode 20 is higher than the potential at the first electrode 10. For simplicity, this is described below by reference to the first cell of the device 300 only.
During the ON state of the device 300, the switch 12 is turned on and off at a high frequency. When the switch 12 is switched off, no current can flow between the electrodes 10 and 20 via the path P1. In the meantime, a current pulse lG is supplied to the gate terminal 40 to activate the second conduction path P2. Therefore current flows through the path P2 only, injecting minority carriers (i.e., holes for the device 300) from the P+ region 5 into the N- drift region 2. When the switch 12 is turned on, the first conduction path P1 is accordingly turned on. The conductivity of the first conduction path P1 is temporarily enhanced by the injected minority carriers. In the meantime, the second conduction path P2 is automatically switched off or enters a very low conductivity mode (depending upon the absence/presence of the current pulse lG as described above) once the current flowing through the path P2 drops below the holding current of the bipolar conducting structure. In this way, the average on-state voltage of the device 300 is reduced to a level lower than the knee voltage of the bipolar conducting structure. It will be appreciated that the conductivity modulation received by the part of the N- drift region 2 along the path P1 is due to the conduction of the second conduction path in each of the first cell and the second cell which surrounds the path P1.
During the OFF state of the device 300, the path P1 is switched off by turning off the switch 12 as described above. Similar to the devices 100, 200, the path P2 is kept off by not supplying any current to the gate terminal 40, thereby not triggering the path P2. Accordingly, current cannot flow from the second electrode 20 to the first electrode 10. Similar to the device 100, switching between the ON state and the OFF state of the device 300 must happen within an on-phase of the path P1.
When the device 300 switches from the ON state to the OFF state, the current flowing through the device 300 during the ON state is interrupted, and accordingly the voltage difference between the second electrode 20 and the first electrode 10 increases over time before reaching its maximum level. This causes the voltage drop across the switch 12 (which is turned off) to rise at the beginning of the OFF state. In the meantime, with the increasing of the voltage difference between the electrodes 20, 10, depletion regions within the N- drift region 2 resulting from reverse-biased PN junctions between each of the P+ wells 4-i and the N- drift region 2 will spread out. When depletion regions associated with adjacent P+ wells 4-i touch each other across the spacing L of adjacent P+ wells 4-i, the depletion regions collectively pinch off the first conduction path P1 of each cell. Once the path P1 is pinched off, the increasing voltage difference between the electrodes 20, 10 will be supported by the depletion regions within the Ndrift region 2 and the voltage drop across the switch will not rise substantially. As described above, the switch is a low voltage switch and cannot withstand high voltage. By designing the spacing L such that the depletion regions associated with adjacent P+ wells 4-i spread enough to cut off the path P1 before the switch 12 breaks down, the switch 12 is protected by the depletion regions from breakdown during the OFF state of the device 300. It will be appreciated that this switch protection mechanism is also applicable to the device 200, and a device 400 described below.
Fig. 5 schematically illustrates a cross-section of a power semiconductor device 400 according to a fourth embodiment of the present disclosure.
Similar to the device 300, the device 400 does not have a gate-driven MOS structure. However, the device 400 differs from the device 300 in that the N+ region 1 is disposed within the P+ well 4, and the N+ region 1 has a boundary substantially aligned with the boundary of the P+ well 4 such that the N+ region 1 is in direct contact with the N- drift region 2. It will be appreciated that the boundary N+ region 1 may slightly protrude over the boundary of the P+ well 4, and the device 400 is functional as long as the N+ region 1 is in direct electrical connection with the N+ substrate 3 via the N- drift region
2. There is no P-type channel region (similar to the channel region 15 of Fig.3) formed between the N+ region 1 and the N- drift region 2. Because the only charge carriers involved in the electrical connection are the majority carriers (i.e., electrons) of the regions 1 to 3, the N+ region 1, the N- drift region 2, and the N+ substrate 3 form a unipolar conducting structure which provides a first conduction path P1.
Similar to the device 200, the N+ region 6, the P+ well 4, the N- drift region 2 and the P+ region 5 collectively form a thyristor-like bipolar conducting structure, which is operable to provide a second conduction path P2 between the first electrode 10 and the second electrode 20. The second conduction path P2 extends sequentially from the P+ region 5, the N- drift region 2, the P+ well 4 to the N+ region 6.
The operation of the device 400 is very similar to the operation of the device 300 as described above. In particular, the switch 12 is turned on and off at a high frequency during the ON state of the device 300. By further providing a current pulse (similar to lG shown in Fig. 2) to the gate terminal 40, current flowing from the electrode 20 to the electrode 10 alternates between the path P1 and the path P2 during the ON state of the device 300, and the conductivity of the N- drift region 2 during the conduction of the path P1 is enhanced by minority carriers injected from the P+ region 5 into the N- drift region 2 during the conduction of the path P2.
Similar to the devices 200, 300, the device 400 has an OFF state, during which the path P1 is switched off by turning off the switch 12 and the path P2 is kept off by not supplying any current to the gate terminal 40, thereby not triggering the path P2.
The devices 300 and 400 have the advantage of not requiring a gate-driven MOS structure or a gate electrode, so the devices 300, 400 are simple and cheap to manufacture.
Each of the devices 100 to 400, when used as a power switch, can achieve an on-state voltage lower than that of existing options, and can provide benefits in many applications such as motor control and switch mode power supply (SMPS). In addition to the efficiency gains through lower on-state voltage, using each of the devices 100 to 400 as a switch in the above applications also provides the benefit of lower power dissipation, allowing reduction or even elimination of bulky and expensive heatsinking. The total gains provided by the devices 100 to 400 to the user and to the environment are therefore enormous.
It will be appreciated that although a planar MOSFET structure having a horizontal channel is used as the unipolar conducting structure in the devices 100, 200, other device structures such as TrenchMOS (U-MOS) can also be used. Indeed, it will be appreciated that there are numerous other equivalent device structures that can be used as the unipolar conducting structure, all of which are within the scope of the present disclosure.
It will further be appreciated that although a thyristor-like structure is used as the bipolar conducting structure in the devices, other structures such as BJTs can also be used.
It will be appreciated that although each of the devices 100 to 400 may be used as a power switch which conducts current in one direction only, two of the devices 100 to 400, which may be the same or different from each other, can be integrated together to make a bi-directional switch which conducts current on both directions.
Further, the unipolar conducting structure within the devices 100-400 uses electrons to conduct current. It will be appreciated that the unipolar conducting structure may alternatively use holes to conduct current. However, the mobility of holes is lower than that of electrons, and the resistivity of the first conduction path provided by the holebased unipolar conducting structure may be higher than that provided by the electronbased unipolar conducting structure.
It will be appreciated that all doping polarities mentioned above could be reversed, the resulting devices still being in accordance with the present disclosure. In the present disclosure, generally the n-type doping polarity is referred as the first conductivity type and the p-type doping polarity is referred as the second conductivity type. However, the skilled person would be able to reverse them to form an appropriate device. The disclosure covers all the devices formed from the reverse doping polarities as well. Further, it will be appreciated that the terminals and the associated contact regions of the devices could be arranged to be out-of-plane or to be differently aligned so that the direction of the carriers is not exactly as described above, the resulting devices still being in accordance with the present disclosure.
The skilled person will understand that in the preceding description and appended claims, positional terms such as ‘top’, ‘bottom’, ‘above’, ‘overlap’, ‘under’, ‘lateral’, ‘vertical’, etc. are made with reference to conceptual illustrations of a semiconductor device, such as those showing standard cross-sectional perspectives and those shown in the appended drawings. These terms are used for ease of reference but are not intended to be of limiting nature. These terms are therefore to be understood as referring to a transistor when in an orientation as shown in the accompanying drawings.
Although the disclosure has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the disclosure, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.

Claims (21)

1. A power semiconductor device, comprising:
a semiconductor substrate comprising:
a unipolar conducting structure comprising a first region of a first conductive type, a second region of the first conductive type, and a third region of the first conductive type, wherein the second region has a lower doping concentration than the first region and the third region; and a bipolar conducting structure comprising a fourth region of a second conductive type opposite to the first conductive type, the second region, a fifth region of the second conductive type;
a first terminal operatively coupled to the first region; and a second terminal operatively coupled to the third region and the fifth region;
wherein the unipolar conducting structure is operable to provide a first conduction path between the first terminal and the second terminal using at least the first, second and third regions;
wherein the bipolar conducting structure is operable to provide a second conduction path between the first terminal and the second terminal using at least the fourth region, the second region and the fifth region;
wherein the first conduction path is configured to be switched on and off at a first frequency under application of a control signal during an ON state of the power semiconductor device, and the second conduction path is configured to operate in a high conductivity mode during an off-phase of the first conduction path and to operate in a low conductivity mode during an on-phase of the first conduction path.
2. A power semiconductor device according to claim 1, wherein the second region is configured to receive conductivity modulation due to at least minority carriers injected from the fifth region into the second region when the second conduction path operates in a high conductivity mode.
3. A power semiconductor device according to claim 1 or 2, wherein the first conduction path is substantially in parallel to the second conduction path.
4. A power semiconductor device according to any preceding claim, wherein the power semiconductor device is operable to have an ON state during which an electric current flows between the first and second terminals using at least one of the first and second conduction paths, and an OFF state during which an electric current does not flow between the first and second terminals.
5. A power semiconductor device according to any preceding claim, wherein the power semiconductor device is a power switch.
6. A power semiconductor device according to any preceding claim, wherein:
the bipolar conducting structure comprises a gate terminal operatively coupled to the fourth region;
the gate terminal is operable to receive a gate signal for activating a current flow through the bipolar conducting structure; and the power semiconductor device is configured to enter the ON state from an OFF state upon application of the gate signal and the control signal.
7. A power semiconductor device according to any preceding claim, wherein a time duration of the on-phase of the first conduction path is configured to be longer than a time duration of the off-phase of the first conduction path during the ON state of the power semiconductor device.
8. A power semiconductor device according to claim 2 or any one of claims 3 to 7 as dependent upon claim 2, wherein a time duration of the on-phase of the first conduction path within at least one cycle of the control signal is shorter than a time duration during which a fraction of the injected carriers disappear through recombination with majority carriers of the second region.
9. A power semiconductor device according to any preceding claim, wherein the fifth region and the third region are embedded within the substrate below the second region.
10. A power semiconductor device according to any preceding claim, wherein the unipolar conducting structure comprises a metal-oxide-semiconductor (MOS) gate structure, and wherein the MOS gate structure comprises a channel region of the second conductive type disposed between the first region and the second region, and a gate electrode for generating an electric field in the channel region to invert the conductivity type of the channel region so as to form a conducting channel between the first and second regions.
11. A power semiconductor device according to claim 10, wherein the gate electrode is configured to receive the control signal to switch on and off the conducting channel of the MOS gate structure so as to switch on and off the first conduction path.
12. A power semiconductor device according to claim 10 or 11, wherein the first region is disposed within the fourth region, and the bipolar conducting structure comprises the first region.
13. A power semiconductor device according to claim 10, further comprising a switch connectable between the first terminal and the first region, and the switch is configured to receive the control signal to switch on and off the first conduction path.
14. A power semiconductor device according to claim 13, wherein:
the first region is disposed within the fourth region;
the bipolar conducting structure comprises a sixth region of the first conductive type, and the sixth region is disposed within the fourth region and is spaced apart from the first region.
15. A power semiconductor device according to any one of claims 1 to 9, wherein the first region is in direct contact with the second region, and the power semiconductor device further comprises a switch connectable between the first terminal and the first region, and the switch is configured to receive the control signal to switch on and off the first conduction path.
16. A power semiconductor device according to claim 15, wherein the bipolar conducting structure comprises a sixth region of the first conductive type, and the sixth region is disposed within the fourth region.
17. A power semiconductor device according to claim 16, wherein:
the bipolar conducting structure comprises a plurality of conducting cell connected in parallel between the first and second terminals, the sixth region includes a plurality of sixth sub-regions spaced apart from one another, the fourth region includes a plurality of fourth sub-regions spaced apart from one another, at least one of the sixth sub-regions is disposed within one of the fourth subregions, forming one of the conducting cells with the second region and the fifth region; and at least one of the sixth sub-regions is operatively connected to the first terminal.
18. A power semiconductor device according to claim 16 or 17, wherein:
the fifth region includes a plurality of fifth sub-regions spaced apart from one another; and at least one of the fifth sub-regions is disposed below one of the fourth subregions.
19. A power semiconductor device according to claim 17 or 18, wherein the first region comprises at least one first sub-region spaced apart from one another, and the at least one first sub-region is disposed between adjacent ones of the fourth subregions.
20. A power semiconductor device according to claim 17 or 18, wherein the first region comprises at least one first sub-region spaced apart from one another, and wherein the at least one first sub-region is disposed within one of the fourth subregions and has a boundary substantially aligned with a boundary of the one of the fourth sub-region such that the at least one first sub-region is in direct contact with the second region.
21. A method of operating a power semiconductor device, the power semiconductor device comprising:
a semiconductor substrate comprising:
a unipolar conducting structure comprising a first region of a first conductive type, a second region of the first conductive type, and a third region of the first conductive type, wherein the second region has a lower doping concentration than the first region and the third region; and a bipolar conducting structure comprising a fourth region of a second conductive type opposite to the first conductive type, the second region, a fifth region of the second conductive type;
a first terminal operatively coupled to the first region; and
5 a second terminal operatively coupled to the third region and the fifth region;
the method comprising:
providing a first conduction path between the first terminal and the second terminal using the first, second and third regions;
10 applying a control signal to switch on and off the first conduction path at a first frequency during the ON state of the power semiconductor device;
providing a second conduction path between the first terminal and the second terminal using the fourth region, the second region and the fifth region; and controlling the second conduction path to operate in a high conductivity mode 15 during an off-phase of the first conduction path, wherein the second conduction path operates in a low conductivity mode during an on-phase of the first conduction path.
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EP4187615A1 (en) * 2021-11-30 2023-05-31 Pakal Technologies, Inc. Npnp layered mos-gated trench device having lowered operating voltage

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