GB2546475A - Ultra lateral extra 3 - Google Patents
Ultra lateral extra 3 Download PDFInfo
- Publication number
- GB2546475A GB2546475A GB1522208.6A GB201522208A GB2546475A GB 2546475 A GB2546475 A GB 2546475A GB 201522208 A GB201522208 A GB 201522208A GB 2546475 A GB2546475 A GB 2546475A
- Authority
- GB
- United Kingdom
- Prior art keywords
- silicon
- doping
- voltage
- power
- transistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
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Abstract
A method of manufacturing a lateral power transistor comprising a silicon planar substrate, the method comprising sequential formation of arrays of vias (i.e. through holes) in the silicon substrate; the side surfaces of the vias are doped with either N or P type diffusion of ions; the vias are then filled with a conducting material; and a diffusing region is formed between adjacent transistors. There is further discussion of a lateral high voltage power transistor construction using doped through hole arrays of N and P type on the X,Y plane of a silicon slice creating a volumetric (3D) utilisation silicon not restricted in volume by the usual limitation of Z dimension of conventional lateral and vertical power devices related to diffusion depth and breakdown voltage respectively.
Description
Ultra-Lateral Power Transistor and Driver structures Background:
Existing co-pending patent application PCT/GB2014/050368 application is included here complete by reference [1]
Existing co-pending US application US CIP application number is 14/797498 is included here complete by reference [2]
High voltage, high power, transistors generally use vertical conduction paths and special “Thin wafef ’ processing to improve the specific on-resistance of the switch.
Lateral power devices, of which many structures are well known, are generally considered to have inferior specific on-resistance because of the reduced conductive volume available to the lateral path which is ordinarily confined close to the wafer surface.
The ideas expounded here feature a new structure with lateral conduction paths of much higher conductive volume than even a typical vertical device and have advantages in that any unidirectional or bidirectional devices thus formed do not need double-sided processing or double-sided base connections. A further advantage comes from the fact that these new devices are fabricated on ordinary full-thickness silicon wafer processing equipment - no “Thin wafer” handling is needed.
Construction:
What follows is a general non-limiting explanation of the concepts and initial designs which have not yet been subject to optimisation techniques. NPN type power structures will be described but certainly PNP structures are also possible by reversing the doping systems. Where reference is made to diffusion, ion implantation is also an option and so on. Silicon is mentioned as the most obvious semiconductor to use but Silicon-Carbide amongst others is also practical.
Fig 101 has the top-view of a Single-Sided-Double-Base-Device (SSDBD) transistor created in accordance to the invention. The voltage-sustaining, current-conducting, drift regions of high resistivity P-type wafer arise from the creation of concentric rings of doped silicon which extend through or at least partly through the thickness of the wafer.
Other shapes not just concentric rings such as meanders, spirals etc are all possible of course.
Multiple interconnected rings, or strips (Fig. 101c) increase the parallel current capacity of the complete switch when connected together. Masking with thermal Si02 grown inside the vertical holes and selective removal permits multiple independent doping operations on different groups of the vertical electrode. Another option is to use a Liquid doping (similar to spin-on-dopant) with pre-masking for multiple dopings, relying on capilary action for the dopant to run into the micro/nano holes with subsequent single furnace step to simultaneously perform all the different drive-ins.
Figl02 shows the vertical cross-section structure of the same SSDBD example of the invention. Concentric pairs of N+ rings of material which extend part-way or entirely through the wafer thickness are alternately labelled CE1, CE2. Inserted inside these CE regions are P+ regions which extend part-way or entirely through the wafer thickness forming BASE1, BASE2.
There exists a conductivity-modulated path from CE1 through the drift region to CE2 controlled by BASE1 and BASE2. The device is structurally different but functionally equivalent to the previously mentioned co-pending patent application's [1] Figl A and can be controlled in the same way - optimally using the “high-side” BASE (or C-BASE) to turn the device on and emitter-switched turn off. A key fabrication step for the Ultra-lateral device are the production of small diameter [or small cross section for non-round] holes with large depth and high aspect ratio as can be produced using known DRJE etching (e.g. Bosch process), laser drilling and also other techniques known to the practitioners of TVS (Through-Silicon-Via) method amongst others. Note that although circular holes are shown, any shape can be produced using DRIE etching and the shape can be optimised to position the dopants where required for optimum performance (see inset of FIGlOla). Plain, updoped holes can change the flow of currents and electric fields around the BASE region.
Atypical Bosch process DRIE etch machine such as Oxford Instruments PlasmaPro 100 Estrelas Deep Silicon Etch System can attain etch rates upto 25u/min and upto 70:1 aspect ratio.
The DRIE holes can act as diffusion surfaces whereby for example a Phosphorus or Boron dopant can be diffused (or implanted) from the holes outwards into the lateral direction of the silicon using perhaps low temperature plasma imersion implant or furnace dopant processing. An alternative method of doping is to use selective epitaxy to create a doped silicon lining e.g. using Applied Materials Centura Epi reactor. Subsequenct furnace drive-in can be used to diffuse the dopants if desired. A lateral device must still have the equivalent of high voltage 'edge termination' of the drift region to support the applied voltage without premature breakdown and one solution shown in Fig 102 involves structuring the surface of both sides with a field-shaping groove which is effectively a lateral version of the technique shown previously in the aforementioned co-pending applications' [1] Fig20 for vertical devices. A known method is to use KOH alkali isotropic etch to form the V. Asymmetrical devices could benefit from a single ramp shape profile rather than the V-shape needed for bidirectional blocking voltage sustaining. Other options are SIPOS scoating to impose a voltage gradient along the outside of the drift region or finally good results have been achieved using A1203 ALD coatings to terminate the edges of P-type wafers used for high voltage photodectors [3] and could work for the wafer surfaces here. For N-type wafers, thermal Si02 or SiN should suffice.
Figl03 shows a Single-Sided-Single-Base-Device (SSSBD) device using optional asymmetric dopings to support for example Punchthrough (and is also applicable to the SSDBD) which is now in the lateral direction. Doping the holes of alternate rings with a deep P type diffusion can create a Field-Stop.
Shallow CE doping can create a “transparent emitter” to create an 12 type (IGBT-replacement transistor) which exhibits rapid turn-off (low Eoff). JFET or BJT type BASE are created according to the doping of the N+ and P+ region profiles and whether or not the N+ doping manages to pinch-off the P region or whether the N doping envelops the extra P doping - this can also be applied to the SSDBD.
An alternative minority lifetime control is possible by using for example Gold or Platinum doping in a seperate step or combined with the CE,B ASE doping phases to produce regions with decreased minority carrier lifetime.
To make low resistance contacts, the holes (or pores) will generally be filled or just plated with metal,polysilicon or similar facilitating contacts on the wafer surface where wiring (possibly multi-level planar metal wiring) connections will be made to parallel multiple rings for higher current ratings and to connect to the outside world. TSV (through-silicon-via) techniques can be used. Atomic Layer Deposition (ALD) is another option for coating the holes with perhaps Tungsten before possible electroplating.
Connections to the top, bottom or both surfaces are possible depending on whether or not the holes pass completely through the wafer. It is not necessary to connect to the bottom electrodes - leaving the option of keeping the bottom surface clear for heat transfer mounting.
For the CE terminals, first a polysilicon liner then a conductor fill would result in the well known Polysilicon-Emitter concept to give higher Beta to the device. TSV type nano hole arrays or porus silicon could be plated using an ALD process combined for rapid bulk quantity deposition for vertical vias eg. WF6 (Tungsten HexaFlouride) /B2H6 (DiBorane) ALD chemisty or WF6/SiH4 or WF6/Si2H6 disilane chemistry.
Faster opions are possible with combination ALD and CVD such as ALTUS® PNL™ (Pulsed Nucleation Layer) Tungsten system.
Kelvin connections are possible using top and bottom if desired e g. Bottom would be CE1 CE2 power terminals, Top would be CE1/BASE1 CE2/BASE2 signal lines and free of high current.
Figl04 Shows a co-packaged driver IC and for the SSDBD (single sided double base device) the driver possibly formed on SOI substrate to allow the CE1+BASE1 and CE2+BASE2 circuity to co-exist on the same silicon where otherwise the high voltage potential difference between these two ends of the power path would cause problems for a bulk silicon driver circuit - The capaciors shown indicate an isolated (high common-mode reject) signalling link between the two domains. The driver chip is shown flipped and bump-attached to the power transistor die.
Figl05 Features junction isolation doped strips to fully isolate multiple independent transistors which can now be located in the same silicon without interference or leakage through the substrate as is a common concern for power integrated circuits. Driver circuity including CMOS circuits can also be fabricated in the voltage islands created by what are effectively unbroken vertical doped walls. By these method, half-bridge, full-bridge switching arrangement or indeed any smart-power high voltage integrated circuit applications can be realised on a single die. By using power switches in series very high voltage composite switches can be fabricated on a single die which will still retain the high switching speed of the low voltage elements from which it is made.
Multiple voltage devices on the same die can be created by use of different ring pitch (drift region width) something not possible for vertical devices. Series connected lower voltage devices also eliminate the problem of ultra-lightly doped silicon being needed for 3kV and above.
Again, capaciors shown indicate an isolated (high common-mode reject) signalling link between two domains for overall control and feedback signalling.
Dual-Lifetime Transistor: Fig.106. and Figl03d,e andFigll2a
One unique feature of the concentric-ring transistor construction is that each ring is a fully contained transistor which in principle could have different doping systems within and at the ends of the drift region compared to its neighbours by using selective masking/doping. This scheme could be applied advantageously to make some fraction of the rings operate at high effective lifetime (Slow turn-off but Low On-resistance) and another possibly smaller fraction of the rings operate at low effective lifetime (Faster turn-off but Higher On-resistance) to make a Dual-lifetime transistor. This is done by modifying the lifetime-control doping mentioned previously between transistor rings. Such a composite device would have high-lifetime-B ASE electrode and a low-lifetime-BASE electrode controlling transistors which are still connected in parallel with each other on the power switching path. With a suitable driver circuit it is possible to achieve simultaneously very good conduction loss and switching loss performance as measured by the well known Ron, Eon, Eoff metrics.
For turn-on, the high-lifetime transistor would be used - routing all the base current into those high-lifetime rings. High lifetime gives high-Beta and therefore a lower Ron for a given base drive. Prior to complete turn off, a suitable driver chip (possibly on-die) can re-route this base current ino the low-lifetime transistor rings. This allows extra time for the space charge to drain away from the high-lifetime rings but the low-lifetime transistor keeps the full current flowing - albeit at a temporarilty higher Ron loss. Ultimately when the low-lifetime path is switched off there will be no tail current from the high-lifetime transistor rings which are clear of charge and Eoff will be that of the speed-optimised low-lifetime devices.
An advanced driver chip can hide the 2-stage turn-off scheme as shown by delaying the initial turn-on by the known turn-off time and thus maintain an output PWM ratio identical to the input PWM ratio [albeit with some small latency - generally not an issue in practice]. See Figl 12a
Figl06a Is one embodiment allowing a driver IC to select different BASE outputs on demand to implement the 2-step 2-lifetime scheme.
Figl06b Shows the expected turn on / off waveforms for the composite transistors.
Fig. 107, Example process :
As a low cost alternative to DRIE plasma etch equipment a wet-etch method called Metal-Assisted-Chemical-Etch (known as MACE or MacEtch) [4] is able to fabricate high aspect ratio structures on silicon. Holes of even sub-micron size can be etched right through a silicon wafer by forming a pattern of noble metal (Au,Ag,Pt, or Rh) on the silicon surface then placing into a tank of H202 + HF + H2O. Either a masked pattern or placement of gold nano/microspheres would form the pattern and the latter would tunnel into the silicon to form the holes.
For economy, throughput can be high by processing many wafers in parallel in one or multiple etching tanks.
The figure shows a technique where even though all of the deep holes are formed at the same time, they can be individually doped with the required polarity using an oxide masking technique followed by furnace or plasma doping. The well know spin-on photoresist, expose, develop, HF etch cycles are not shown and occur between stages. Full control of dopant position and strength is gained by using as many repetitions of this process as needed. Polysilicon emitters can be formed during this process for highest possible Beta. Retrograde doping profiles and hetrojuntion emitters are possible by changing the materials deposited. Discretely identifiable holes are shown but there is no reason that nano-hole making effectively a porus silicon in the desired areas would not work just as well.
An interesting further possibility is to use smaller, possibly nano-sized holes to dope the drift region with profiles impossible to achieve ordinarily. On the figure are shown nano holes which have a dot-density used to modulate the doping. Given suffiicient thermal diffusion time the doping profiles could be smooth gradients. With a gradient of SiGe doping in the drift applied by this method electron drift could be enhanced through bandgap engineering.
Supeijunction concepts [5] where N and P type strips are doped side by side and work to deplete each other to produce a net “instrinsic” silicon effect but with much better than normal majority-carrier conduction due to their increased doping are becomes possible. This would make for much faster operation of the dual-carrier (Electron & Hole) devices since a higher minumum level of majority carrier conductivity is possible when the devices are not in their depleted state.
Typical application:
Fig. 108 depicts a schematic for the high voltage components of an active bridge rectifier manufacturable with the techniques shown here.
Different polarity of T2 switches have been used; the top two are manufactured on an N-type wafer so that a single I-MODE driver chip can support those two integrated devices from a single VDD supply to rectifiy the +Ve excursion of the AC input.
To rectify the negative polarity, a pair of T2 devices are built on a P-type wafer. The bases can be controlled as mentioned in [2] to effect soft-start or overvoltage protection to the downstream DC equipment. This only requires 2 of the 4 active rectifiers to be controllable hence the note next to the top two switches on the figure. JFET devices of both high power and low power are easy to fabricate in the ultra-lateral concept see figl08D and are useful for bias supplies - in the role of extracting a few uA of startup through IDSS@Vgs=OV ( current is gateable 'off after boot-up digitally as shown). JFETs are also useful as high-common-mode-difference level translators for digital signals between low-side and high-side I-MODE drivers as shown. JFETs can be driven with forward-biased gates to operate as Bipolar-Mode JFETS (BMJFETs) with the same drive circuits as used for other PN junctions.
TCAD A TCAD simulation result of a nominallly 700V SSDBD is seen in Fig. 109. The hole sizes are 8u dia for the BASE and 8u x 16u slot for the CE terminals and doped accordingly.
Centrifugal method of MacEtching:
In Fig. 110 a machine construction is shown for providing centrifugal assistance to the metal-assisted-chemica-etch process. Catalyst-metal of Au,Ag,Rh,Pt,W or similar possibly isolated patterns of discrete shapes are deposited on the surface of the wafers. The wafers are placed in a typically plastic drum with closed ends together with the etchant. Low speed initial rotation will allow the shapes to 'bed in' then high speed rotation will give many 'g' of effective increase in centrifugal forces directed as pushing the catalyst through the wafers as the etching process proceeds. Currently known method of magnetic force MacEtch is weaker by comparison so is more prone to exhibit trajectory drift as the metal passes through the wafer. Centrifugal force is sufficient to warp the wafer temporarily and this would also help keep the etched holes normal to the wafer surface.
Improved MacEtch hole formation method - Fig. Ill
Usually 1:1 patterns of noble metal as per Fig. 11 la are used for etching isolated structures with the MacEtch process so gold is patterned exactly as the holes are to appear in the etched material. Problems arise because the etching process requires exchange of etchant and reactants from underneath the gold to the bulk liquid or else etching stops and/or bubbles form causing the mask to move around laterally. The usual solution is to make the gold “nano-porus” or so thin that atoms can diffuse though it. This helps but limits the etching rate and the very thin e.g. lOnm gold films are fragile and tend to break up over long duration etching.
To fix these problems a two-step approach is used. First as in Fig. 11 lb or c, a “Waffle Griddle” pattern can be used instead of a full circle to do the etching. It has ample edge length to allow diffusion to/from under the metal catalyst but acts like a cookie-cutter and will produce long tall 'nano' or 'microwires' within the desired hole as the metal descends through the silicon.
These wires will be etched away with a final 'Trilogy Etchant' typically 126parts Nitric Acid (70%), 60parts H20, 5 parts Ammonium Flouride (40%) which has a Silicon etch rate 150nm/min. 4 minutes in this solution will completely dissolve wires upto lu diameter and will attack less than lOOnm of protective oxide which would be used on the silicon surfaces. An increase of diameter of 1.2u of the holes is expected.
Improvements expected of using this MacEtch method are - prevents isolated patterns from wandering - gives more edge length to allow for chemical diffusing of etching and byproducts for faster speed - etch process is now fairly independent of the shape of hole to create.
Further switching circuits for Power Integrated circuits:
Figl 12 gives circuits and structures suitable for integrating on the ultralateral concept.
Figl 12 A is shows how a combination of B2 device and 12 device [1] makes a Half-Bridge output on a single piece of silicon yet only a single driver IC is needed. No level shifting is required and the same base current is effectively switched to whichever Base bhl, bll or bl2 is needed where bll and bl2 are different lifetime-controlled sub-transistors within the lowside switch.
Multiple half-bridges can be placed on the same silicon e.g. 2 or 3 half bridges to make a monolithic 2phase or 3phase power stage. ESBT i.e. emitter-switched bipolar mode explained in [2] is possible but not shown.
Fig 112B is the same circuit as Abut is shown working as an active half bridge rectifier. In this mode the current directions are opposite which invokes opposite conduction modes in the transistors (Common Emitter becomes Emitter-Follower and vice-versa ) to Figll2Abut otherwise the circuit sequencing operation is similar.
Alternative labeling AC 1, AC2 on Fig. 112 B is for using the configuration as a fast AC switch which connects between AC1 and AC2 nodes when activated. The base current would be multiplexed at high speed between the two inverse-series connected transistors to turn them both on individually or at the same time. Many options are possible for the choice of series device for a 1200V AC switch e.g. two 12 devices of 1200V rating each using punchthrough (each only supports unidirectional blocking) or two 600V rated T2 switches where each can support +/-600V for 1200V total rating.
High switching speed of the former is assured when lifetime or transparent emitter control is used and conduction loss is still good for a dual device because two 1200V punchthrough devices have the same combined drift region thickness as a single 1200V non-punchthrough AC device but a super-proportional benefit of Beta and Ron due to the half-thickness of the each active switch.
Figl 12 D is a transformer coupled driver which affords the possibility of recovering base charge energy since the paths through the transformers are fully bidirectional. The drive circuit has limited ability to move far from 50:50 duty cycle as is typical for simple transformer systems. Circuit shown with a double base device from Figl of [1]
Fig. 112 E helps in this regard with transformers operating at multiples of the power switching frequency to deliver a bipolar drive voltage able to turn on and off the bipolar junctions at will for arbitrary PWM ratio.
Figl13 - These are I-MODE [2] driver circuit configurations which can be used with the ultralateral switches of different unipolar and bidirectional switching.
Figl14 - Different transistor types are useful for multiplexing different voltage sources to make stepwise arbitrary power waveforms suitable for controlling a load. The top and bottom transistor are unidirectional while the middle taps need bidirectional switches.
Fast Single-Sided-Single-Base-AC-Switch SSSBAC - also known as “T3” type:
Making a fast switching, single-base, AC switch is possible without needing lifetime control or transparent electrodes using the scheme of Figl 15. This can be seen as simplification of Fig.ll2B but here, instead of two separate transistors each with terminated N+ structures at the ends of the drift region, the two transistors share a common base connection and have a drift regions which permit diffusions of electrons back and forwards. In effect it has a centre-tapped drift region. Operation is similar to FiglC of [1], The SSSBAC has the ability to pull charge from the base for rapid turn off and means that base drive can be adiabatic [charge recovering],
Figll5Ais a 3D view of section through a ring structure. Electrons can be injected through a forward-biased PN junction of BASE / EBASE which will turn on both transistors since there is not a continuous N+ region to in the middle of the drift region which would block electrons. P-medium doping around all the holes made in the middle gives a field-stop effect to support punchthrough blocking mode of whichever transistor half is reversed biased [this approximately halves the needed drift thickness versun non-punchthrough]. Due to the PN junctions at the ends of the drift region, the BASE driver circuitry will generally be self-biased at 1 diode drop above the most negative of CE1 or CE2. For this reason it helps to use a floating base driver using transformer coupling. The I-MODE self-bootstrap driver concept of [2] can be used through transformer coupling and very high (multiples e.g. lOx or lOOx of power switching frequency) base current generation circuitry. In Fig. 115D, the AC current path is interrupted with a capacitor which provides a low impedence source to extract a fraction of the load current through the PWM action of SWA after first being rectified by the polarity swapper circuit (intelligently controlled by the detected polarity - not shown). TR1 is a typically 1:1 turns ratio coupled-inductor (i.e. transformer) which only needs to be in the nanohenry range of primary inductance. The normal function of the missing SWB is taken with D1 which is a Schottky barrier rectifier to capture the flyback energy as a voltage driving a current into the SSSBAC transistor. Waveforms similar to those shown in Fig. 112E can be expected and D2/D3 prevents any losses during the SWA on-time. Fully proportional base current control is set as a forced-Beta given by the SWA pwm ratio. This circuit can also be used to drive any other BJT or 12, or other transistor type in a fully floating configuration with the main downside being the extra loss of the Schottky voltage drop which itself could be overcome with active rectification on the secondary side of the coupled inductor. Both D1 and D2 could be fabricated on power transistor die meaning that only a passive external coupled-inductor is needed to control the power devices in a totally isolated manner.
For fast turn turn-off of the power transistor, PFET1 in combination with SWA can be turned on briefly then periodically whereby D2 will set a negative bias on the BASE of the transistor. Reverse voltages of around 5 V are sufficient. nOFF going low is used to turn on PFET1. A Ping circuit to monitor a remote switch or other isolated input can be realised by adding one more winding to TR1. This is a useful control input from either a mechanical switch or electrical output of e.g. a PLC controller. The state of the switch on the isolated side can be determined on the primary side be the extent of the primary voltage swing.
Example Process Flow to build the basic transistors: THROUGH-SILICON HOLES MASK#1 - Pattern gold for making through-silicon holes using Soft UV Nano Imprinting - Etch all through-silicon holes at the same time in wet etchant
DOPING
All hole dopings - Any doping which should be applied to all the holes goes here. E.g. Field-stop P- region could be applied to all holes presumably CE1 and CE2 formation - Grow oxide everywhere - Remove oxide for the N+ holes MASK#2 - Phosphorus dope
BASE - Grow oxide again - Remove oxide for the P+ holes MASK#3 - Boron Dope
PASSIVATION - Passivate the top and bottom surface which represents the edge of the drift region ALD of A1203 e.g. with spacial ALD machines http://www.solaytec.com/ - Pattern passivation MASK#4 DIELECTRIC - Both sides - Cover with dielectric - Both sides - Spin on SU-8 - Will cover the passivation above e g. 2u thick - Pattern so openings exist where the through-silicon holes are MASK#5 (front), MASK#6(back) - Second SU-8 - Pattern for trenches SU8 MASK#7 (front), MASK#8(back) these will link up to the openings of previous mask so can get down to the contacts METALISTION [similar to a TSV process]
Level 1 and TSV - just plate into the trenches - TiN ALD (Spacial ALD) conformal deposition 50nm thick, 25ohm[] resistance - coats inside of the through-silicon holes and top and bottom wafer surface and is a diffusion barrier for Copper into silicon. - Copper Electoless and/or Electroplating - plates the through-silicon holes and thickens up the TiN patterns to form the first level copper interconnect in the trenches
Anneal copper for 350oC lhr in N2 atmosphere (no higher because SU8 is affected)
Flip device so it can be SMD soldered [2 layer metal will be on the bottom] and top surface can be prepared for clip on heatsinking
Adiabatic operations of minority carrier transistors:
The transistors described previously are all either minority carrier devices or majority carrier devices with conductivity modulation caused by minority carrier injection. This phenomenon dramatically reduces the conductivity losses of the switches but comes at a price of “saturation” and “desaturation” time. These refer to the processes of charging and then extracting charge from the forward biased PN junctions of the transistor respectively. Often this puts minority carrier based devices at a competitive disadvantage to unipolar devices such as Mosfets which do not have this issue and can switch faster in “Hard-Switching” applications.
To combat this effect, a technique called adiabatic switching is described in the following sections and the specific measures needed to apply it to minority carrier devices where it can reduce switching losses to below those achievable even with Silicon Carbide or Gallium Nitride. When operating adiabatically, all charging and discharging is done in a non dissipative way using magnetic energy stored in inductive components to exchange energy with the charge storage nodes.
Figl 16A gives a building block for building an adiabatic system using a transformer coupled set of switches to form a bridge aka synchronous mod/demodulator. As mentioned for figl 12 D and E there exists a bidirectional i.e. reversible energy path between the switch capacitances and the magnetic components.
Figl 17 shows multiple of the previous transformers/bridges operated in phase-offset interleaving and how this can maintain a continuous power path between both sides of a power converter yet still allow time for the adiabatic voltage reversals needed - which are hidden in the sequence.
Operation in adiabatic mode occurs as shown in a simplified transformer +/- drive polarity circuit of
Figl 18. By controlling the switching times it is possible to exploit the largely trapezoid ramp of voltage caused by magnetisation current to charge all the different capaciances. There exists an optimum point of operation shown in Figl 19 where the transistors switch on perfectly in time with the inductive-current induced ramp. A unique identifying feature of a properly adiabatic system is that virtually all of the observable power voltage swings in the system occur when the transistors are OFF. Ideally, transistors switch on only to remagnetise the inductive components where energy is being stored for the next voltage transition.
The switching environment for the transistors is entirely benign. There is no risk of second breakdown in the transistors, no chance of dynamic breakdown or snapback effects. The usual figures of Eon and Eoff energy loss do not apply. The transistors are always switched on and off with zero voltage across them.
The output capacitance of power transistors, the transformer stray capacitances any any other charge store attached form one effective 'C' capacitance value. Since the switching losses and C VA2 F losses are largely eliminated the transistors can be scaled up in size to reduce conduction losses to the lowest practical level.
The above has shown adiabatic operation of the power transformers but the exact same technique can be applied to the base drive transformer of Fig. 116 where all of the base charge (and some of the drift charge) of driving the power bridge transistors is recoverable, is stored in the magnetising current of suitably chosen transformer design and recirculated to discharge the base (and some of the drift charge) charge. Very high levels of circulating current can be used and the transistors can be switched on and off in under 500nS. Very efficient operation upto 200KHz is possible for a 1000V transistor system. Higher speeds for lower voltage systems.
One drawback of adiabatic operation is the fairly fixed operating frequency and the limited ability to modulate the output voltage by the usual variable PWM method. Instead to produce a variable output voltage (effectively a programmable transformer turns ration) a dynamic tap selection (coarse) with a fine tune PWM “blend” is implemented as shown in Fig. 120 and Figl21. Such circuits or multiples thereof can perform all the usual tasks such as AC sinewave generation as per 3 phase motor Inverter or in reverse can perform AC —» DC conversion with unity power factor if needed.
Figl20A gives an application of a 400V using a stack of 66V rated power bridges but the concept is applicable for higher voltages e.g. using 1000V transistor bridges would support 6000V operation. The stack is a series string on the DC bridge but note that the transformer windings are not in series but each is driven by its own bridge and each shares a common magnetic core. On the other side of the isolation barrier is a similar stack of bridges and now multiple voltages are available by tapping at the different positions in the stack.
Non-Isolated Autotransformer version Fig. 120B
It can be advantagous to produce a non-isolated DC->AC converter since this reduces the copper losses [primary is removed, freeing winding area on the core for the inductor string], promotes an 'Autotransformer' mode of power transfer and can simplify the control electronics.
To convert to non-isolated mode, both the primary winding and primary drive/control electronics is dispensed with and the input DC power source is connected to the top and bottom of what was the secondary series-DC synchronous modulator tap string. No other changes are needed.
Operation is now quite different because much of the output current from the selected tap is coming directly from the DC input source. Interleaving of transformers is still beneficial to prevent discontinuities in the input and subsequent inductor voltage-bounce or capacitor voltage dips and
To generate any voltage from 0 to 400V the circuit of Figl21 can be used. Here a coarse taps of 50V resolution is selected using switches of the kind described throughout this document then fine tune is performed using PWM interpolation (blending) between tap voltages. In this example low voltage mosfets are suggested from the fine tune PWM.
Note that the previous adiabatic circuits work for AC <-> AC power conversion where the switches are AC types. Also the DC circuits operate as bidirectional power converters useful for vehicle application for motor drive and regenerative braking.
Commincation and power linkage using coupled inductors: see Fig 122
In many of the applications beyond simple on/off control of these transistors there is the need to coordinate activity of one or a number of transistors with one or more controller devices which entails communicating digital data to/from transistors which may be riding on very high and fast slewing common-mode voltages. A mechanism and communications protocol is shown which can achieve this using only a single coupled-inductor shared with the I-MODE boost inductor function which is explained in [2], The normal I-MODE self-bootstrap, forced-beta base drive concept is previously described as being divided into a two portions of inductor operation CHARGE and DISCHARGE. In the CHARGE portion with SWA=On magnetic flux builds up in the inductor in response to an imposed voltage whereas during DISCHARGEportion with SWB=On where normally the current is redirected into the BASE of a power transistor. Where isolated secondary windings are present on the core the DISCHARGE could also be seen as a 'Flyback' event.
Fig. 115 D showed a simplistic floating AC transistor switch with an isolated On/Off control interface all linked together wth a common magnetic circuit (core) suitable for perhaps Solid-State-Relay application
This concept of coupled inductors can be extended to a fully function isolated digital data and power network to support high frequency half-bridge or full bridge switching with control and measurement data. The extra features are shown in Fig. 122
For the example of a full bridge, quad power transistor setup.There a s 5 seperate control ICs each electrically isolated from each other. One device is a typically a master controller in DomainO and will either implement the overall control algorithm of the module or interface to controller that does. Simply by using turns on a common air or other magnetic circuit to make the coupled inductors each of the ICs is simultaneously in power and communication with the others. A data communications protocol built on top of the power transfer mechanism. A round-robin or bit-addressable protocol sequences the particular transistor as the target for communication. The addressed transistor can route the flyback energy from the core to the BASE of its controlled power transistor. If the flyback energy is not directed to any transistor the voltage can shoot high as was documented for the I-MODE driver. Here each device in each domain uses either active of passive rectification on each isolated domain of the system is able to charge up a local VDD from this event and thus all the isolated CMOS I-MODE die can run their logic and analog contol functions. This event can also be used a synchronising event ones per packet whereby all the attached devices synchronise their state machines.
DomainO is the Interface-Domain it interfaces with an external device to control the power transistors and provides a conventional digital data interface e.g. SPI for status, setup and measurements. It too generates a VDD via the coupled-inductors so any CMOS control IC connected in this domain will be powered.
Domainl and Domain3 are Power-Sequencing domains. ICs in this type of domain are responsible for high-current (through current) control of one or more transistors in the main power path (SWA) and will extract the base drive current using the I-MODE boost system and can (SWB) directly drive (without intervening winding) one or more BASE of one or more transistors. In quiescent mode when no power transistors are turned on there would be a microampre leakage (parasitic or JFET current-source for example) which would allow occasional [perhaps several Khz] 'pings' of the local winding using SWA and the VCAP leakge-developed voltage and flyback (vboost time) will be rectified by ICs in all other domains to furnish them with micropower level VDD supplies to operate the CMOS.
Domains 2, and 4 are Slave-domains and do not posses the SWA switch instead relying on power from the coupled inductor to feed to the BASE of the controlled transistor using active rectification of the flyback energy. These slave ICs can be physically much smaller and lower cost than Power-sequencing ICs since they lack the very large SWA mosfet and only have to carry base current which is some fraction (forced beta) less than the collector current.
Two distinct data communication protocols are present. The first is in the Pre-Active mode signalling regime when the power stage is not active and the second is active-mode data communication regime. The biggest difference between the protocols is whether the power transistors are switched on or not.
Pre-Active Signalling Protocol:
DomainO, the Interface-domain is able to issue signals to all domains simultaneously by pulsing its winding to VDD for a short time using PFET1. This signal is received in all other domains . The length of this pulse determines the event. This event may clash with the quiescent power generation of the Power-sequencing domains mentioned above so in quiescent mode Domain 1 must use especially designed weakened drive transistors which can be forcibly overridden by the signalling domain [put them in the figure], SYNCH = Short length VDD pulse from domain 0 (longer than 'ping' pulse) signals node to enter Pre-Active data protocol and synchronises the state machines in each domain. ON command = Long length pulse to enter Active protocol and turn power transistors on.
When the SYNCH pulse is received by domains they enter into a Pre-Active mode where Power-Sequencing domain controller (Domainl) will now issue multiple rapid pings in a row the purpose of each is to transfer one bit of data from one domain to to all the other domains. A simple round-robin scheme or bit-addressable scheme could be implemented to set the currently addressed domain as the source of the databit. In Pre-Active mode, no IC will route the flyback (aka DISCHARGE) pusle onto any transistor base so flyback will rise to VDD level unless it is 'squashed' to some lower level.
The mechanism for data transfer is by “flyback pulse squashing”.
This is done by any 'addressed' domain's driver IC driving SWX [instead of routing the pulse to the transistor's base via SWB] and by doing so this can transmit a “1” bit of information (and absense of this even can be interpretted as sending a “0” bit). SWX being on keeps the flux in the core constant (zero volts over the winding) and the magnetisation current is circulated at low loss.
Any domains will be able to detect the “swashed” flyback pulse using its receive comparator. A receiver gets the databit value using a differential comparator to find 0V instead of finding either VDD (vboost) or typ 0.7V (the VBE voltage) as would be typical if all SWX switches were off.
It is important that there can be some guaranteed full flyback events - some that are not squashed -to preserve the floating VDD generation mechanism sufficient to power all of the CMOS ICs attached. One implemation is to hard-coded by design that every Nth (e.g 4) pulse will never be squashed. This reduces the date rate somewhat and also the reduction of Base drive current must be accomodated similar to as suggested previously for the data.
The Pre-Active protocol is very useful for setting up the domains ready for On/Off activity for example to configure them for how to implement the Active protol (which can therefore be soft) and setting current limits, temperature limits, setting which devices are to be switched On when the Active protocol begins etc. A programable logic similar to FPGA fabric could be incorporated onto the CMOS chip and devices uploaded over the Pre-Active protocol.
Active Protocol:
To actually turn on some of the power transistors, DomainO issues a Long-length-VDD pulse which is immediately and easily detected in all domains. Domainl will respond by starting the active mode where SWA and SWB switch in sequence to boostrap current to drive one or more transistors. Which switches are activated and in which round-robin timeslot depend on the databits previously sent during pre-active protocol. Again since the inductor flux is shared my the multiple windings in each domain a round-robin time-share the base current driving scheme could activating BASE1, the the next pulse goes to BASE2 and so on in each of the domains where transistors are to be turned on i.e. multiple transistors can be powered by the single magnetic core. Each transistor receives proportionally less average base current but still it is possible to adjust the PWM ratios so that each transistor gets a sufficiently low forced-beta level. Generally a 4-transistor bridge only two of the power transistors are turned on at a time. With a 50nS,25nS,25nS interval for Charge,Dischargel,Discharge2 two power transistors would be operated at a forced beta of approximately 4.
Even during Active mode, the data commincations are possible, if the addressed domain 'squashes' the flyback pulse thereby sending a detectable “1” one - using the same mechanism as was described for Pre-active mode. The downside is that by squashing a flyback pulse the current given to the transistor's base current is obviously reduced. This can be correct by Domainl where it can extending subsequent base drive pulses given to make up the shortfall.
Turn off (Active —> Quiescent mode change):
DomainO can very quickly turn off one or more or all power transistors without delay or contention using the 'Flyback squashing' mechanism. If SWX in any DomainO is active it can squash the base-current flyback events for all transistors connected to the single magnetic core since the magnetic core is shorted out during SWX time. The effect on the transistors is immediate but the state machines may take longer to respond perhaps when the power sequencing domains detect that the reserved VDD flyback pulse has been squashed the will revert back to Quiescent mode.
Indeed any domain could force other domains to turn off for example because of a fault (e.g. overtemperature, short circuit, stuck-on) by exerting its SWX which would also set Domainl to quiescent mode.
Multiple Active mode selection without intervening Turn-off event:
Some applications such as the dual-lifetime transistor require more than just On/Off sequencing of the transistors so extra control bits are needed.
Multiphase implementations.
For each of the circuits involving the inductors and cores there exists mutliphase versions where multiple independent inductive / electronic paths work in parallel but are sequenced to be phase offset from each other. Such circuits would be able to pass multiple bits in parallel if configured with the full compliment of logic. Ripple current is reduced, the size of the inductors is reduced and the effect of'flyback squashing' might be reduced if only 1 out of N phases is squashed to transmit a single-bit path of data.
Networking and interconnect.
Figl23 A places all the components of Figl22 together into a single module. It is also possible to create a monolithic silicon device with all the same pieces created in or on the substrate.
Coaxial square section ferrite tube construction running around the periphery of the stacked die. Effectively this scheme forms a network of intelligent addressable isolated power transistors bootstraping to gain all the necessary floating supplies at low cost.
Because CHARGE/DISCHARGE pulses are issued at rates 10MHz or above and each can transfer one bit of data a high data-ratedatastream is achieved which could carry information like voltage, temperature and current digitisations between the isolated domains for control or protection purposes. The signal levels are high current (on the order of amps) and highly immune to interference. CHARGE time - the device in each domain is able to participate in the CHARGE time once the domains become fully synchronous. Phase locked loops could be deployed to lock. Should for example two devices simultaneously route say 0.1V of VCAP voltage to their respective windings (they will lock together by transformer action) the current will be fed from two sources. Effectively the two windings are in series in terms of magnetising the core
Signal-only linkages and isolated inductors.
What was shown involved fully combining power and voltage distribution and signalling while it is entirely possible to use signal-only coupled inductors not intended to transmit BASE and/or VDD power or to have some sections using some domains using non-coupled inductors
Magnetics Design:
Fig 123B - On chip magnetics using nano-pores and TSV technology.
Nano-hole facility affords the possibility to make extremely high performance integrated inductors and transformers. A silicon wafer is etched with MacEtch or similar to produce through wafer nano-slots arranged into a torroidal arrangement. These slots can be ALD or Electrplated or wet chemical plated with a magnetic material which deposits on the surface first them plates outwards to fill the nano-slots. (Fig.l23B shows a much coarser view of the nano slots rather than those would actually be used) The silicon still retains its integrity but in the preferred radial magnetisation mode there are periodic discontinuities in the magnetic material affording a distributed airgap. Due to the very fine distributed structure and predominantly 1-dimensional aspect of the magnetic material eddy currents are suppressed. This allows use of high flux density magnetic materials including pure metals such as Iron, Nickel or Cobolt without risk of high eddy losses. Ferrite and other non-conductive materials are also possible.
Assuming the magnetic material of of relatively high permeability, the effective permiability is set by the total airgap length between the magnetic pieces and can be well controlled.
To make the conductive (typ. Copper) windings of the transformer a modification of TSV (through silicon via) technique is used similar to that mentioned before and possibly co-created with the contacts for the power transistors and this will produce vertical copper pillars which pass through the silicon substrate and can function as the vertical part of one or more spiral windings. The final step to create inductors or transformers are to form linkages from the inside copper pillars to the outside copper pillars in a pattern which creates one or more spiral windings.
Leakage inductance can be very low and isolation voltage between windings would be set by oxide (or other dielectric) thickness between the windings or else by depleted silicon if using doped holes. In the extreme, a nano/microporus silicon structure could be wet-oxidised to turn it into 100% Si02 - this could accommodate be infinitely (effectively) fine wires and ideally low skin and proximity effects.
Supeijunction Mosfet / .TFET / B.TT system using the through-wafer nanohole concept:
The concept of through-wafer lateral devices is depicted in relation to a supeijunction (SJ) [5] mosfet concept in Figl24 shown from above the wafer surface looking down at the through-silicon structures. The same concept can be applied to the drift region of JFET device or BJT device and this will be demonstrated. A through-wafer gate 'tube' is created using MacEtch or other technique and then this is thermally oxidised (or else ALD deposition of another gate dielectric could be used) before typically a polysilicon fill or even metal coating method to provide the gate electrode.
By using the ideas presented earlier for creating doped regions and profiles through the thickness of the wafer using nano/micro holes the doping patterns shown could result. AN type wafer with a P doped region underneath the MOS channel forms the mosfet control gate of a typically enhacement mode device (though depletion mode is possible with the correct implants). The other end of the channel enters into the drift region of the structure. Then OptionA a charge-compensating columns of Pmed (P medium doped) are formed with the peppered nano-hole, or nano-pore through-wafer MacEtch process explained with regard to the bipolar devices.
The N drift region could optionally be doped in a special way. Option B using the native N wafer doping and only dopes the Pmed columns for the super-junction effect. - doping with using selective conformal epitaxy of doped silicon (see Stanford paper) would achieve the doping needed and could be used to close up the nano holes. - Looking at OptionB, the purpose of the Pmed (P medium doping) regions is only to deplete the N drift region columns to give the blocking voltage rating but at the same time benefit of the higher wafer N doping during the conduction region of operation. The Pmed columns dont participate in majority-carrier conduction so the fact that the cylindrical or other shaped holes might not have low surface recombination velocity shouldnt affect operation. The only concern is that the P regions properly deplete and do not cause localised high voltage gradients. The choice of surface passivation of the holes is important - again a combination of ALD alumina and or silicon dioxide should be suitable.
It should be apparent that the construction has no constraints upon the drift region length which is now a lateral dimension unlike a normal super-junction mosfet where the pitch of the columnar structure is restricted by the etching tools capacity for producing deep trenches. Here the drift regions are 90degrees to a standard superjunction mosfet and the wafer thickness is decoupled from the drift region length. Wafer thickness just sets the effective “width” of the MOS device e.g. a 500u thick wafer using 50u lateral drift length would have lOx lower specific on resistance than a standard SJ vertical mosfet and be much easier to manufacture without special thin-wafer processing. Using nano sized holes e.g. lOOnm diameter, the column pitch could be reduced to below lum and with drift length of 80u from the graph Figl25 it should be possible to build mosfets many 1000's of volts rating with this method with less than single-digit specific on resistances in mOhm*cm2.
Another advantage of the super-junction concept is that any voltage rating device can be fabricated by adjustment of the drift length since the charge compensation mechanism scales linearly without needing to alter the drift doping at all.
Superiunction JFET. BJT, Cascodes A JFET differs from the Mosfet implementation only at the source side where instead of inversion of a thin channel of semiconductor, a pre-assigned channel is depleted by an adjacent junction to turn it on or off. JFET can be normally on or normally-off depending on the doping characteristics although by adding a low-voltage source-series typically MOS switch, a cascode circuit is created where a normally-on JFET characteristic is acceptable since the overall cascode is normally-off.
The Cascode circuit gives very fast switching characteristics.
Figl24E has a JFET. Figl24F is the JFET system reconfigured slightly to be driven in BJT mode where the base must exceed one diode-drop in order to turn on the device. BJT mode has the advantage of given conductivity modulation which can take the ON resistance below that of the normal super-junction drift region. JFET device also can be have its gate driven into forward bias whereby it injects minority-carriers into both the BASE and Drift regions substantially lowering conductivity when turned on. A nice feature of the Bipolar-Mode JFET is that it can very quickly be returned to JFET, majority-carrier mode before turnoff giving a tail-less turn off suitable for hard switching applications.
For all the devices mentioned, junction or trench isolation is possible between the devives and mix-and-match with opposite polarity mosfets and any other bipolar or other devices can be co-integrated.
Fractional current boost converter for VDD supply
With a JFET (or Mosfet) cascode system using normally-on power FETs it is easy to extract a VDD voltage supply while the switch is off since SOURCE will naturally rise to a voltage Vpinchoff when SWcascode is off. A diode and an LDO regulator is all that is needed to provide VDD from the Source voltage.
To provide VDD continuously while the switch is on, modifications to the previous descriptions of the I-MODE driver circuit for BJT type are beneficial. Diagram of a multi-element JFET device where a fraction of the elements, and therefore a fraction of the total drain current, are routed through an SWboost mos switch and an inductor which both can now can have a low current rating - Figl24G. The main power current path is switched by SWcascode without any added inductor and SWboost is switching some fraction of the drain current and forming a boost converter to provide VDD. For a BJT type of Bipolar-mode-JFET Fig. 124H is more appropriate.
Superiunction or normal Pin Diodes or Schottkv diodes
Methods of manufacture of PIN diodes of normal or super-junction type can be easily deduced from the figures since all of the structures have a PIN diode type structure which is supporting the voltage. PIN and Shottky diodes are useful to allow for handover from possibly slow reverse-conducting Imode switches in a bridge - especially in hard switching applications.
Summary:
As well as other benefits the main effectiveness of the Ultra-Lateral concept versus a thin-wafer vertical device can be seen by way of an example device. Assume a wafer thickness of 500u and with a lateral drift region length of 75u - typical for a 600V device - and assuming 50u length overhead for the CE and BASE regions (giving a 125u ring pitch) then a lcm2 area of power device would yield a cross-sectional conduction path area of 400mm2 rather than the 100mm2 of conduction path area for a vertical device, i.e. the device acheieves 4cm2 of transistor area for lcm2 of silicon area. Some of the die area could be given over to sophisticated driver and protection circuitry and still result in a smart-power IC of smaller dimensions and lower cost than current 'dumb' transistors.
[3] G.-F. Dalla Betta et al., Development of modified 3D detectors at FBK ffiEENucl. Sci. Conf. R. (NSS/MIC) (2010) 382 [4] Zhipeng Huang,Nadine Geyer,Peter Werner, Johannes de Boor, and Ulrich Gosele Adv.
Mater. 2011, 23, 285-308 [5] US patent 4754310
Claims (3)
- Claims 1. method of lateral Power transistor construction comprising Silicon planar substrate, sequential formation of arrays of through-holes in said silicon for purposes of creating tubular doping surfaces, doping said surfaces with either N or P type high temperature diffusions to create bipolar or JFET transistors where the doped array formations are patterned to create multiple parellel lateral transistor conduction paths and also form at least one enclosing bounding diffusion to support a high voltage lateral drift region.
- 2. a lateral power transistor according to claim 1 where additional through-hole array diffusions produce columns of doped material inline to the drift region voltage sustaining to act as a so-called Supeijunction mechanism where the net doping of the drift region is substantially higher than the normal maximum doping for a given breakdown voltage.
- 3. muliple lateral power transistors according to claim 1 or 2 constructed upon a single monolithic silicon substrate isolated from each other by multiple bounding diffusions to support a high voltage between devices on same substrate.
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| WO2018109452A1 (en) * | 2016-12-12 | 2018-06-21 | John Wood | Lateral power transistor comprising filled vertical nano- or micro-holes and manufacture thereof |
| US11411557B2 (en) | 2020-05-18 | 2022-08-09 | Ideal Power Inc. | Method and system of operating a bi-directional double-base bipolar junction transistor (B-TRAN) |
| US11496129B2 (en) | 2020-06-08 | 2022-11-08 | Ideal Power Inc. | Method and system of current sharing among bidirectional double-base bipolar junction transistors |
| US11637016B2 (en) | 2013-12-11 | 2023-04-25 | Ideal Power Inc. | Systems and methods for bidirectional device fabrication |
| US11777018B2 (en) | 2020-11-19 | 2023-10-03 | Ideal Power Inc. | Layout to reduce current crowding at endpoints |
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| EP1128441A2 (en) * | 2000-02-21 | 2001-08-29 | Hitachi, Ltd. | Semiconductor devices comprising a SOI bipolar transistor and corresponding manufacturing methods |
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| US11637016B2 (en) | 2013-12-11 | 2023-04-25 | Ideal Power Inc. | Systems and methods for bidirectional device fabrication |
| WO2018109452A1 (en) * | 2016-12-12 | 2018-06-21 | John Wood | Lateral power transistor comprising filled vertical nano- or micro-holes and manufacture thereof |
| GB2572702A (en) * | 2016-12-12 | 2019-10-09 | Wood John | Lateral power transistor comprising filled vertical nano- or micro-holes and manufacture thereof |
| GB2572702B (en) * | 2016-12-12 | 2022-06-01 | Wood John | Adiabatic gate/base driver circuit |
| AU2017374758B2 (en) * | 2016-12-12 | 2022-08-11 | John Wood | Lateral power transistor comprising filled vertical nano- or micro-holes and manufacture thereof |
| US11411557B2 (en) | 2020-05-18 | 2022-08-09 | Ideal Power Inc. | Method and system of operating a bi-directional double-base bipolar junction transistor (B-TRAN) |
| US11804835B2 (en) | 2020-05-18 | 2023-10-31 | Ideal Power Inc. | Method and system of operating a bi-directional double-base bipolar junction transistor (B-TRAN) |
| US11496129B2 (en) | 2020-06-08 | 2022-11-08 | Ideal Power Inc. | Method and system of current sharing among bidirectional double-base bipolar junction transistors |
| US11777018B2 (en) | 2020-11-19 | 2023-10-03 | Ideal Power Inc. | Layout to reduce current crowding at endpoints |
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