GB2444093A

GB2444093A - Providing power from a piezoelectric source

Info

Publication number: GB2444093A
Application number: GB0623324A
Authority: GB
Inventors: Richard Brown
Original assignee: Measurement Specialties Europe
Current assignee: Measurement Specialties Europe
Priority date: 2006-11-22
Filing date: 2006-11-22
Publication date: 2008-05-28
Anticipated expiration: 2026-11-22
Also published as: GB2444093B; GB0623324D0

Abstract

An apparatus for providing a potential from a piezoelectric source 50 to an output 120 includes a first array 150 of capacitive elements 155 switchably 110 coupled to the piezoelectric source, the elements of the first array being selectively connectable to one another in series and in parallel; a second array 200 of capacitive elements 205 switchably coupled to the piezoelectric source, the elements of the second array being selectively connectable to one another series and in parallel. The first and second arrays are adapted to be connected in parallel.

Description

METHOD AND APPARATUS FOR PROVIDING POWER TO AN

ELECTRONIC SYSTEM

FIELD OF INVENTION

[00011 The present invention relates to electronics, and particularly to a method and apparatus for providing power.

BACKGROUND

(0002] Various methods have been developed in the prior art for converting energy in a non-electrical form into electrical energy using charge generators.

One example of a charge generator is a piezoelectric generator. A piezoelectric generator mayreceive an applied force, and output a voltage. When a piezoelectric generator Is provided for output to a device, there Is typically a mismatch between the voltage of the charge generated by a piezoelectric source, and a voltage which the device may employ. By way of example, piezoelectric elements, one or more of which may constitute a piezoelectric source, may provide an output voltage of hundreds of volts. Devices may run on lower voltages. Accordingly, it is necessary to step down the voltage.

3] In the prior art, a capacitor, of relatively large value, is employed as a storage medium between the piezoelectric source and the device. However, there is a large loss of energy between the source and the storage capacitor when the storage capacitor is initially uncharged. A rectification system is provided intermediate the storage capacitor and the piezoelectric source, so that generated signals of either polarity can charge the storage capacitor. I)

(0004] U.S. Patent No. 6,407,483 (NJunuparov, et al.) attempts to resolve this problem by providing a charge energy converter having capacitors, and a switching device which can connect the capacitors in series to store charges and in parallel to reduce the potential at an output. However, such a switched array is relatively inefficient.

SUMMARY OF THE INVENTION

5] In one embodiment of the invention, an apparatus for providing power to an electronic system from a piezoelectric source comprises a first array of capacitive elements switchingly coupled to the piezoelectric source, the elements of the first array being selectively connectable to one another in series and in parallel; and a second array of capacitive elements switchingly coupled to the piezoelectric source, the elements of the second array being selectively connectable to one another in series and in parallel; wherein the first and the second arrays are adapted to be connected in parallel to the output.

(0006] In an another embodiment of the invention, a method for providing power to an electronic system includes the steps of connecting a first array of capacitive elements to the source, said capacitive elements of said first array being connected to one another in series; disconnecting the first array from the source; connecting the capacitive elements of the first array to one another in parallel; connecting a second array of capacitive elements to the source, said capacitive elements of the second array being connected to one another in series; disconnecting the second array from the source: connecting the capacitive elements of the second array to one another in parallel and connecting the first and the second array to the output.

BRIEF DESCRIPTION OF THE DRAWINGS

7] Fig. 1 is a block diagram showing components of an apparatus for providing power in accordance with an embodiment of the invention.

8] Fig. 2 is a flow diagram illustrating a method in accordance with an implementation of the invention.

9] Fig. 3 is a block diagram illustrating an embodiment of the invention.

(0010] Fig. 4 is a circuit diagram of an exemplary array in accordance with an embodiment of the invention, showing the capacitive elements connected in series.

1] Fig. 5 is a diagram of the exemplary array of Fig. 4, showing the capacitive elements connected in parallel.

DETAILED DESCRIPTiON

2] Referring to Fig. 1, an apparatus 100 for providing power from a piezoelectric source to an output In accordance with an embodiment of the invention will now be described. Apparatus 100 is coupled to piezoelectric source 50. Apparatus 100 includes first array 150 of capacitive elements and second array 200 of capacitive elements. First array 150 and second array 200 are coupled through switch 110 to piezoelectric source 50. First array 150 and second array 200 are coupled through switch 120 to output 300.

3] Switches 110 and 120 may be configured to connect a single one of arrays 150, 200 between source 50 and output 300. Alternatively, switches 110 and 120 may be configured to connect arrays 150, 200, in parallel, between source 50 and output 300.

4] First array 150 has at least two capacitive elements 155. Capacitive elements 155 may be connected to one another either in series or in paralleI Second array 200 has at least two capacitive elements 205. Capacitive elements 205 may be connected to one another either in series or in parallel.

5] Referring now to Fig. 2, there will be described a process flow of an exemplary process of providing power from a piezoelectric source to an output employing an apparatus 100 (Fig. 1). In a first step, indicated at block 400, first airay of capacitive elements 150 is connected to source 50, with capacitive elements 155 connected in series. The first array 150 may remain connected to source 50, with capacitive elements 155 in series, while capacitive elements 155 become charged, and may remain connected to source 50, with capacitive elements 155 in series, until capacitive elements 155 are each fully or substantially fully charged, e.g. until capacitive elements 155 in series reach voltage equilibrium with source 50. First array 150 of capacitive elements 155 is then disconnected from source 50, as indicated at block 405.

(0016] Second array 200 of capacitive elements 205 is then connected to source 50, with capacitive elements 205 connected in series, as indicated at block 415. Second array 200 may remain connected to source 50, with capacitive elements 205 connected in series, until capacitive elements 205 are each fuHy or substantially fully charged, e.g. capacitive elements 205 in series reach voltage equilibrium with source 50. Second array 200 of capacitive elements 205 is then disconnected from source 50, as indicated at block 420. At this time, the charging process is complete, and discharging to the output may begin. Capacitive elements 155 may then be connected to output terminals in parallel, as indicated at block 420. Capacitive elements 205 may then be connected to output terminals in parallel, as indicated at block 425.

7] Referring now to Fig. 3, there is shown an exemplary embodiment of an apparatus according to the invention. Refenirig to Fig. 3, apparatus 500 is coupled to piezogenerator 505. Piezogenerator 505 is coupled to apparatus 500 via rectifier bridge 510. One output of rectifier bridge 510 is coupled to an input of switch 515. Each output of switth 515 is coupled to a signal input of a demultiplexer 520, 525. In the embodiment of Fig. 3, switch 515 has two outputs, and there are two demultiplexers 520, 525. However, there may be more than two switched outputs and more than two demuttiplexers. Each demultiplexer 520, 525 demultiplexes the signal received from piezogenerator 505 via rectifier bridge 510 and switch 515 and furnishes the signal to a corresponding array of capacitive elements 550, 560. Select inputs for demultiplexers 520, 525 are provided by timing and control logic 530, discussed below. In the illustrated embodiment, demultiplexer 520 has eight output channels, each of which is coupled to an input of one of arrays 550 through 557 of capacitive elements.

Similarly, demultiplexer 525 has eight output channels, each of which is coupled to an input of one of arrays 560 through 567 of capacitive elements.

8] In the iUustrated embodiment, the timing and control logic 530 controls functions, including the operation of the switch 515, i.e. whether the first output of the bridge 510 is connected to demultiplexer 520 or demultiplexer 525. To provide this functionality, an output of timing and control logic 530 is coupled to a control input of switch 515. Timing and control logic 530 also has outputs 531, 532 coupled to select inputs of demultiplexers 520, 525, respectively. Timing and control logic 530 provides via outputs 531, 532, signals to control demultiplexers 520, 525, and thereby controls the timing and selection of providing demultiplexed output signals to arrays 550 to 557 and 560 to 567.

Demultiplexers 520, 525 serve as switches to distribute the output from piezogenerator 505 to the various arrays 550 to 557 and 560 to 567. It will be appreciated that suitable switches may be employed as an alternative to demultiplexers 520, 525. The second output of bridge circuit 510 is coupled to each array 550 to 557, and 560 to 567, and is not demultiplexed.

(00191 Each array 550 to 557 and 560 to 567 is coupled to two output terminals 570, 571.

(00201 Timing and control logic 530 also has output 533 coupled to arrays 550 to 557, and output 534 coupled to arrays 560 to 567. Timing and control logic 530 provides a control signal on output 533 to operate switches in array 550 to 557 so as to cause capacitive elements In each array 550 to 557 to be connected either in series between the outputs of bridge circuit 510, or in parallel between output terminals 570, 571. f

1] Timing and control logic 530 may be a suitable programmable processor. "Processor", as used herein, generally refers to a circuit arrangement that may be contained on one or more silicon chips, and/or integrated circuit (IC) boards, and that contains a Central Processing Unit (CPU). The CPU may generally include an arithmetic logic unit (ALU), which performs arithmetic and logical operations, and a control unit, which extracts instructions from memory and decodes and executes them, calling on the ALU when necessary.

[00221 The processor may take the form of a microprocessor. The present invention is operable with computer storage products or computer readable media that contain program code for performing the various computer-implemented operations. The computer-readable medium is any data storage device that can store data which can thereafter be read by a computer system such as a microprocessor. The media and program code may be those specially designed and constructed for the purposes of the present invention, or they may be of the kind well known to those of ordinary skill in the computer software arts.

Examples of computer-readable media include, but are not limited to magnetic media such as hard disks, floppy disks, and magnetic tape; optical media such as CD-ROM disks; magneto-optical media; and specially configured hardware devices such as application-specific integrated circuits (ASICs), programmable logic devices (PLDs), and ROM and RAM devices. Examples of program code include both machine code, as produced, for example, by a compiler, or files containing higher-level code that may be executed using an interpreter.

(0023] Referring now to Figs. 4 and 5, there Is shown an exemplary circuit diagram of an array 550 of Fig. 1. In Fig. 4, array 550 is shown with capacitive elements 655, 660... 665 connected in series, and in Fig. 5, the array 150 is shown with elements 655, 660, ... 665 connected in parallel. An input from demultiplexer 520 (of Fig. 3) is shown at 620. The output directly from bridge circuit 510 (of Fig. 3) is shown at 610. A line carrying a signal from timing and control logic 530 (of Fig. 3) is shown at 630. Lines to output terminals 570, 571 (of Fig. 3) are shown at 670, 671. First capacitive element 655 has first terminal 656 and second terminal 657. First switch 658 connects first terminal 656 alternatively to demultiplexer input 620, which carries an input from the piezoelectric source, and to second output line 671. Second switch 659 connects second terminal 657 alternatively to first output line 670 and via a switch as described below, to a first terminal of intermediate capacitive element 660.

4] Array 550 has one or more intermediate capacitive elements 660.

Each intermediate capacitive element 660 has first terminal 661 and second terminal 662. Array 550 further has a final capacitive element 665, havIng first terminal 666 and second terminal 667.

5] Each intermediate capacitive element 660 has first switch 663 for connecting first terminal 661 to second terminal 657 of first capacitive element 655, or to second terminal 662 of a preceding one of the intermediate capacitive elements 660, and to first output line 671. Each intermediate capacitive element 660 also has second switch 664 for connecting second terminal 662 to first output line 670 and either to first terminal 666 final capacitive element 665 or to first terminal 661 of a next one of the intermediate capacitive elements 660.

Final capacitive element 665 has first switch 668 for connecting first terminal 666 to second output line 671 and to second terminal 662 of a preceding one of intermediate capacitive elements 660, and a second switch 669 for connecting second terminal 667 to first output line 670 and line 610 which is an input from the piezoelectric source. It will be appreciated that first capacitive element 655, intermediate capacitive elements 660 and final capacitive elements 665 may be connected in series between lines 610 and 620 from the piezoelectric source, and in parallel between first output line 670 and second output line 671.

6] There will be described in detail the charging and discharging of capacitive elements 655, 660, 665 of array 150. When capacitive elements 655, 660, 665 are charging from the source 50, they are connected in series, as shown in Fig. 4. First capacitive element 655 is connected, at its first terminal 656, by first switch 658 to line 620 from the piezoelectric source, and at its second terminal 657 by second switch 659 to first terminal 661 of a first intermediate capacitive element 660, via first switch 663 of first intermediate capacitive element 660. Second terminal 662 of first intermediate capacitive element 660 is coupled by its second switch 664 to first terminal 661 a of second intermediate capacitive element 660a, via first switch 663a. Second terminal 662a of second intermediate capacitive element 660a is coupled by switch 664a to a first terminal of a next intermediate capacitive element (not shown), and so on until a second terminal of an intermediate capacitive element is coupled to a first temilnal 666 of final capacitive element 665 via first switch 668. Second terminal 667 of final capacitive element 665 is coupled to line 610 coupled to a positive input of piezoelectric source 50. Thus, each capacitive element of array 550 is coupled in series between positive and negative terminals of the piezoetectric source. During charging, as in Fig. 4, the output lines 670, 671 are not coupled to the capacitive elements of the array.

7] Referring now to Fig. 5, array 550 is shown having capacitive elements connected in parallel between positive and negative terminals of an output, via lines 670, 671. First terminal 656 of first capacitive element 655 is coupled via switch 658 to line 671. Second terminal 657 is coupled via switch 659 to line 670. First terminal 661 of each intermediate capacitive element 660 is coupled via switch 663 to line 671. Second terminal 662 of each intermediate capacitive element 660 is coupled via switch 664 to line 670. First terminal 666 of final capacitive element 665 is coupled via switch 668 to line 671. Second terminal 667 of final capacitive element 665 is coupled via switch 669 to line 670.

8] Thus, capacitive elements 655, 660, 665 are connected in series between positive and negative outputs of the piezoelectric source when charging.

When capacitive elements 655, 660, 665 are discharging, they are connected in parallel to the output terminals by lines 670, 671, connected to respective output terminals, as shown in Fig. 5.

[00293 The switches may include virtually any type of switch mechanism, such as double pole, double throw mechanical switches, analog switches provided by MOSFETs, for example, or other switch types as understood by one skilled in the arts. The MOSFETs may have a design which provides a relatively low on resistance. Those of skill in the art of the design of MOSFETs are aware of design parameters which result in a relatively low on resistance. By way of example, a relatively high ratio of gate width to gate length may provide a r&atively low on resistance. Control line 630 carries control signals from timing and control logic 630 to each switch.

0] The efficiency of an exemplary apparatus in accordance with an embodiment of the present invention will now been explained. Consider, only as an example, the piezoelectric generator 505 having a capacitance C0 of 10 nano Farad (unF) and produce (under open circuit condition) a positive-going pulse with a peak amplitude VP of 100 Volts (UVP?) when excited by a mechanical stimulus. The charge Q, in micro Coulomb ("pC"), present in the generator 505 at that instant and the peak energy level Wi,, micro Joule ("pJ), reached by the generator under this open-circuit condition can be calculated as: Q=C0V=(10nF)x(100V)=1 pC.

W /2C0V2 = 1/2 x (10 nF)x (100 V)2 = 50 pJ.

1] Suppose the charge is completely removed from the generator when the mechanical stimulus is at its peak value. Now, when the mechanical force reduces to zero, a corresponding negative voltage of - 100 V will be generated and the energy level will reach a peak of 50 pJ. Thus, theoretically the generator can provide a maximum total energy of 100 1jJ from a single mechanical stimul us.

(0032] To understand the increase in efficiency of energy gain possible from an embodiment of the present invention, first consider connecting a single switched capacitor array having same series capacitance as the generator, since that is the optimum value for a single, one-shot connection to the generator.

When an uncharged single switched capacitor array with capacitance of 10 nF is connected, the total charge of 1 pG will be shared across a total capacitance of nF, a resultant voltage of 50 V will be produced, as shown below: Vp=Qp/(C0nF+lOnF)1 pC/(lOnF+lOnF)=50V.

[0033J The energy stored in the 10 nF single switched capacitor array as well as the generator would be given by: Ws = 1/2CSVp2 = Y2 x 10 nF x (50 V)2 = 12.5 pJ.

W9 = 1/2CgVp2 = 1/2 x 10 nF x (50 2 12.5 pJ.

Such an array can extract only 12.5 pJ out of a total 100 pJ theoretically possible, giving an efficiency ratio of 12.5%.

4] Secondly, if an uncharged load capacitor of 1 nF were connected to the generator, the total charge of 1 pG would be shared across a total capacitance of 11 nF, a resultant voltage of 90.91 V would be produced, as shown by the calculation below: VP = QP/(GO nF + I nF) = I pCI(10 nF + I nF) = 90.91 V. (00353 The energy stored in the 1 nF load capacitor as well as the generator at this instant would be given by: W1Y201VP2=1/zx 1 nFx(90.91 = 4.13 pJ.

Wg=YzCgVp2=lAxlOnFx(90.9IV)241.3pJ.

6] Now, if the I nF load were removed and another uncharged load of I nF were connected to the generator, the generator now would have a total charge of 0.909 p0, which would be again be shared across a total capacitance of 11 nF, resulting in a voltage of 82.64 V. The energy stored in the second load of I nF would be 3.42 pJ, while the generator would still have about 34.2 pJ.

7] If this process were repeated many times in a short period of time, relative to the mechanical input signal, it can be shown that the fractional energy accumulated would be given by the sequence: 1 10 100 ____ + +...±+...

12.1 12.12 12.1 12.1 (0038] it may be shown that this sequence has a sum to infinity of 0.4762, meaning that in this case 47.6% of the energy originally present may be removed and stored.

9] If instead of a single load of I nF, the array 550 of a large number of smaller unit capacitance, connected in series, is used at each progressive step, the final percentage of stored energy can be taken as high as 50 %. A more favorable sequence of unit capacitances for the case of the 10 nF generator is found to be: 1 nF, 2 nF, 3 nF... 6 nF (using a sequence of 6 steps to progressively discharge the generator). Although the sequence of fractional energy is not a geometrical progression in this case, it can be calculated numericafly to give the sum to infinity of 0.436 (43.6%), and over 97% of this avaUabie energy is collected within the first 6 steps (giving 42.4% yield).

(0040] In cases where electrical energy is to be harnessed from a piezoelectnc generator, it is common to find that the open-circuit voltage produced by the generator is greater than the desired target voltage for subsequent use, by a factor of several orders of magnitude. For example, a piezoelectnc element may generate hundreds of volts under open-circuit conditions, but the downstream e'ectronic network that is to be powered by the generator may require a supply voltage of just a few volts. Assume that the target voltage for storage in this case is 5 V. Meanwhile, the sequence of combined generator and toad voltages during the progressive discharge in this case is: 90.9, 75.8, 58.3, 41.6, 27.8, 17.3 [0041] Using an array of capacitors, in the first case 18 cells each of 18 nF, connected initially in series, instead of a single fixed component, the 90.9 V is shared evenly across the 18 cells, giving 5.05 V across each individual cell.

Once charged, the cells are then disconnected from the generator, and reconnected into a parallel grouping, with total capacitance now of 324 nF and total potential difference of 5.05 V. The stored energy is 4.13 pJ, exactly as for the series combination. Therefore, assuming no loss is incurred during the switching operation, an initial high voltage from low capacitance has been transformed into a low voltage from a higher capacitance. This is one of the advantages of the invention.

2] Similar experimentation has yielded another sequence of 6 steps with good energy yield (42.5 % within 6 steps) and has adjusted out unit cell values that are integer multiples of 10 nF.

An exemplary composition of the series toad capacances in arrays 550 through 555, is as follows: 550) Total series C: 1.11 nF: 18 cells at 20 nF/cell total parallel C: 360 nF 551) 2.0,iF: 15 cells at 30 nF/celI total parallel C: 450 nF 552) 2.5 nF: 12 cells at 30 nF/cell total parallel C: 360 nF 553) 5 nE: 8 cells at 40 nF/cell total parallel C: 320 nF 554) 6 nF: 5 cells at 30 nFIcell total parallel C: 150 nF 555) 6.67 nF: 3 cells at 20 nF/cell total parallel C: 60 nF In this case, the voltage discharge sequence (starting from 100 V as before) is: 90V, 75V, 60V, 40V, 25V, 15V [0043] It will be appreciated that the number of arrays, total series capacitances, total parallel capacitances, numbers of capacitive elements or cells in each array, and capacitances of individual elements or cells, is merely exemplary. The arrays may have inversely related total series capacitance and total parallel capacitance. By way of example, the first array may have lower total series capacitance than the next array, and each array in turn may have lower total series capacitance than the next array, with a final array having the highest total series capacitance. The first array may have greater total parallel capacitance than the next array, and each array may have greater total parallel capacitance than the succeeding array, with the final array having the lowest total parallel capacitance. By way of example, the first array may have the greatest number of capacitive elements, and each array in turn having more capacitive elements than next array, with the final array having the smallest number of capacitive elements.

4] The dernultiplexer 520, with the input from the Timing and Control Logic 530 controls the progressive discharge of the piezogenerator 505 by connecting and disconnecting the arrays 550 through 557. Once the array 550 is disconnected from the piezogenerator 505, the Timing and Control Logic 530 will switch the unit capacitive cells from a series connection to a parallel connection for discharging at low voltage and higher capacitance.

5] Returning now to the discharged piezogenerator 505, it should be noted that there is a residual voltage still present after the last discharge step.

This small residual voltage represents very little stored energy, and it is desirable to discharge this directly (e.g. via short-circuit) prior to proceeding with the next step, since the next excursion of the generator will swing in opposite direction, and the maximum negative extent is advantageous.

[00461 The piezogenerator 505 was discharged at instant of peak stress, and the voltage across it is now zero. But the mechanical input will now reduce from maximum value back to zero, and this will create a negative-going transition with same magnitude as the original positive (zero to peak value) swing.

7] Since the piezogenerator 505 is connected via the bridge rectifier 510, it is possible to harness this transition in exactly the same way as the initial transition. The Switch 515 will now connect the demultiplexer 525 to the bridge rectifier 510. The first series array 560 (using same step sequence as for positive-going transition) may already be connected (it can be connected after the final discharge in the previous sequence). When a peak value is reached across this array, it is disconnected, switched into parallel mode, and the second and progressive arrays, 561 through 567, are connected in sequence as before.

(0048] Changing the step-down ratio and/or the generator capacitance may require different step sequences, as the cell voltages must be maintained at a near-constant value. More steps may be required to discharge a higher generator capacitance, or the step size (each load capacitance value) can be selected to suit. Fig. 3 shows only in an exemplary manner an eight (8) step progressive discharge.

(0049] One of the advantages of the present invention thus includes an increase in efficiency of energy extraction from 12.5 % to a theoretical high of 50%. This makes it possible to extract maximum possible energy from just a single mechanical stimulus. After the mechanical input Increases from zero to maximum, the generator is discharged at the peak stress by the first group of arrays and the voltage across the generator is now zero. When the mechanical input reduces from the maximum to zero, a voltage with opposite polarity, but same magnitude, will be generated across the generator. The second group of arrays will discharge the generator and extract similar magnitude of energy as did the first group of arrays, thereby doubling the total amount of energy theoretically available for extraction. This is another advantage of this invention.

This invention thus enables one to extract more energy from a larger reservoir of

energy compared to that from prior art.

(0050] While the foregoing invention has been described with reference to the above embodiments, various modifications and changes can be made without departing from the spirit of the invention. Accordingly, aH such modifications and changes are considered to be within the scope of the appended claims.

Claims

An apparatus for providing power from a piezoelectric source to an output, comprising: a first array of capacitive elements switchingly coupled to the plezoelectric source, said elements of said first array being selectively connectable to one another in series and in parallel: and a second array of capacitive elements switchingly coupled to the piezoelectric source, said elements of said second array being selectively connectable to one another in series and in parallel; wherein said first and second arrays are adapted to be connected in parallel to an output.
2. The apparatus of claim 1, further comprising: a demultiplexer, a signal input of said demultiplexer connected to said piezoelectric source, a first output of said demuitiplexer connected to said first array and a second output of said demultiplexer connected to said second array.
3. The apparatus of claim 1, further comprising: a timing and control logic connected to said first and second arrays, said timing and control logic capable of controlling whether said capacitive elements of said first and second arrays are connected in series or in pa raVel.
4. The apparatus of claim 1, wherein said first array further comprises: a first capacitive element having first and second terminals, a first switch connecting said first terminal to a first input of said source and to a first output; at least one intermediate capacitive element, each of said at least one intermediate capacitive elements having first and second terminals; and a final capacitive element having first and second terminals; said first capacitive element having a first switch for connecting said first terminal to one input of said source and to a first output, and a second switch for connecting said second terminal to a second output and to said first terminal of one of said intermediate capacitive elements; each of said intermediate capacitive elements having a first switch for connecting said first terminal to said second terminal, either of said first capacitive element or a preceding one of said intermediate capacitive elements, and to said first output, and a second switch for connecting said second terminal to said first output and to said first terminal, either of said final capacitive element or of a next one of said intermediate capacitive elements; and said final capacitive element having a first switch for connecting said first terminal to one input of said source and to a first output, and a second switch for connecting said second terminal to a second output and to said first terminal of one of said intermediate capacitive elements.
5. The apparatus of claim 4, wherein said first and second switches are Single Pole, Double Throw switches.
6. The apparatus of claim 4 wherein said first and second switches are MOSFET switches.
7. The apparatus of claim 1, further comprising a rectifier connected intermediate said piezoelectric source and said first and second arrays.
8. The apparatus of claim 1, further comprising: a third array of capacitive elements switchingly coupled to the piezoelectric source, said elements of said third array being selectively connectable to one another in series and in parallel; and a fourth array of capacitive elements switchingly coupled to the piezoelectric source, said elements of said fourth array being selectively connectable to one another in series and in parallel.
9. The apparatus of claim 8, further comprising: a switch capable having an input connected to said source and a first and second outputs; a first demultiplexer, an input of said first demultiplexer connected to said first output of said switch, a first output of said first demultiplexer connected to said first array and a second output of said first demultiplexer connected to said second array; and a second demultiplexer, an input of said second demultiplexer connected to said second output of said switch, a first output of said second demultipiexer connected to said third array, and a second output of said second demultipexer connected to said fourth array.
10. The apparatus of claim 9, further comprising a timing and control logic connected to said first and second demuitiplexers and to said first, second, third and fourth arrays, said timing and logic control capable of connecting said capacitive elements of said first, second, third and fourth arrays in series and in parallel.
11. The apparatus of claim 8, wherein a total series capacitance of said first array is less than a total series capacitance of said second array; the total series capacitance of said second array is less than a total series capacitance of said third array; the total series capacitance of said third array is less than a total series capacitance of said fourth array; a total parallel capacitance of said first array is greater than a total parallel capacitance of said second array; a total parallel capacitance of said second array is greater than a total parallel capacitance of said third array; and a total parallel capacitance of said third array is greater than a total parallel capacitance of said fourth array.
12. A method for providing power from a piezoelectric source to an output, comprising the steps of: (a) connecting a first array of capacitive elements to the source, said capacitive elements of said first array being connected to one another in series; (b) disconnecting said first array from the source; (C) connecting said capacitive elements of said first array to one another in parallel; (d) connecting a second array of capacitive elements to the source, said capacitive elements of said second array being connected to one another in series; (e) disconnecting said second array from the source; (1) connecting said capacitive elements of said second array to one another in parallel; and (g) connecting said first and second arrays in parallel to the output.
13. The method of claim 11, further comprising the steps of: connecting a third array of capacitive elements to the source, said capacitive elements of said third array being connected to one another in series; disconnecting said third array from the source; connecting said capacitive elements of said third array to one another in parallel; connecting a fourth array of capacitive elements to the source, said capacitive elements of said fourth array being connected to one another in series; disconnecting said fourth array from the source; connecting said capacitive elements of said fourth array to one another in parallel; and connecting said third and fourth arrays in parallel to the output.
14. The method of claim 12, wherein said steps of connecting and disconnecting said third and fourth arrays from the source are performed by a demultiplexer.
15. The method of claim 13 whereIn a timing and logic control provides select inputs to said demultiplexer.
16. The method of claim 12 wherein said steps of connecting said capacitive elements of said first, second, third and fourth arrays in parallel to one another are controlled by a timing and logic control.
17. The method of claim 11, further comprising the step of rectifying a signal from said piezogenerator.
18. A method for providing power from a piezogenerator source substantially as herein before described with reference to the drawings.
19. Apparatus for providing power from a piezogenerator sourse substantially as herein before described with reference to the drawings.